1/*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <errno.h>
24#include <xf86drm.h>
25#include <nouveau_drm.h>
26#include "util/format/u_format.h"
27#include "util/format/u_format_s3tc.h"
28#include "util/u_screen.h"
29#include "pipe/p_screen.h"
30#include "compiler/nir/nir.h"
31
32#include "nv50/nv50_context.h"
33#include "nv50/nv50_screen.h"
34
35#include "nouveau_vp3_video.h"
36
37#include "nv_object.xml.h"
38
39/* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
40#define LOCAL_WARPS_ALLOC 32
41/* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
42#define STACK_WARPS_ALLOC 32
43
44#define THREADS_IN_WARP 32
45
46static bool
47nv50_screen_is_format_supported(struct pipe_screen *pscreen,
48                                enum pipe_format format,
49                                enum pipe_texture_target target,
50                                unsigned sample_count,
51                                unsigned storage_sample_count,
52                                unsigned bindings)
53{
54   if (sample_count > 8)
55      return false;
56   if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
57      return false;
58   if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
59      return false;
60
61   if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
62      return false;
63
64   /* Short-circuit the rest of the logic -- this is used by the gallium frontend
65    * to determine valid MS levels in a no-attachments scenario.
66    */
67   if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
68      return true;
69
70   switch (format) {
71   case PIPE_FORMAT_Z16_UNORM:
72      if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
73         return false;
74      break;
75   default:
76      break;
77   }
78
79   if (bindings & PIPE_BIND_LINEAR)
80      if (util_format_is_depth_or_stencil(format) ||
81          (target != PIPE_TEXTURE_1D &&
82           target != PIPE_TEXTURE_2D &&
83           target != PIPE_TEXTURE_RECT) ||
84          sample_count > 1)
85         return false;
86
87   /* shared is always supported */
88   bindings &= ~(PIPE_BIND_LINEAR |
89                 PIPE_BIND_SHARED);
90
91   if (bindings & PIPE_BIND_INDEX_BUFFER) {
92      if (format != PIPE_FORMAT_R8_UINT &&
93          format != PIPE_FORMAT_R16_UINT &&
94          format != PIPE_FORMAT_R32_UINT)
95         return false;
96      bindings &= ~PIPE_BIND_INDEX_BUFFER;
97   }
98
99   return (( nv50_format_table[format].usage |
100            nv50_vertex_format[format].usage) & bindings) == bindings;
101}
102
103static int
104nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
105{
106   const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
107   struct nouveau_device *dev = nouveau_screen(pscreen)->device;
108   static bool debug_cap_printed[PIPE_CAP_LAST] = {};
109
110   switch (param) {
111   /* non-boolean caps */
112   case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
113      return 8192;
114   case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
115      return 12;
116   case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
117      return 14;
118   case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
119      return 512;
120   case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
121   case PIPE_CAP_MIN_TEXEL_OFFSET:
122      return -8;
123   case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
124   case PIPE_CAP_MAX_TEXEL_OFFSET:
125      return 7;
126   case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
127      return 128 * 1024 * 1024;
128   case PIPE_CAP_GLSL_FEATURE_LEVEL:
129      return 330;
130   case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
131      return 330;
132   case PIPE_CAP_ESSL_FEATURE_LEVEL:
133      return class_3d >= NVA3_3D_CLASS ? 310 : 300;
134   case PIPE_CAP_MAX_RENDER_TARGETS:
135      return 8;
136   case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
137      return 1;
138   case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
139      return NV50_MAX_GLOBALS - 1;
140   case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
141   case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
142      return 8;
143   case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
144      return 4;
145   case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
146      return 64;
147   case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
148      return 4;
149   case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
150   case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
151      return 1024;
152   case PIPE_CAP_MAX_VERTEX_STREAMS:
153      return 1;
154   case PIPE_CAP_MAX_GS_INVOCATIONS:
155      return 0;
156   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
157      return 1 << 27;
158   case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
159      return 2048;
160   case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
161      return 2047;
162   case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
163      return 256;
164   case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
165      return 16; /* 256 for binding as RT, but that's not possible in GL */
166   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
167      return 256; /* the access limit is aligned to 256 */
168   case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
169      return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
170   case PIPE_CAP_MAX_VIEWPORTS:
171      return NV50_MAX_VIEWPORTS;
172   case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
173      return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
174   case PIPE_CAP_ENDIANNESS:
175      return PIPE_ENDIAN_LITTLE;
176   case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
177      return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
178   case PIPE_CAP_MAX_WINDOW_RECTANGLES:
179      return NV50_MAX_WINDOW_RECTANGLES;
180   case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
181      return 16 * 1024 * 1024;
182   case PIPE_CAP_MAX_VARYINGS:
183      return 15;
184   case PIPE_CAP_MAX_VERTEX_BUFFERS:
185      return 16;
186   case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
187      return 512 * 1024; /* TODO: Investigate tuning this */
188   case PIPE_CAP_MAX_TEXTURE_MB:
189      return 0; /* TODO: use 1/2 of VRAM for this? */
190
191   case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
192   case PIPE_CAP_SUPPORTED_PRIM_MODES:
193      return BITFIELD_MASK(PIPE_PRIM_MAX);
194
195   /* supported caps */
196   case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
197   case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
198   case PIPE_CAP_TEXTURE_SWIZZLE:
199   case PIPE_CAP_TEXTURE_SHADOW_MAP:
200   case PIPE_CAP_NPOT_TEXTURES:
201   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
202   case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
203   case PIPE_CAP_ANISOTROPIC_FILTER:
204   case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
205   case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
206   case PIPE_CAP_DEPTH_CLIP_DISABLE:
207   case PIPE_CAP_POINT_SPRITE:
208   case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
209   case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
210   case PIPE_CAP_VERTEX_SHADER_SATURATE:
211   case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
212   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
213   case PIPE_CAP_VERTEX_COLOR_CLAMPED:
214   case PIPE_CAP_QUERY_TIMESTAMP:
215   case PIPE_CAP_QUERY_TIME_ELAPSED:
216   case PIPE_CAP_OCCLUSION_QUERY:
217   case PIPE_CAP_BLEND_EQUATION_SEPARATE:
218   case PIPE_CAP_INDEP_BLEND_ENABLE:
219   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
220   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
221   case PIPE_CAP_PRIMITIVE_RESTART:
222   case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
223   case PIPE_CAP_TGSI_INSTANCEID:
224   case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
225   case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
226   case PIPE_CAP_CONDITIONAL_RENDER:
227   case PIPE_CAP_TEXTURE_BARRIER:
228   case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
229   case PIPE_CAP_START_INSTANCE:
230   case PIPE_CAP_USER_VERTEX_BUFFERS:
231   case PIPE_CAP_TEXTURE_MULTISAMPLE:
232   case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
233   case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
234   case PIPE_CAP_SAMPLER_VIEW_TARGET:
235   case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
236   case PIPE_CAP_CLIP_HALFZ:
237   case PIPE_CAP_POLYGON_OFFSET_CLAMP:
238   case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
239   case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
240   case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
241   case PIPE_CAP_DEPTH_BOUNDS_TEST:
242   case PIPE_CAP_TGSI_TXQS:
243   case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
244   case PIPE_CAP_CLEAR_TEXTURE:
245   case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
246   case PIPE_CAP_INVALIDATE_BUFFER:
247   case PIPE_CAP_STRING_MARKER:
248   case PIPE_CAP_CULL_DISTANCE:
249   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
250   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
251   case PIPE_CAP_TGSI_TEX_TXF_LZ:
252   case PIPE_CAP_TGSI_CLOCK:
253   case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
254   case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
255   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
256   case PIPE_CAP_TGSI_DIV:
257   case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
258   case PIPE_CAP_FLATSHADE:
259   case PIPE_CAP_ALPHA_TEST:
260   case PIPE_CAP_POINT_SIZE_FIXED:
261   case PIPE_CAP_TWO_SIDED_COLOR:
262   case PIPE_CAP_CLIP_PLANES:
263   case PIPE_CAP_PACKED_STREAM_OUTPUT:
264   case PIPE_CAP_CLEAR_SCISSORED:
265   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
266   case PIPE_CAP_COMPUTE:
267      return 1;
268   case PIPE_CAP_SEAMLESS_CUBE_MAP:
269      return 1; /* class_3d >= NVA0_3D_CLASS; */
270   /* supported on nva0+ */
271   case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
272      return class_3d >= NVA0_3D_CLASS;
273   /* supported on nva3+ */
274   case PIPE_CAP_CUBE_MAP_ARRAY:
275   case PIPE_CAP_INDEP_BLEND_FUNC:
276   case PIPE_CAP_TEXTURE_QUERY_LOD:
277   case PIPE_CAP_SAMPLE_SHADING:
278   case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
279      return class_3d >= NVA3_3D_CLASS;
280
281   /* unsupported caps */
282   case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
283   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
284   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
285   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
286   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
287   case PIPE_CAP_SHADER_STENCIL_EXPORT:
288   case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
289   case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
290   case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
291   case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
292   case PIPE_CAP_TGSI_TEXCOORD:
293   case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
294   case PIPE_CAP_TEXTURE_GATHER_SM5:
295   case PIPE_CAP_FAKE_SW_MSAA:
296   case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
297   case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
298   case PIPE_CAP_DRAW_INDIRECT:
299   case PIPE_CAP_MULTI_DRAW_INDIRECT:
300   case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
301   case PIPE_CAP_VERTEXID_NOBASE:
302   case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
303   case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
304   case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
305   case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
306   case PIPE_CAP_DRAW_PARAMETERS:
307   case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
308   case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
309   case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
310   case PIPE_CAP_GENERATE_MIPMAP:
311   case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
312   case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
313   case PIPE_CAP_QUERY_BUFFER_OBJECT:
314   case PIPE_CAP_QUERY_MEMORY_INFO:
315   case PIPE_CAP_PCI_GROUP:
316   case PIPE_CAP_PCI_BUS:
317   case PIPE_CAP_PCI_DEVICE:
318   case PIPE_CAP_PCI_FUNCTION:
319   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
320   case PIPE_CAP_TGSI_VOTE:
321   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
322   case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
323   case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
324   case PIPE_CAP_NATIVE_FENCE_FD:
325   case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
326   case PIPE_CAP_FBFETCH:
327   case PIPE_CAP_DOUBLES:
328   case PIPE_CAP_INT64:
329   case PIPE_CAP_INT64_DIVMOD:
330   case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
331   case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
332   case PIPE_CAP_TGSI_BALLOT:
333   case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
334   case PIPE_CAP_POST_DEPTH_COVERAGE:
335   case PIPE_CAP_BINDLESS_TEXTURE:
336   case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
337   case PIPE_CAP_QUERY_SO_OVERFLOW:
338   case PIPE_CAP_MEMOBJ:
339   case PIPE_CAP_LOAD_CONSTBUF:
340   case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
341   case PIPE_CAP_TILE_RASTER_ORDER:
342   case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
343   case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
344   case PIPE_CAP_CONTEXT_PRIORITY_MASK:
345   case PIPE_CAP_FENCE_SIGNAL:
346   case PIPE_CAP_CONSTBUF0_FLAGS:
347   case PIPE_CAP_PACKED_UNIFORMS:
348   case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
349   case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
350   case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
351   case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
352   case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
353   case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
354   case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
355   case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
356   case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
357   case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
358   case PIPE_CAP_SURFACE_SAMPLE_COUNT:
359   case PIPE_CAP_TGSI_ATOMFADD:
360   case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
361   case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
362   case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
363   case PIPE_CAP_NIR_COMPACT_ARRAYS:
364   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
365   case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
366   case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
367   case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
368   case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
369   case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
370   case PIPE_CAP_FBFETCH_COHERENT:
371   case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
372   case PIPE_CAP_TGSI_ATOMINC_WRAP:
373   case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
374   case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
375   case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
376   case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
377   case PIPE_CAP_FRONTEND_NOOP:
378   case PIPE_CAP_GL_SPIRV:
379   case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
380   case PIPE_CAP_TEXTURE_SHADOW_LOD:
381   case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
382   case PIPE_CAP_PSIZ_CLAMPED:
383   case PIPE_CAP_VIEWPORT_SWIZZLE:
384   case PIPE_CAP_VIEWPORT_MASK:
385   case PIPE_CAP_TEXTURE_BUFFER_SAMPLER:
386   case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
387   case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE: /* when we fix MT stuff */
388   case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
389   case PIPE_CAP_SHADER_ATOMIC_INT64:
390   case PIPE_CAP_GLSL_ZERO_INIT:
391   case PIPE_CAP_BLEND_EQUATION_ADVANCED:
392   case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
393   case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
394   case PIPE_CAP_NIR_IMAGES_AS_DEREF:
395      return 0;
396
397   case PIPE_CAP_VENDOR_ID:
398      return 0x10de;
399   case PIPE_CAP_DEVICE_ID: {
400      uint64_t device_id;
401      if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
402         NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
403         return -1;
404      }
405      return device_id;
406   }
407   case PIPE_CAP_ACCELERATED:
408      return 1;
409   case PIPE_CAP_VIDEO_MEMORY:
410      return dev->vram_size >> 20;
411   case PIPE_CAP_UMA:
412      return 0;
413
414   default:
415      if (!debug_cap_printed[param]) {
416         debug_printf("%s: unhandled cap %d\n", __func__, param);
417         debug_cap_printed[param] = true;
418      }
419      FALLTHROUGH;
420   /* caps where we want the default value */
421   case PIPE_CAP_DMABUF:
422   case PIPE_CAP_THROTTLE:
423      return u_pipe_screen_get_param_defaults(pscreen, param);
424   }
425}
426
427static int
428nv50_screen_get_shader_param(struct pipe_screen *pscreen,
429                             enum pipe_shader_type shader,
430                             enum pipe_shader_cap param)
431{
432   const struct nouveau_screen *screen = nouveau_screen(pscreen);
433
434   switch (shader) {
435   case PIPE_SHADER_VERTEX:
436   case PIPE_SHADER_GEOMETRY:
437   case PIPE_SHADER_FRAGMENT:
438   case PIPE_SHADER_COMPUTE:
439      break;
440   default:
441      return 0;
442   }
443
444   switch (param) {
445   case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
446   case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
447   case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
448   case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
449      return 16384;
450   case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
451      return 4;
452   case PIPE_SHADER_CAP_MAX_INPUTS:
453      if (shader == PIPE_SHADER_VERTEX)
454         return 32;
455      return 15;
456   case PIPE_SHADER_CAP_MAX_OUTPUTS:
457      return 16;
458   case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
459      return 65536;
460   case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
461      return NV50_MAX_PIPE_CONSTBUFS;
462   case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
463      return shader != PIPE_SHADER_FRAGMENT;
464   case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
465   case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
466   case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
467      return 1;
468   case PIPE_SHADER_CAP_MAX_TEMPS:
469      return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
470   case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
471      return 1;
472   case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
473      return 1;
474   case PIPE_SHADER_CAP_INT64_ATOMICS:
475   case PIPE_SHADER_CAP_FP16:
476   case PIPE_SHADER_CAP_FP16_DERIVATIVES:
477   case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
478   case PIPE_SHADER_CAP_INT16:
479   case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
480   case PIPE_SHADER_CAP_SUBROUTINES:
481      return 0; /* please inline, or provide function declarations */
482   case PIPE_SHADER_CAP_INTEGERS:
483      return 1;
484   case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
485      return 1;
486   case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
487      /* The chip could handle more sampler views than samplers */
488   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
489      return MIN2(16, PIPE_MAX_SAMPLERS);
490   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
491      return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
492   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
493      return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
494   case PIPE_SHADER_CAP_PREFERRED_IR:
495      return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
496   case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
497      return 32;
498   case PIPE_SHADER_CAP_SUPPORTED_IRS:
499      return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
500   case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
501   case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
502   case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
503   case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
504   case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
505   case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
506   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
507   case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
508      return 0;
509   default:
510      NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
511      return 0;
512   }
513}
514
515static float
516nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
517{
518   switch (param) {
519   case PIPE_CAPF_MAX_LINE_WIDTH:
520   case PIPE_CAPF_MAX_LINE_WIDTH_AA:
521      return 10.0f;
522   case PIPE_CAPF_MAX_POINT_WIDTH:
523   case PIPE_CAPF_MAX_POINT_WIDTH_AA:
524      return 64.0f;
525   case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
526      return 16.0f;
527   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
528      return 15.0f;
529   case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
530   case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
531   case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
532      return 0.0f;
533   }
534
535   NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
536   return 0.0f;
537}
538
539static int
540nv50_screen_get_compute_param(struct pipe_screen *pscreen,
541                              enum pipe_shader_ir ir_type,
542                              enum pipe_compute_cap param, void *data)
543{
544   struct nv50_screen *screen = nv50_screen(pscreen);
545
546#define RET(x) do {                  \
547   if (data)                         \
548      memcpy(data, x, sizeof(x));    \
549   return sizeof(x);                 \
550} while (0)
551
552   switch (param) {
553   case PIPE_COMPUTE_CAP_GRID_DIMENSION:
554      RET((uint64_t []) { 3 });
555   case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
556      RET(((uint64_t []) { 65535, 65535, 65535 }));
557   case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
558      RET(((uint64_t []) { 512, 512, 64 }));
559   case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
560      RET((uint64_t []) { 512 });
561   case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
562      RET((uint64_t []) { 1ULL << 32 });
563   case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
564      RET((uint64_t []) { 16 << 10 });
565   case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
566      RET((uint64_t []) { 16 << 10 });
567   case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
568      RET((uint64_t []) { 4096 });
569   case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
570      RET((uint32_t []) { 32 });
571   case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
572      RET((uint64_t []) { 1ULL << 40 });
573   case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
574      RET((uint32_t []) { 0 });
575   case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
576      RET((uint32_t []) { screen->mp_count });
577   case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
578      RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
579   case PIPE_COMPUTE_CAP_ADDRESS_BITS:
580      RET((uint32_t []) { 32 });
581   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
582      RET((uint64_t []) { 0 });
583   default:
584      return 0;
585   }
586
587#undef RET
588}
589
590static void
591nv50_screen_destroy(struct pipe_screen *pscreen)
592{
593   struct nv50_screen *screen = nv50_screen(pscreen);
594
595   if (!nouveau_drm_screen_unref(&screen->base))
596      return;
597
598   nouveau_fence_cleanup(&screen->base);
599
600   if (screen->base.pushbuf)
601      screen->base.pushbuf->user_priv = NULL;
602
603   if (screen->blitter)
604      nv50_blitter_destroy(screen);
605   if (screen->pm.prog) {
606      screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
607      nv50_program_destroy(NULL, screen->pm.prog);
608      FREE(screen->pm.prog);
609   }
610
611   nouveau_bo_ref(NULL, &screen->code);
612   nouveau_bo_ref(NULL, &screen->tls_bo);
613   nouveau_bo_ref(NULL, &screen->stack_bo);
614   nouveau_bo_ref(NULL, &screen->txc);
615   nouveau_bo_ref(NULL, &screen->uniforms);
616   nouveau_bo_ref(NULL, &screen->fence.bo);
617
618   nouveau_heap_destroy(&screen->vp_code_heap);
619   nouveau_heap_destroy(&screen->gp_code_heap);
620   nouveau_heap_destroy(&screen->fp_code_heap);
621
622   FREE(screen->tic.entries);
623
624   nouveau_object_del(&screen->tesla);
625   nouveau_object_del(&screen->eng2d);
626   nouveau_object_del(&screen->m2mf);
627   nouveau_object_del(&screen->compute);
628   nouveau_object_del(&screen->sync);
629
630   nouveau_screen_fini(&screen->base);
631
632   FREE(screen);
633}
634
635static void
636nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
637{
638   struct nv50_screen *screen = nv50_screen(pscreen);
639   struct nouveau_pushbuf *push = screen->base.pushbuf;
640
641   /* we need to do it after possible flush in MARK_RING */
642   *sequence = ++screen->base.fence.sequence;
643
644   assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
645   PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
646   PUSH_DATAh(push, screen->fence.bo->offset);
647   PUSH_DATA (push, screen->fence.bo->offset);
648   PUSH_DATA (push, *sequence);
649   PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
650                    NV50_3D_QUERY_GET_UNK4 |
651                    NV50_3D_QUERY_GET_UNIT_CROP |
652                    NV50_3D_QUERY_GET_TYPE_QUERY |
653                    NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
654                    NV50_3D_QUERY_GET_SHORT);
655}
656
657static u32
658nv50_screen_fence_update(struct pipe_screen *pscreen)
659{
660   return nv50_screen(pscreen)->fence.map[0];
661}
662
663static void
664nv50_screen_init_hwctx(struct nv50_screen *screen)
665{
666   struct nouveau_pushbuf *push = screen->base.pushbuf;
667   struct nv04_fifo *fifo;
668   unsigned i;
669
670   fifo = (struct nv04_fifo *)screen->base.channel->data;
671
672   BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
673   PUSH_DATA (push, screen->m2mf->handle);
674   BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
675   PUSH_DATA (push, screen->sync->handle);
676   PUSH_DATA (push, fifo->vram);
677   PUSH_DATA (push, fifo->vram);
678
679   BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
680   PUSH_DATA (push, screen->eng2d->handle);
681   BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
682   PUSH_DATA (push, screen->sync->handle);
683   PUSH_DATA (push, fifo->vram);
684   PUSH_DATA (push, fifo->vram);
685   PUSH_DATA (push, fifo->vram);
686   BEGIN_NV04(push, NV50_2D(OPERATION), 1);
687   PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
688   BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
689   PUSH_DATA (push, 0);
690   BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
691   PUSH_DATA (push, 0);
692   BEGIN_NV04(push, NV50_2D(SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP), 1);
693   PUSH_DATA (push, 1);
694   BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
695   PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
696
697   BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
698   PUSH_DATA (push, screen->tesla->handle);
699
700   BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
701   PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
702
703   BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
704   PUSH_DATA (push, screen->sync->handle);
705   BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
706   for (i = 0; i < 11; ++i)
707      PUSH_DATA(push, fifo->vram);
708   BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
709   for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
710      PUSH_DATA(push, fifo->vram);
711
712   BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
713   PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
714   BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
715   PUSH_DATA (push, 0xf);
716
717   if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
718      BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
719      PUSH_DATA (push, 0x18);
720   }
721
722   BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
723   PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
724
725   BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
726   for (i = 0; i < 8; ++i)
727      PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
728
729   BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
730   PUSH_DATA (push, 1);
731
732   BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
733   PUSH_DATA (push, 0);
734   BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
735   PUSH_DATA (push, 0);
736   BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
737   PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
738   BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
739   PUSH_DATA (push, 0);
740   BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
741   PUSH_DATA (push, 1);
742   BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
743   PUSH_DATA (push, 1);
744
745   if (screen->tesla->oclass >= NVA0_3D_CLASS) {
746      BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
747      PUSH_DATA (push, 0);
748   }
749
750   BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
751   PUSH_DATA (push, 0);
752   BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
753   PUSH_DATA (push, 0);
754   PUSH_DATA (push, 0);
755   BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
756   PUSH_DATA (push, 0x3f);
757
758   BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
759   PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
760   PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
761
762   BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
763   PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
764   PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
765
766   BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
767   PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
768   PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
769
770   BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
771   PUSH_DATAh(push, screen->tls_bo->offset);
772   PUSH_DATA (push, screen->tls_bo->offset);
773   PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
774
775   BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
776   PUSH_DATAh(push, screen->stack_bo->offset);
777   PUSH_DATA (push, screen->stack_bo->offset);
778   PUSH_DATA (push, 4);
779
780   BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
781   PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
782   PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
783   PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
784
785   BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
786   PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
787   PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
788   PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
789
790   BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
791   PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
792   PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
793   PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
794
795   BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
796   PUSH_DATAh(push, screen->uniforms->offset + (4 << 16));
797   PUSH_DATA (push, screen->uniforms->offset + (4 << 16));
798   PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
799
800   BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
801   PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
802   PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
803   PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
804
805   /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
806   BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
807   PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
808   BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
809   PUSH_DATAf(push, 0.0f);
810   PUSH_DATAf(push, 0.0f);
811   PUSH_DATAf(push, 0.0f);
812   PUSH_DATAf(push, 0.0f);
813   BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
814   PUSH_DATAh(push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
815   PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
816
817   /* set the membar offset */
818   BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
819   PUSH_DATA (push, (NV50_CB_AUX_MEMBAR_OFFSET << (8 - 2)) | NV50_CB_AUX);
820   BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 1);
821   PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_MEMBAR_OFFSET);
822
823   nv50_upload_ms_info(push);
824
825   /* max TIC (bits 4:8) & TSC bindings, per program type */
826   for (i = 0; i < NV50_MAX_3D_SHADER_STAGES; ++i) {
827      BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
828      PUSH_DATA (push, 0x54);
829   }
830
831   BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
832   PUSH_DATAh(push, screen->txc->offset);
833   PUSH_DATA (push, screen->txc->offset);
834   PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
835
836   BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
837   PUSH_DATAh(push, screen->txc->offset + 65536);
838   PUSH_DATA (push, screen->txc->offset + 65536);
839   PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
840
841   BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
842   PUSH_DATA (push, 0);
843
844   BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
845   PUSH_DATA (push, 0);
846   BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
847   PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
848   BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
849   for (i = 0; i < 8 * 2; ++i)
850      PUSH_DATA(push, 0);
851   BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
852   PUSH_DATA (push, 0);
853
854   BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
855   PUSH_DATA (push, 1);
856   for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
857      BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
858      PUSH_DATAf(push, 0.0f);
859      PUSH_DATAf(push, 1.0f);
860      BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
861      PUSH_DATA (push, 8192 << 16);
862      PUSH_DATA (push, 8192 << 16);
863   }
864
865   BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
866#ifdef NV50_SCISSORS_CLIPPING
867   PUSH_DATA (push, 0x0000);
868#else
869   PUSH_DATA (push, 0x1080);
870#endif
871
872   BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
873   PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
874
875   /* We use scissors instead of exact view volume clipping,
876    * so they're always enabled.
877    */
878   for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
879      BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
880      PUSH_DATA (push, 1);
881      PUSH_DATA (push, 8192 << 16);
882      PUSH_DATA (push, 8192 << 16);
883   }
884
885   BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
886   PUSH_DATA (push, 1);
887   BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
888   PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
889   BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
890   PUSH_DATA (push, 0x11111111);
891   BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
892   PUSH_DATA (push, 1);
893
894   BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
895   PUSH_DATA (push, 0);
896   if (screen->base.class_3d >= NV84_3D_CLASS) {
897      BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
898      PUSH_DATA (push, 0);
899   }
900
901   BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
902   PUSH_DATA (push, 1);
903   BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
904   PUSH_DATA (push, 1);
905
906   PUSH_KICK (push);
907}
908
909static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
910      uint64_t *tls_size)
911{
912   struct nouveau_device *dev = screen->base.device;
913   int ret;
914
915   screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
916         ONE_TEMP_SIZE;
917   if (nouveau_mesa_debug)
918      debug_printf("allocating space for %u temps\n",
919            util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
920   *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
921         screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
922
923   ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
924                        *tls_size, NULL, &screen->tls_bo);
925   if (ret) {
926      NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
927      return ret;
928   }
929
930   return 0;
931}
932
933int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
934{
935   struct nouveau_pushbuf *push = screen->base.pushbuf;
936   int ret;
937   uint64_t tls_size;
938
939   if (tls_space < screen->cur_tls_space)
940      return 0;
941   if (tls_space > screen->max_tls_space) {
942      /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
943       * LOCAL_WARPS_NO_CLAMP) */
944      NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
945            (unsigned)(tls_space / ONE_TEMP_SIZE),
946            (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
947      return -ENOMEM;
948   }
949
950   nouveau_bo_ref(NULL, &screen->tls_bo);
951   ret = nv50_tls_alloc(screen, tls_space, &tls_size);
952   if (ret)
953      return ret;
954
955   BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
956   PUSH_DATAh(push, screen->tls_bo->offset);
957   PUSH_DATA (push, screen->tls_bo->offset);
958   PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
959
960   return 1;
961}
962
963static const nir_shader_compiler_options nir_options = {
964   .fuse_ffma16 = false, /* nir doesn't track mad vs fma */
965   .fuse_ffma32 = false, /* nir doesn't track mad vs fma */
966   .fuse_ffma64 = false, /* nir doesn't track mad vs fma */
967   .lower_flrp32 = true,
968   .lower_flrp64 = true,
969   .lower_fpow = false,
970   .lower_uadd_carry = true,
971   .lower_usub_borrow = true,
972   .lower_ffract = true,
973   .lower_pack_half_2x16 = true,
974   .lower_pack_unorm_2x16 = true,
975   .lower_pack_snorm_2x16 = true,
976   .lower_pack_unorm_4x8 = true,
977   .lower_pack_snorm_4x8 = true,
978   .lower_unpack_half_2x16 = true,
979   .lower_unpack_unorm_2x16 = true,
980   .lower_unpack_snorm_2x16 = true,
981   .lower_unpack_unorm_4x8 = true,
982   .lower_unpack_snorm_4x8 = true,
983   .lower_extract_byte = true,
984   .lower_extract_word = true,
985   .lower_insert_byte = true,
986   .lower_insert_word = true,
987   .lower_all_io_to_temps = false,
988   .lower_cs_local_index_from_id = true,
989   .lower_rotate = true,
990   .lower_to_scalar = true,
991   .use_interpolated_input_intrinsics = true,
992   .max_unroll_iterations = 32,
993};
994
995static const void *
996nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
997                                 enum pipe_shader_ir ir,
998                                 enum pipe_shader_type shader)
999{
1000   if (ir == PIPE_SHADER_IR_NIR)
1001      return &nir_options;
1002   return NULL;
1003}
1004
1005struct nouveau_screen *
1006nv50_screen_create(struct nouveau_device *dev)
1007{
1008   struct nv50_screen *screen;
1009   struct pipe_screen *pscreen;
1010   struct nouveau_object *chan;
1011   uint64_t value;
1012   uint32_t tesla_class;
1013   unsigned stack_size;
1014   int ret;
1015
1016   screen = CALLOC_STRUCT(nv50_screen);
1017   if (!screen)
1018      return NULL;
1019   pscreen = &screen->base.base;
1020   pscreen->destroy = nv50_screen_destroy;
1021
1022   ret = nouveau_screen_init(&screen->base, dev);
1023   if (ret) {
1024      NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
1025      goto fail;
1026   }
1027
1028   /* TODO: Prevent FIFO prefetch before transfer of index buffers and
1029    *  admit them to VRAM.
1030    */
1031   screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
1032      PIPE_BIND_VERTEX_BUFFER;
1033   screen->base.sysmem_bindings |=
1034      PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
1035
1036   screen->base.pushbuf->user_priv = screen;
1037   screen->base.pushbuf->rsvd_kick = 5;
1038
1039   chan = screen->base.channel;
1040
1041   pscreen->context_create = nv50_create;
1042   pscreen->is_format_supported = nv50_screen_is_format_supported;
1043   pscreen->get_param = nv50_screen_get_param;
1044   pscreen->get_shader_param = nv50_screen_get_shader_param;
1045   pscreen->get_paramf = nv50_screen_get_paramf;
1046   pscreen->get_compute_param = nv50_screen_get_compute_param;
1047   pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
1048   pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
1049
1050   /* nir stuff */
1051   pscreen->get_compiler_options = nv50_screen_get_compiler_options;
1052
1053   nv50_screen_init_resource_functions(pscreen);
1054
1055   if (screen->base.device->chipset < 0x84 ||
1056       debug_get_bool_option("NOUVEAU_PMPEG", false)) {
1057      /* PMPEG */
1058      nouveau_screen_init_vdec(&screen->base);
1059   } else if (screen->base.device->chipset < 0x98 ||
1060              screen->base.device->chipset == 0xa0) {
1061      /* VP2 */
1062      screen->base.base.get_video_param = nv84_screen_get_video_param;
1063      screen->base.base.is_video_format_supported = nv84_screen_video_supported;
1064   } else {
1065      /* VP3/4 */
1066      screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
1067      screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
1068   }
1069
1070   ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
1071                        NULL, &screen->fence.bo);
1072   if (ret) {
1073      NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
1074      goto fail;
1075   }
1076
1077   nouveau_bo_map(screen->fence.bo, 0, NULL);
1078   screen->fence.map = screen->fence.bo->map;
1079   screen->base.fence.emit = nv50_screen_fence_emit;
1080   screen->base.fence.update = nv50_screen_fence_update;
1081
1082   ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
1083                            &(struct nv04_notify){ .length = 32 },
1084                            sizeof(struct nv04_notify), &screen->sync);
1085   if (ret) {
1086      NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
1087      goto fail;
1088   }
1089
1090   ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
1091                            NULL, 0, &screen->m2mf);
1092   if (ret) {
1093      NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
1094      goto fail;
1095   }
1096
1097   ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
1098                            NULL, 0, &screen->eng2d);
1099   if (ret) {
1100      NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
1101      goto fail;
1102   }
1103
1104   switch (dev->chipset & 0xf0) {
1105   case 0x50:
1106      tesla_class = NV50_3D_CLASS;
1107      break;
1108   case 0x80:
1109   case 0x90:
1110      tesla_class = NV84_3D_CLASS;
1111      break;
1112   case 0xa0:
1113      switch (dev->chipset) {
1114      case 0xa0:
1115      case 0xaa:
1116      case 0xac:
1117         tesla_class = NVA0_3D_CLASS;
1118         break;
1119      case 0xaf:
1120         tesla_class = NVAF_3D_CLASS;
1121         break;
1122      default:
1123         tesla_class = NVA3_3D_CLASS;
1124         break;
1125      }
1126      break;
1127   default:
1128      NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
1129      goto fail;
1130   }
1131   screen->base.class_3d = tesla_class;
1132
1133   ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
1134                            NULL, 0, &screen->tesla);
1135   if (ret) {
1136      NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
1137      goto fail;
1138   }
1139
1140   /* This over-allocates by a page. The GP, which would execute at the end of
1141    * the last page, would trigger faults. The going theory is that it
1142    * prefetches up to a certain amount.
1143    */
1144   ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
1145                        (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
1146                        NULL, &screen->code);
1147   if (ret) {
1148      NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1149      goto fail;
1150   }
1151
1152   nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1153   nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1154   nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1155
1156   nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1157
1158   screen->TPs = util_bitcount(value & 0xffff);
1159   screen->MPsInTP = util_bitcount(value & 0x0f000000);
1160
1161   screen->mp_count = screen->TPs * screen->MPsInTP;
1162
1163   stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1164         STACK_WARPS_ALLOC * 64 * 8;
1165
1166   ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1167                        &screen->stack_bo);
1168   if (ret) {
1169      NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1170      goto fail;
1171   }
1172
1173   uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1174         screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
1175         ONE_TEMP_SIZE;
1176   screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1177   screen->max_tls_space /= 2; /* half of vram */
1178
1179   /* hw can address max 64 KiB */
1180   screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1181
1182   uint64_t tls_size;
1183   unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1184   ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1185   if (ret)
1186      goto fail;
1187
1188   if (nouveau_mesa_debug)
1189      debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1190            screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1191
1192   ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 5 << 16, NULL,
1193                        &screen->uniforms);
1194   if (ret) {
1195      NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1196      goto fail;
1197   }
1198
1199   ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1200                        &screen->txc);
1201   if (ret) {
1202      NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1203      goto fail;
1204   }
1205
1206   screen->tic.entries = CALLOC(4096, sizeof(void *));
1207   screen->tsc.entries = screen->tic.entries + 2048;
1208
1209   if (!nv50_blitter_create(screen))
1210      goto fail;
1211
1212   nv50_screen_init_hwctx(screen);
1213
1214   ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1215   if (ret) {
1216      NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1217      goto fail;
1218   }
1219
1220   nouveau_fence_new(&screen->base, &screen->base.fence.current);
1221
1222   return &screen->base;
1223
1224fail:
1225   screen->base.base.context_create = NULL;
1226   return &screen->base;
1227}
1228
1229int
1230nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1231{
1232   int i = screen->tic.next;
1233
1234   while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1235      i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1236
1237   screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1238
1239   if (screen->tic.entries[i])
1240      nv50_tic_entry(screen->tic.entries[i])->id = -1;
1241
1242   screen->tic.entries[i] = entry;
1243   return i;
1244}
1245
1246int
1247nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1248{
1249   int i = screen->tsc.next;
1250
1251   while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1252      i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1253
1254   screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1255
1256   if (screen->tsc.entries[i])
1257      nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1258
1259   screen->tsc.entries[i] = entry;
1260   return i;
1261}
1262