1/**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifndef RADEON_UVD_H
29#define RADEON_UVD_H
30
31#include "radeon/radeon_winsys.h"
32#include "vl/vl_video_buffer.h"
33
34/* UVD uses PM4 packet type 0 and 2 */
35#define RUVD_PKT_TYPE_S(x)        (((unsigned)(x)&0x3) << 30)
36#define RUVD_PKT_TYPE_G(x)        (((x) >> 30) & 0x3)
37#define RUVD_PKT_TYPE_C           0x3FFFFFFF
38#define RUVD_PKT_COUNT_S(x)       (((unsigned)(x)&0x3FFF) << 16)
39#define RUVD_PKT_COUNT_G(x)       (((x) >> 16) & 0x3FFF)
40#define RUVD_PKT_COUNT_C          0xC000FFFF
41#define RUVD_PKT0_BASE_INDEX_S(x) (((unsigned)(x)&0xFFFF) << 0)
42#define RUVD_PKT0_BASE_INDEX_G(x) (((x) >> 0) & 0xFFFF)
43#define RUVD_PKT0_BASE_INDEX_C    0xFFFF0000
44#define RUVD_PKT0(index, count)                                                                    \
45   (RUVD_PKT_TYPE_S(0) | RUVD_PKT0_BASE_INDEX_S(index) | RUVD_PKT_COUNT_S(count))
46#define RUVD_PKT2() (RUVD_PKT_TYPE_S(2))
47
48/* registers involved with UVD */
49#define RUVD_GPCOM_VCPU_CMD   0xEF0C
50#define RUVD_GPCOM_VCPU_DATA0 0xEF10
51#define RUVD_GPCOM_VCPU_DATA1 0xEF14
52#define RUVD_ENGINE_CNTL      0xEF18
53
54#define RUVD_GPCOM_VCPU_CMD_SOC15   0x2070c
55#define RUVD_GPCOM_VCPU_DATA0_SOC15 0x20710
56#define RUVD_GPCOM_VCPU_DATA1_SOC15 0x20714
57#define RUVD_ENGINE_CNTL_SOC15      0x20718
58
59/* UVD commands to VCPU */
60#define RUVD_CMD_MSG_BUFFER             0x00000000
61#define RUVD_CMD_DPB_BUFFER             0x00000001
62#define RUVD_CMD_DECODING_TARGET_BUFFER 0x00000002
63#define RUVD_CMD_FEEDBACK_BUFFER        0x00000003
64#define RUVD_CMD_SESSION_CONTEXT_BUFFER 0x00000005
65#define RUVD_CMD_BITSTREAM_BUFFER       0x00000100
66#define RUVD_CMD_ITSCALING_TABLE_BUFFER 0x00000204
67#define RUVD_CMD_CONTEXT_BUFFER         0x00000206
68
69/* UVD message types */
70#define RUVD_MSG_CREATE  0
71#define RUVD_MSG_DECODE  1
72#define RUVD_MSG_DESTROY 2
73
74/* UVD stream types */
75#define RUVD_CODEC_H264      0x00000000
76#define RUVD_CODEC_VC1       0x00000001
77#define RUVD_CODEC_MPEG2     0x00000003
78#define RUVD_CODEC_MPEG4     0x00000004
79#define RUVD_CODEC_H264_PERF 0x00000007
80#define RUVD_CODEC_MJPEG     0x00000008
81#define RUVD_CODEC_H265      0x00000010
82
83/* UVD decode target buffer tiling mode */
84#define RUVD_TILE_LINEAR 0x00000000
85#define RUVD_TILE_8X4    0x00000001
86#define RUVD_TILE_8X8    0x00000002
87#define RUVD_TILE_32AS8  0x00000003
88
89/* UVD decode target buffer array mode */
90#define RUVD_ARRAY_MODE_LINEAR                   0x00000000
91#define RUVD_ARRAY_MODE_MACRO_LINEAR_MICRO_TILED 0x00000001
92#define RUVD_ARRAY_MODE_1D_THIN                  0x00000002
93#define RUVD_ARRAY_MODE_2D_THIN                  0x00000004
94#define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004
95#define RUVD_ARRAY_MODE_MACRO_TILED_MICRO_TILED  0x00000005
96
97/* UVD tile config */
98#define RUVD_BANK_WIDTH(x)              ((x) << 0)
99#define RUVD_BANK_HEIGHT(x)             ((x) << 3)
100#define RUVD_MACRO_TILE_ASPECT_RATIO(x) ((x) << 6)
101#define RUVD_NUM_BANKS(x)               ((x) << 9)
102
103/* H.264 profile definitions */
104#define RUVD_H264_PROFILE_BASELINE    0x00000000
105#define RUVD_H264_PROFILE_MAIN        0x00000001
106#define RUVD_H264_PROFILE_HIGH        0x00000002
107#define RUVD_H264_PROFILE_STEREO_HIGH 0x00000003
108#define RUVD_H264_PROFILE_MVC         0x00000004
109
110/* VC-1 profile definitions */
111#define RUVD_VC1_PROFILE_SIMPLE   0x00000000
112#define RUVD_VC1_PROFILE_MAIN     0x00000001
113#define RUVD_VC1_PROFILE_ADVANCED 0x00000002
114
115enum ruvd_surface_type
116{
117   RUVD_SURFACE_TYPE_LEGACY = 0,
118   RUVD_SURFACE_TYPE_GFX9
119};
120
121struct ruvd_mvc_element {
122   uint16_t viewOrderIndex;
123   uint16_t viewId;
124   uint16_t numOfAnchorRefsInL0;
125   uint16_t viewIdOfAnchorRefsInL0[15];
126   uint16_t numOfAnchorRefsInL1;
127   uint16_t viewIdOfAnchorRefsInL1[15];
128   uint16_t numOfNonAnchorRefsInL0;
129   uint16_t viewIdOfNonAnchorRefsInL0[15];
130   uint16_t numOfNonAnchorRefsInL1;
131   uint16_t viewIdOfNonAnchorRefsInL1[15];
132};
133
134struct ruvd_h264 {
135   uint32_t profile;
136   uint32_t level;
137
138   uint32_t sps_info_flags;
139   uint32_t pps_info_flags;
140   uint8_t chroma_format;
141   uint8_t bit_depth_luma_minus8;
142   uint8_t bit_depth_chroma_minus8;
143   uint8_t log2_max_frame_num_minus4;
144
145   uint8_t pic_order_cnt_type;
146   uint8_t log2_max_pic_order_cnt_lsb_minus4;
147   uint8_t num_ref_frames;
148   uint8_t reserved_8bit;
149
150   int8_t pic_init_qp_minus26;
151   int8_t pic_init_qs_minus26;
152   int8_t chroma_qp_index_offset;
153   int8_t second_chroma_qp_index_offset;
154
155   uint8_t num_slice_groups_minus1;
156   uint8_t slice_group_map_type;
157   uint8_t num_ref_idx_l0_active_minus1;
158   uint8_t num_ref_idx_l1_active_minus1;
159
160   uint16_t slice_group_change_rate_minus1;
161   uint16_t reserved_16bit_1;
162
163   uint8_t scaling_list_4x4[6][16];
164   uint8_t scaling_list_8x8[2][64];
165
166   uint32_t frame_num;
167   uint32_t frame_num_list[16];
168   int32_t curr_field_order_cnt_list[2];
169   int32_t field_order_cnt_list[16][2];
170
171   uint32_t decoded_pic_idx;
172
173   uint32_t curr_pic_ref_frame_num;
174
175   uint8_t ref_frame_list[16];
176
177   uint32_t reserved[122];
178
179   struct {
180      uint32_t numViews;
181      uint32_t viewId0;
182      struct ruvd_mvc_element mvcElements[1];
183   } mvc;
184};
185
186struct ruvd_h265 {
187   uint32_t sps_info_flags;
188   uint32_t pps_info_flags;
189
190   uint8_t chroma_format;
191   uint8_t bit_depth_luma_minus8;
192   uint8_t bit_depth_chroma_minus8;
193   uint8_t log2_max_pic_order_cnt_lsb_minus4;
194
195   uint8_t sps_max_dec_pic_buffering_minus1;
196   uint8_t log2_min_luma_coding_block_size_minus3;
197   uint8_t log2_diff_max_min_luma_coding_block_size;
198   uint8_t log2_min_transform_block_size_minus2;
199
200   uint8_t log2_diff_max_min_transform_block_size;
201   uint8_t max_transform_hierarchy_depth_inter;
202   uint8_t max_transform_hierarchy_depth_intra;
203   uint8_t pcm_sample_bit_depth_luma_minus1;
204
205   uint8_t pcm_sample_bit_depth_chroma_minus1;
206   uint8_t log2_min_pcm_luma_coding_block_size_minus3;
207   uint8_t log2_diff_max_min_pcm_luma_coding_block_size;
208   uint8_t num_extra_slice_header_bits;
209
210   uint8_t num_short_term_ref_pic_sets;
211   uint8_t num_long_term_ref_pic_sps;
212   uint8_t num_ref_idx_l0_default_active_minus1;
213   uint8_t num_ref_idx_l1_default_active_minus1;
214
215   int8_t pps_cb_qp_offset;
216   int8_t pps_cr_qp_offset;
217   int8_t pps_beta_offset_div2;
218   int8_t pps_tc_offset_div2;
219
220   uint8_t diff_cu_qp_delta_depth;
221   uint8_t num_tile_columns_minus1;
222   uint8_t num_tile_rows_minus1;
223   uint8_t log2_parallel_merge_level_minus2;
224
225   uint16_t column_width_minus1[19];
226   uint16_t row_height_minus1[21];
227
228   int8_t init_qp_minus26;
229   uint8_t num_delta_pocs_ref_rps_idx;
230   uint8_t curr_idx;
231   uint8_t reserved1;
232   int32_t curr_poc;
233   uint8_t ref_pic_list[16];
234   int32_t poc_list[16];
235   uint8_t ref_pic_set_st_curr_before[8];
236   uint8_t ref_pic_set_st_curr_after[8];
237   uint8_t ref_pic_set_lt_curr[8];
238
239   uint8_t ucScalingListDCCoefSizeID2[6];
240   uint8_t ucScalingListDCCoefSizeID3[2];
241
242   uint8_t highestTid;
243   uint8_t isNonRef;
244
245   uint8_t p010_mode;
246   uint8_t msb_mode;
247   uint8_t luma_10to8;
248   uint8_t chroma_10to8;
249   uint8_t sclr_luma10to8;
250   uint8_t sclr_chroma10to8;
251
252   uint8_t direct_reflist[2][15];
253};
254
255struct ruvd_vc1 {
256   uint32_t profile;
257   uint32_t level;
258   uint32_t sps_info_flags;
259   uint32_t pps_info_flags;
260   uint32_t pic_structure;
261   uint32_t chroma_format;
262};
263
264struct ruvd_mpeg2 {
265   uint32_t decoded_pic_idx;
266   uint32_t ref_pic_idx[2];
267
268   uint8_t load_intra_quantiser_matrix;
269   uint8_t load_nonintra_quantiser_matrix;
270   uint8_t reserved_quantiser_alignement[2];
271   uint8_t intra_quantiser_matrix[64];
272   uint8_t nonintra_quantiser_matrix[64];
273
274   uint8_t profile_and_level_indication;
275   uint8_t chroma_format;
276
277   uint8_t picture_coding_type;
278
279   uint8_t reserved_1;
280
281   uint8_t f_code[2][2];
282   uint8_t intra_dc_precision;
283   uint8_t pic_structure;
284   uint8_t top_field_first;
285   uint8_t frame_pred_frame_dct;
286   uint8_t concealment_motion_vectors;
287   uint8_t q_scale_type;
288   uint8_t intra_vlc_format;
289   uint8_t alternate_scan;
290};
291
292struct ruvd_mpeg4 {
293   uint32_t decoded_pic_idx;
294   uint32_t ref_pic_idx[2];
295
296   uint32_t variant_type;
297   uint8_t profile_and_level_indication;
298
299   uint8_t video_object_layer_verid;
300   uint8_t video_object_layer_shape;
301
302   uint8_t reserved_1;
303
304   uint16_t video_object_layer_width;
305   uint16_t video_object_layer_height;
306
307   uint16_t vop_time_increment_resolution;
308
309   uint16_t reserved_2;
310
311   uint32_t flags;
312
313   uint8_t quant_type;
314
315   uint8_t reserved_3[3];
316
317   uint8_t intra_quant_mat[64];
318   uint8_t nonintra_quant_mat[64];
319
320   struct {
321      uint8_t sprite_enable;
322
323      uint8_t reserved_4[3];
324
325      uint16_t sprite_width;
326      uint16_t sprite_height;
327      int16_t sprite_left_coordinate;
328      int16_t sprite_top_coordinate;
329
330      uint8_t no_of_sprite_warping_points;
331      uint8_t sprite_warping_accuracy;
332      uint8_t sprite_brightness_change;
333      uint8_t low_latency_sprite_enable;
334   } sprite_config;
335
336   struct {
337      uint32_t flags;
338      uint8_t vol_mode;
339      uint8_t reserved_5[3];
340   } divx_311_config;
341};
342
343/* message between driver and hardware */
344struct ruvd_msg {
345
346   uint32_t size;
347   uint32_t msg_type;
348   uint32_t stream_handle;
349   uint32_t status_report_feedback_number;
350
351   union {
352      struct {
353         uint32_t stream_type;
354         uint32_t session_flags;
355         uint32_t asic_id;
356         uint32_t width_in_samples;
357         uint32_t height_in_samples;
358         uint32_t dpb_buffer;
359         uint32_t dpb_size;
360         uint32_t dpb_model;
361         uint32_t version_info;
362      } create;
363
364      struct {
365         uint32_t stream_type;
366         uint32_t decode_flags;
367         uint32_t width_in_samples;
368         uint32_t height_in_samples;
369
370         uint32_t dpb_buffer;
371         uint32_t dpb_size;
372         uint32_t dpb_model;
373         uint32_t dpb_reserved;
374
375         uint32_t db_offset_alignment;
376         uint32_t db_pitch;
377         uint32_t db_tiling_mode;
378         uint32_t db_array_mode;
379         uint32_t db_field_mode;
380         uint32_t db_surf_tile_config;
381         uint32_t db_aligned_height;
382         uint32_t db_reserved;
383
384         uint32_t use_addr_macro;
385
386         uint32_t bsd_buffer;
387         uint32_t bsd_size;
388
389         uint32_t pic_param_buffer;
390         uint32_t pic_param_size;
391         uint32_t mb_cntl_buffer;
392         uint32_t mb_cntl_size;
393
394         uint32_t dt_buffer;
395         uint32_t dt_pitch;
396         uint32_t dt_tiling_mode;
397         uint32_t dt_array_mode;
398         uint32_t dt_field_mode;
399         uint32_t dt_luma_top_offset;
400         uint32_t dt_luma_bottom_offset;
401         uint32_t dt_chroma_top_offset;
402         uint32_t dt_chroma_bottom_offset;
403         uint32_t dt_surf_tile_config;
404         uint32_t dt_uv_surf_tile_config;
405         // re-use dt_wa_chroma_top_offset as dt_ext_info for UV pitch in stoney
406         uint32_t dt_wa_chroma_top_offset;
407         uint32_t dt_wa_chroma_bottom_offset;
408
409         uint32_t reserved[16];
410
411         union {
412            struct ruvd_h264 h264;
413            struct ruvd_h265 h265;
414            struct ruvd_vc1 vc1;
415            struct ruvd_mpeg2 mpeg2;
416            struct ruvd_mpeg4 mpeg4;
417
418            uint32_t info[768];
419         } codec;
420
421         uint8_t extension_support;
422         uint8_t reserved_8bit_1;
423         uint8_t reserved_8bit_2;
424         uint8_t reserved_8bit_3;
425         uint32_t extension_reserved[64];
426      } decode;
427   } body;
428};
429
430/* driver dependent callback */
431typedef struct pb_buffer *(*ruvd_set_dtb)(struct ruvd_msg *msg, struct vl_video_buffer *vb);
432
433/* create an UVD decode */
434struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,
435                                                      const struct pipe_video_codec *templat,
436                                                      ruvd_set_dtb set_dtb);
437
438/* fill decoding target field from the luma and chroma surfaces */
439void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
440                            struct radeon_surf *chroma, enum ruvd_surface_type type);
441#endif
442