1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25/* The compiler middle-end architecture: Explaining (non-)monolithic shaders 26 * ------------------------------------------------------------------------- 27 * 28 * Typically, there is one-to-one correspondence between API and HW shaders, 29 * that is, for every API shader, there is exactly one shader binary in 30 * the driver. 31 * 32 * The problem with that is that we also have to emulate some API states 33 * (e.g. alpha-test, and many others) in shaders too. The two obvious ways 34 * to deal with it are: 35 * - each shader has multiple variants for each combination of emulated states, 36 * and the variants are compiled on demand, possibly relying on a shader 37 * cache for good performance 38 * - patch shaders at the binary level 39 * 40 * This driver uses something completely different. The emulated states are 41 * usually implemented at the beginning or end of shaders. Therefore, we can 42 * split the shader into 3 parts: 43 * - prolog part (shader code dependent on states) 44 * - main part (the API shader) 45 * - epilog part (shader code dependent on states) 46 * 47 * Each part is compiled as a separate shader and the final binaries are 48 * concatenated. This type of shader is called non-monolithic, because it 49 * consists of multiple independent binaries. Creating a new shader variant 50 * is therefore only a concatenation of shader parts (binaries) and doesn't 51 * involve any compilation. The main shader parts are the only parts that are 52 * compiled when applications create shader objects. The prolog and epilog 53 * parts are compiled on the first use and saved, so that their binaries can 54 * be reused by many other shaders. 55 * 56 * One of the roles of the prolog part is to compute vertex buffer addresses 57 * for vertex shaders. A few of the roles of the epilog part are color buffer 58 * format conversions in pixel shaders that we have to do manually, and write 59 * tessellation factors in tessellation control shaders. The prolog and epilog 60 * have many other important responsibilities in various shader stages. 61 * They don't just "emulate legacy stuff". 62 * 63 * Monolithic shaders are shaders where the parts are combined before LLVM 64 * compilation, and the whole thing is compiled and optimized as one unit with 65 * one binary on the output. The result is the same as the non-monolithic 66 * shader, but the final code can be better, because LLVM can optimize across 67 * all shader parts. Monolithic shaders aren't usually used except for these 68 * special cases: 69 * 70 * 1) Some rarely-used states require modification of the main shader part 71 * itself, and in such cases, only the monolithic shader variant is 72 * compiled, and that's always done on the first use. 73 * 74 * 2) When we do cross-stage optimizations for separate shader objects and 75 * e.g. eliminate unused shader varyings, the resulting optimized shader 76 * variants are always compiled as monolithic shaders, and always 77 * asynchronously (i.e. not stalling ongoing rendering). We call them 78 * "optimized monolithic" shaders. The important property here is that 79 * the non-monolithic unoptimized shader variant is always available for use 80 * when the asynchronous compilation of the optimized shader is not done 81 * yet. 82 * 83 * Starting with GFX9 chips, some shader stages are merged, and the number of 84 * shader parts per shader increased. The complete new list of shader parts is: 85 * - 1st shader: prolog part 86 * - 1st shader: main part 87 * - 2nd shader: prolog part 88 * - 2nd shader: main part 89 * - 2nd shader: epilog part 90 */ 91 92/* How linking shader inputs and outputs between vertex, tessellation, and 93 * geometry shaders works. 94 * 95 * Inputs and outputs between shaders are stored in a buffer. This buffer 96 * lives in LDS (typical case for tessellation), but it can also live 97 * in memory (ESGS). Each input or output has a fixed location within a vertex. 98 * The highest used input or output determines the stride between vertices. 99 * 100 * Since GS and tessellation are only possible in the OpenGL core profile, 101 * only these semantics are valid for per-vertex data: 102 * 103 * Name Location 104 * 105 * POSITION 0 106 * PSIZE 1 107 * CLIPDIST0..1 2..3 108 * CULLDIST0..1 (not implemented) 109 * GENERIC0..31 4..35 110 * 111 * For example, a shader only writing GENERIC0 has the output stride of 5. 112 * 113 * Only these semantics are valid for per-patch data: 114 * 115 * Name Location 116 * 117 * TESSOUTER 0 118 * TESSINNER 1 119 * PATCH0..29 2..31 120 * 121 * That's how independent shaders agree on input and output locations. 122 * The si_shader_io_get_unique_index function assigns the locations. 123 * 124 * For tessellation, other required information for calculating the input and 125 * output addresses like the vertex stride, the patch stride, and the offsets 126 * where per-vertex and per-patch data start, is passed to the shader via 127 * user data SGPRs. The offsets and strides are calculated at draw time and 128 * aren't available at compile time. 129 */ 130 131#ifndef SI_SHADER_H 132#define SI_SHADER_H 133 134#include "ac_binary.h" 135#include "ac_llvm_build.h" 136#include "ac_llvm_util.h" 137#include "util/simple_mtx.h" 138#include "util/u_inlines.h" 139#include "util/u_live_shader_cache.h" 140#include "util/u_queue.h" 141#include "si_pm4.h" 142 143#include <stdio.h> 144 145#ifdef __cplusplus 146extern "C" { 147#endif 148 149// Use LDS symbols when supported by LLVM. Can be disabled for testing the old 150// path on newer LLVM for now. Should be removed in the long term. 151#define USE_LDS_SYMBOLS (true) 152 153struct nir_shader; 154struct si_shader; 155struct si_context; 156 157#define SI_MAX_ATTRIBS 16 158#define SI_MAX_VS_OUTPUTS 40 159 160#define SI_NGG_PRIM_EDGE_FLAG_BITS ((1 << 9) | (1 << 19) | (1 << 29)) 161 162#define SI_PS_INPUT_CNTL_0000 (S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(0)) 163#define SI_PS_INPUT_CNTL_0001 (S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(3)) 164#define SI_PS_INPUT_CNTL_UNUSED SI_PS_INPUT_CNTL_0000 165/* D3D9 behaviour for COLOR0 requires 0001. GL is undefined. */ 166#define SI_PS_INPUT_CNTL_UNUSED_COLOR0 SI_PS_INPUT_CNTL_0001 167 168/* SGPR user data indices */ 169enum 170{ 171 SI_SGPR_INTERNAL_BINDINGS, 172 SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES, 173 SI_SGPR_CONST_AND_SHADER_BUFFERS, /* or just a constant buffer 0 pointer */ 174 SI_SGPR_SAMPLERS_AND_IMAGES, 175 SI_NUM_RESOURCE_SGPRS, 176 177 /* API VS, TES without GS, GS copy shader */ 178 SI_SGPR_VS_STATE_BITS = SI_NUM_RESOURCE_SGPRS, 179 SI_NUM_VS_STATE_RESOURCE_SGPRS, 180 181 /* all VS variants */ 182 SI_SGPR_BASE_VERTEX = SI_NUM_VS_STATE_RESOURCE_SGPRS, 183 SI_SGPR_DRAWID, 184 SI_SGPR_START_INSTANCE, 185 SI_VS_NUM_USER_SGPR, 186 187 SI_SGPR_VS_BLIT_DATA = SI_SGPR_CONST_AND_SHADER_BUFFERS, 188 189 /* TES */ 190 SI_SGPR_TES_OFFCHIP_LAYOUT = SI_NUM_VS_STATE_RESOURCE_SGPRS, 191 SI_SGPR_TES_OFFCHIP_ADDR, 192 SI_TES_NUM_USER_SGPR, 193 194 /* GFX6-8: TCS only */ 195 GFX6_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS, 196 GFX6_SGPR_TCS_OUT_OFFSETS, 197 GFX6_SGPR_TCS_OUT_LAYOUT, 198 GFX6_SGPR_TCS_IN_LAYOUT, 199 GFX6_TCS_NUM_USER_SGPR, 200 201 /* GFX9: Merged shaders. */ 202 /* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO (SGPR0). */ 203 /* 2ND_SAMPLERS_AND_IMAGES is set in USER_DATA_ADDR_HI (SGPR1). */ 204 GFX9_MERGED_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR, 205 206 /* GFX9: Merged LS-HS (VS-TCS) only. */ 207 GFX9_SGPR_TCS_OFFCHIP_LAYOUT = GFX9_MERGED_NUM_USER_SGPR, 208 GFX9_SGPR_TCS_OUT_OFFSETS, 209 GFX9_SGPR_TCS_OUT_LAYOUT, 210 GFX9_TCS_NUM_USER_SGPR, 211 212 /* GS limits */ 213 GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS, 214 GFX9_VSGS_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR, 215 GFX9_TESGS_NUM_USER_SGPR = SI_TES_NUM_USER_SGPR, 216 SI_GSCOPY_NUM_USER_SGPR = SI_NUM_VS_STATE_RESOURCE_SGPRS, 217 218 /* PS only */ 219 SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS, 220 SI_PS_NUM_USER_SGPR, 221 222 /* The value has to be 12, because the hw requires that descriptors 223 * are aligned to 4 SGPRs. 224 */ 225 SI_SGPR_VS_VB_DESCRIPTOR_FIRST = 12, 226}; 227 228/* LLVM function parameter indices */ 229enum 230{ 231 SI_NUM_RESOURCE_PARAMS = 4, 232 233 /* PS only parameters */ 234 SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS, 235 SI_PARAM_PRIM_MASK, 236 SI_PARAM_PERSP_SAMPLE, 237 SI_PARAM_PERSP_CENTER, 238 SI_PARAM_PERSP_CENTROID, 239 SI_PARAM_PERSP_PULL_MODEL, 240 SI_PARAM_LINEAR_SAMPLE, 241 SI_PARAM_LINEAR_CENTER, 242 SI_PARAM_LINEAR_CENTROID, 243 SI_PARAM_LINE_STIPPLE_TEX, 244 SI_PARAM_POS_X_FLOAT, 245 SI_PARAM_POS_Y_FLOAT, 246 SI_PARAM_POS_Z_FLOAT, 247 SI_PARAM_POS_W_FLOAT, 248 SI_PARAM_FRONT_FACE, 249 SI_PARAM_ANCILLARY, 250 SI_PARAM_SAMPLE_COVERAGE, 251 SI_PARAM_POS_FIXED_PT, 252 253 SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */ 254}; 255 256/* Fields of driver-defined VS state SGPR. */ 257#define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x)&0x1) << 0) 258#define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE 259#define S_VS_STATE_INDEXED(x) (((unsigned)(x)&0x1) << 1) 260#define C_VS_STATE_INDEXED 0xFFFFFFFD 261#define S_VS_STATE_OUTPRIM(x) (((unsigned)(x)&0x3) << 2) 262#define C_VS_STATE_OUTPRIM 0xFFFFFFF3 263#define S_VS_STATE_PROVOKING_VTX_INDEX(x) (((unsigned)(x)&0x3) << 4) 264#define C_VS_STATE_PROVOKING_VTX_INDEX 0xFFFFFFCF 265#define S_VS_STATE_STREAMOUT_QUERY_ENABLED(x) (((unsigned)(x)&0x1) << 6) 266#define C_VS_STATE_STREAMOUT_QUERY_ENABLED 0xFFFFFFBF 267#define S_VS_STATE_SMALL_PRIM_PRECISION(x) (((unsigned)(x)&0xF) << 7) 268#define C_VS_STATE_SMALL_PRIM_PRECISION 0xFFFFF87F 269#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x)&0x1FFF) << 11) 270#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFF0007FF 271#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x)&0xFF) << 24) 272#define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF 273 274enum 275{ 276 /* These represent the number of SGPRs the shader uses. */ 277 SI_VS_BLIT_SGPRS_POS = 3, 278 SI_VS_BLIT_SGPRS_POS_COLOR = 7, 279 SI_VS_BLIT_SGPRS_POS_TEXCOORD = 9, 280}; 281 282#define SI_NGG_CULL_ENABLED (1 << 0) /* this implies W, view.xy, and small prim culling */ 283#define SI_NGG_CULL_BACK_FACE (1 << 1) /* back faces */ 284#define SI_NGG_CULL_FRONT_FACE (1 << 2) /* front faces */ 285#define SI_NGG_CULL_LINES (1 << 3) /* the primitive type is lines */ 286 287/** 288 * For VS shader keys, describe any fixups required for vertex fetch. 289 * 290 * \ref log_size, \ref format, and the number of channels are interpreted as 291 * by \ref ac_build_opencoded_load_format. 292 * 293 * Note: all bits 0 (size = 1 byte, num channels = 1, format = float) is an 294 * impossible format and indicates that no fixup is needed (just use 295 * buffer_load_format_xyzw). 296 */ 297union si_vs_fix_fetch { 298 struct { 299 uint8_t log_size : 2; /* 1, 2, 4, 8 or bytes per channel */ 300 uint8_t num_channels_m1 : 2; /* number of channels minus 1 */ 301 uint8_t format : 3; /* AC_FETCH_FORMAT_xxx */ 302 uint8_t reverse : 1; /* reverse XYZ channels */ 303 } u; 304 uint8_t bits; 305}; 306 307struct si_shader; 308 309/* State of the context creating the shader object. */ 310struct si_compiler_ctx_state { 311 /* Should only be used by si_init_shader_selector_async and 312 * si_build_shader_variant if thread_index == -1 (non-threaded). */ 313 struct ac_llvm_compiler *compiler; 314 315 /* Used if thread_index == -1 or if debug.async is true. */ 316 struct pipe_debug_callback debug; 317 318 /* Used for creating the log string for gallium/ddebug. */ 319 bool is_debug_context; 320}; 321 322enum si_color_output_type { 323 SI_TYPE_ANY32, 324 SI_TYPE_FLOAT16, 325 SI_TYPE_INT16, 326 SI_TYPE_UINT16, 327}; 328 329union si_input_info { 330 struct { 331 ubyte semantic; 332 ubyte interpolate; 333 ubyte fp16_lo_hi_valid; 334 ubyte usage_mask; 335 }; 336 uint32_t _unused; /* this just forces 4-byte alignment */ 337}; 338 339struct si_shader_info { 340 shader_info base; 341 342 gl_shader_stage stage; 343 344 ubyte num_inputs; 345 ubyte num_outputs; 346 union si_input_info input[PIPE_MAX_SHADER_INPUTS]; 347 ubyte output_semantic[PIPE_MAX_SHADER_OUTPUTS]; 348 ubyte output_usagemask[PIPE_MAX_SHADER_OUTPUTS]; 349 ubyte output_readmask[PIPE_MAX_SHADER_OUTPUTS]; 350 ubyte output_streams[PIPE_MAX_SHADER_OUTPUTS]; 351 ubyte output_type[PIPE_MAX_SHADER_OUTPUTS]; /* enum nir_alu_type */ 352 353 ubyte color_interpolate[2]; 354 ubyte color_interpolate_loc[2]; 355 356 int constbuf0_num_slots; 357 ubyte num_stream_output_components[4]; 358 359 uint num_memory_stores; 360 361 ubyte colors_read; /**< which color components are read by the FS */ 362 ubyte colors_written; 363 uint16_t output_color_types; /**< Each bit pair is enum si_color_output_type */ 364 bool color0_writes_all_cbufs; /**< gl_FragColor */ 365 bool reads_samplemask; /**< does fragment shader read sample mask? */ 366 bool reads_tess_factors; /**< If TES reads TESSINNER or TESSOUTER */ 367 bool writes_z; /**< does fragment shader write Z value? */ 368 bool writes_stencil; /**< does fragment shader write stencil value? */ 369 bool writes_samplemask; /**< does fragment shader write sample mask? */ 370 bool writes_edgeflag; /**< vertex shader outputs edgeflag */ 371 bool uses_interp_color; 372 bool uses_persp_center_color; 373 bool uses_persp_centroid_color; 374 bool uses_persp_sample_color; 375 bool uses_persp_center; 376 bool uses_persp_centroid; 377 bool uses_persp_sample; 378 bool uses_linear_center; 379 bool uses_linear_centroid; 380 bool uses_linear_sample; 381 bool uses_interp_at_sample; 382 bool uses_instanceid; 383 bool uses_base_vertex; 384 bool uses_base_instance; 385 bool uses_drawid; 386 bool uses_primid; 387 bool uses_frontface; 388 bool uses_invocationid; 389 bool uses_thread_id[3]; 390 bool uses_block_id[3]; 391 bool uses_variable_block_size; 392 bool uses_grid_size; 393 bool uses_subgroup_info; 394 bool writes_position; 395 bool writes_psize; 396 bool writes_clipvertex; 397 bool writes_primid; 398 bool writes_viewport_index; 399 bool writes_layer; 400 bool uses_bindless_samplers; 401 bool uses_bindless_images; 402 bool uses_indirect_descriptor; 403 404 bool uses_vmem_return_type_sampler_or_bvh; 405 bool uses_vmem_return_type_other; /* all other VMEM loads and atomics with return */ 406 407 /** Whether all codepaths write tess factors in all invocations. */ 408 bool tessfactors_are_def_in_all_invocs; 409 410 /* A flag to check if vrs2x2 can be enabled to reduce number of 411 * fragment shader invocations if flat shading. 412 */ 413 bool allow_flat_shading; 414 415 /* Optimization: if the texture bound to this texunit has been cleared to 1, 416 * then the draw can be skipped (see si_draw_vbo_skip_noop). Initially the 417 * value is 0xff (undetermined) and can be later changed to 0 (= false) or 418 * texunit + 1. 419 */ 420 uint8_t writes_1_if_tex_is_1; 421}; 422 423/* A shader selector is a gallium CSO and contains shader variants and 424 * binaries for one NIR program. This can be shared by multiple contexts. 425 */ 426struct si_shader_selector { 427 struct util_live_shader base; 428 struct si_screen *screen; 429 struct util_queue_fence ready; 430 struct si_compiler_ctx_state compiler_ctx_state; 431 432 simple_mtx_t mutex; 433 struct si_shader *first_variant; /* immutable after the first variant */ 434 struct si_shader *last_variant; /* mutable */ 435 436 /* The compiled NIR shader without a prolog and/or epilog (not 437 * uploaded to a buffer object). 438 */ 439 struct si_shader *main_shader_part; 440 struct si_shader *main_shader_part_ls; /* as_ls is set in the key */ 441 struct si_shader *main_shader_part_es; /* as_es is set in the key */ 442 struct si_shader *main_shader_part_ngg; /* as_ngg is set in the key */ 443 struct si_shader *main_shader_part_ngg_es; /* for Wave32 TES before legacy GS */ 444 445 struct si_shader *gs_copy_shader; 446 447 struct nir_shader *nir; 448 void *nir_binary; 449 unsigned nir_size; 450 451 struct pipe_stream_output_info so; 452 struct si_shader_info info; 453 454 enum pipe_shader_type pipe_shader_type; 455 ubyte const_and_shader_buf_descriptors_index; 456 ubyte sampler_and_images_descriptors_index; 457 bool vs_needs_prolog; 458 ubyte cs_shaderbufs_sgpr_index; 459 ubyte cs_num_shaderbufs_in_user_sgprs; 460 ubyte cs_images_sgpr_index; 461 ubyte cs_images_num_sgprs; 462 ubyte cs_num_images_in_user_sgprs; 463 ubyte num_vs_inputs; 464 ubyte num_vbos_in_user_sgprs; 465 unsigned ngg_cull_vert_threshold; /* UINT32_MAX = disabled */ 466 ubyte clipdist_mask; 467 ubyte culldist_mask; 468 enum pipe_prim_type rast_prim; 469 470 /* ES parameters. */ 471 uint16_t esgs_itemsize; /* vertex stride */ 472 uint16_t lshs_vertex_stride; 473 474 /* GS parameters. */ 475 uint16_t gsvs_vertex_size; 476 ubyte gs_input_verts_per_prim; 477 unsigned max_gsvs_emit_size; 478 uint16_t enabled_streamout_buffer_mask; 479 bool tess_turns_off_ngg; 480 481 /* PS parameters. */ 482 ubyte color_attr_index[2]; 483 unsigned db_shader_control; 484 /* Set 0xf or 0x0 (4 bits) per each written output. 485 * ANDed with spi_shader_col_format. 486 */ 487 unsigned colors_written_4bit; 488 489 uint64_t outputs_written_before_ps; /* "get_unique_index" bits */ 490 uint64_t outputs_written; /* "get_unique_index" bits */ 491 uint32_t patch_outputs_written; /* "get_unique_index_patch" bits */ 492 493 uint64_t inputs_read; /* "get_unique_index" bits */ 494 uint64_t tcs_vgpr_only_inputs; /* TCS inputs that are only in VGPRs, not LDS. */ 495 496 /* bitmasks of used descriptor slots */ 497 uint64_t active_const_and_shader_buffers; 498 uint64_t active_samplers_and_images; 499}; 500 501/* Valid shader configurations: 502 * 503 * API shaders VS | TCS | TES | GS |pass| PS 504 * are compiled as: | | | |thru| 505 * | | | | | 506 * Only VS & PS: VS | | | | | PS 507 * GFX6 - with GS: ES | | | GS | VS | PS 508 * - with tess: LS | HS | VS | | | PS 509 * - with both: LS | HS | ES | GS | VS | PS 510 * GFX9 - with GS: -> | | | GS | VS | PS 511 * - with tess: -> | HS | VS | | | PS 512 * - with both: -> | HS | -> | GS | VS | PS 513 * | | | | | 514 * NGG - VS & PS: GS | | | | | PS 515 * (GFX10+) - with GS: -> | | | GS | | PS 516 * - with tess: -> | HS | GS | | | PS 517 * - with both: -> | HS | -> | GS | | PS 518 * 519 * -> = merged with the next stage 520 */ 521 522/* Use the byte alignment for all following structure members for optimal 523 * shader key memory footprint. 524 */ 525#pragma pack(push, 1) 526 527/* Common VS bits between the shader key and the prolog key. */ 528struct si_vs_prolog_bits { 529 /* - If neither "is_one" nor "is_fetched" has a bit set, the instance 530 * divisor is 0. 531 * - If "is_one" has a bit set, the instance divisor is 1. 532 * - If "is_fetched" has a bit set, the instance divisor will be loaded 533 * from the constant buffer. 534 */ 535 uint16_t instance_divisor_is_one; /* bitmask of inputs */ 536 uint16_t instance_divisor_is_fetched; /* bitmask of inputs */ 537 unsigned ls_vgpr_fix : 1; 538}; 539 540/* Common TCS bits between the shader key and the epilog key. */ 541struct si_tcs_epilog_bits { 542 unsigned prim_mode : 3; 543 unsigned invoc0_tess_factors_are_def : 1; 544 unsigned tes_reads_tess_factors : 1; 545}; 546 547struct si_gs_prolog_bits { 548 unsigned tri_strip_adj_fix : 1; 549}; 550 551/* Common PS bits between the shader key and the prolog key. */ 552struct si_ps_prolog_bits { 553 unsigned color_two_side : 1; 554 unsigned flatshade_colors : 1; 555 unsigned poly_stipple : 1; 556 unsigned force_persp_sample_interp : 1; 557 unsigned force_linear_sample_interp : 1; 558 unsigned force_persp_center_interp : 1; 559 unsigned force_linear_center_interp : 1; 560 unsigned bc_optimize_for_persp : 1; 561 unsigned bc_optimize_for_linear : 1; 562 unsigned samplemask_log_ps_iter : 3; 563}; 564 565/* Common PS bits between the shader key and the epilog key. */ 566struct si_ps_epilog_bits { 567 unsigned spi_shader_col_format; 568 unsigned color_is_int8 : 8; 569 unsigned color_is_int10 : 8; 570 unsigned last_cbuf : 3; 571 unsigned alpha_func : 3; 572 unsigned alpha_to_one : 1; 573 unsigned poly_line_smoothing : 1; 574 unsigned clamp_color : 1; 575}; 576 577union si_shader_part_key { 578 struct { 579 struct si_vs_prolog_bits states; 580 unsigned num_input_sgprs : 6; 581 /* For merged stages such as LS-HS, HS input VGPRs are first. */ 582 unsigned num_merged_next_stage_vgprs : 3; 583 unsigned num_inputs : 5; 584 unsigned as_ls : 1; 585 unsigned as_es : 1; 586 unsigned as_ngg : 1; 587 unsigned load_vgprs_after_culling : 1; 588 /* Prologs for monolithic shaders shouldn't set EXEC. */ 589 unsigned is_monolithic : 1; 590 } vs_prolog; 591 struct { 592 struct si_tcs_epilog_bits states; 593 } tcs_epilog; 594 struct { 595 struct si_gs_prolog_bits states; 596 unsigned as_ngg : 1; 597 } gs_prolog; 598 struct { 599 struct si_ps_prolog_bits states; 600 unsigned num_input_sgprs : 6; 601 unsigned num_input_vgprs : 5; 602 /* Color interpolation and two-side color selection. */ 603 unsigned colors_read : 8; /* color input components read */ 604 unsigned num_interp_inputs : 5; /* BCOLOR is at this location */ 605 unsigned face_vgpr_index : 5; 606 unsigned ancillary_vgpr_index : 5; 607 unsigned wqm : 1; 608 char color_attr_index[2]; 609 signed char color_interp_vgpr_index[2]; /* -1 == constant */ 610 } ps_prolog; 611 struct { 612 struct si_ps_epilog_bits states; 613 unsigned colors_written : 8; 614 unsigned color_types : 16; 615 unsigned writes_z : 1; 616 unsigned writes_stencil : 1; 617 unsigned writes_samplemask : 1; 618 } ps_epilog; 619}; 620 621struct si_shader_key { 622 /* Prolog and epilog flags. */ 623 union { 624 struct { 625 struct si_vs_prolog_bits prolog; 626 } vs; 627 struct { 628 struct si_vs_prolog_bits ls_prolog; /* for merged LS-HS */ 629 struct si_shader_selector *ls; /* for merged LS-HS */ 630 struct si_tcs_epilog_bits epilog; 631 } tcs; /* tessellation control shader */ 632 struct { 633 struct si_vs_prolog_bits vs_prolog; /* for merged ES-GS */ 634 struct si_shader_selector *es; /* for merged ES-GS */ 635 struct si_gs_prolog_bits prolog; 636 } gs; 637 struct { 638 struct si_ps_prolog_bits prolog; 639 struct si_ps_epilog_bits epilog; 640 } ps; 641 } part; 642 643 /* These three are initially set according to the NEXT_SHADER property, 644 * or guessed if the property doesn't seem correct. 645 */ 646 unsigned as_es : 1; /* whether it's a shader before GS */ 647 unsigned as_ls : 1; /* whether it's VS before TCS */ 648 unsigned as_ngg : 1; /* whether it's the last GE stage and NGG is enabled, 649 also set for the stage right before GS */ 650 651 /* Flags for monolithic compilation only. */ 652 struct { 653 /* Whether fetch should be opencoded according to vs_fix_fetch. 654 * Otherwise, if vs_fix_fetch is non-zero, buffer_load_format_xyzw 655 * with minimal fixups is used. */ 656 uint16_t vs_fetch_opencode; 657 union si_vs_fix_fetch vs_fix_fetch[SI_MAX_ATTRIBS]; 658 659 union { 660 uint64_t ff_tcs_inputs_to_copy; /* for fixed-func TCS */ 661 /* When PS needs PrimID and GS is disabled. */ 662 unsigned vs_export_prim_id : 1; 663 struct { 664 unsigned interpolate_at_sample_force_center : 1; 665 unsigned fbfetch_msaa : 1; 666 unsigned fbfetch_is_1D : 1; 667 unsigned fbfetch_layered : 1; 668 } ps; 669 } u; 670 } mono; 671 672 /* Optimization flags for asynchronous compilation only. */ 673 struct { 674 /* For HW VS (it can be VS, TES, GS) */ 675 uint64_t kill_outputs; /* "get_unique_index" bits */ 676 unsigned kill_clip_distances : 8; 677 unsigned kill_pointsize : 1; 678 679 /* For NGG VS and TES. */ 680 unsigned ngg_culling : 4; /* SI_NGG_CULL_* */ 681 682 /* For shaders where monolithic variants have better code. 683 * 684 * This is a flag that has no effect on code generation, 685 * but forces monolithic shaders to be used as soon as 686 * possible, because it's in the "opt" group. 687 */ 688 unsigned prefer_mono : 1; 689 690 /* VS and TCS have the same number of patch vertices. */ 691 unsigned same_patch_vertices:1; 692 693 unsigned inline_uniforms:1; 694 695 /* This must be kept last to limit the number of variants 696 * depending only on the uniform values. 697 */ 698 uint32_t inlined_uniform_values[MAX_INLINABLE_UNIFORMS]; 699 } opt; 700}; 701 702/* Restore the pack alignment to default. */ 703#pragma pack(pop) 704 705/* GCN-specific shader info. */ 706struct si_shader_binary_info { 707 ubyte vs_output_param_offset[SI_MAX_VS_OUTPUTS]; 708 uint32_t vs_output_ps_input_cntl[NUM_TOTAL_VARYING_SLOTS]; 709 ubyte num_input_sgprs; 710 ubyte num_input_vgprs; 711 signed char face_vgpr_index; 712 signed char ancillary_vgpr_index; 713 bool uses_instanceid; 714 ubyte nr_pos_exports; 715 ubyte nr_param_exports; 716 unsigned private_mem_vgprs; 717 unsigned max_simd_waves; 718}; 719 720struct si_shader_binary { 721 const char *elf_buffer; 722 size_t elf_size; 723 724 char *uploaded_code; 725 size_t uploaded_code_size; 726 727 char *llvm_ir_string; 728}; 729 730struct gfx9_gs_info { 731 unsigned es_verts_per_subgroup; 732 unsigned gs_prims_per_subgroup; 733 unsigned gs_inst_prims_in_subgroup; 734 unsigned max_prims_per_subgroup; 735 unsigned esgs_ring_size; /* in bytes */ 736}; 737 738#define SI_NUM_VGT_STAGES_KEY_BITS 5 739#define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS) 740 741/* The VGT_SHADER_STAGES key used to index the table of precomputed values. 742 * Some fields are set by state-change calls, most are set by draw_vbo. 743 */ 744union si_vgt_stages_key { 745 struct { 746#if UTIL_ARCH_LITTLE_ENDIAN 747 uint8_t tess : 1; 748 uint8_t gs : 1; 749 uint8_t ngg_passthrough : 1; 750 uint8_t ngg : 1; /* gfx10+ */ 751 uint8_t streamout : 1; /* only used with NGG */ 752 uint8_t _pad : 8 - SI_NUM_VGT_STAGES_KEY_BITS; 753#else /* UTIL_ARCH_BIG_ENDIAN */ 754 uint8_t _pad : 8 - SI_NUM_VGT_STAGES_KEY_BITS; 755 uint8_t streamout : 1; 756 uint8_t ngg : 1; 757 uint8_t ngg_passthrough : 1; 758 uint8_t gs : 1; 759 uint8_t tess : 1; 760#endif 761 } u; 762 uint8_t index; 763}; 764 765struct si_shader { 766 struct si_pm4_state pm4; /* base class */ 767 struct si_compiler_ctx_state compiler_ctx_state; 768 769 struct si_shader_selector *selector; 770 struct si_shader_selector *previous_stage_sel; /* for refcounting */ 771 struct si_shader *next_variant; 772 773 struct si_shader_part *prolog; 774 struct si_shader *previous_stage; /* for GFX9 */ 775 struct si_shader_part *prolog2; 776 struct si_shader_part *epilog; 777 778 struct si_resource *bo; 779 struct si_resource *scratch_bo; 780 struct si_shader_key key; 781 struct util_queue_fence ready; 782 bool compilation_failed; 783 bool is_monolithic; 784 bool is_optimized; 785 bool is_binary_shared; 786 bool is_gs_copy_shader; 787 788 /* The following data is all that's needed for binary shaders. */ 789 struct si_shader_binary binary; 790 struct ac_shader_config config; 791 struct si_shader_binary_info info; 792 793 /* SI_SGPR_VS_STATE_BITS */ 794 bool uses_vs_state_provoking_vertex; 795 bool uses_vs_state_outprim; 796 797 bool uses_base_instance; 798 799 struct { 800 uint16_t ngg_emit_size; /* in dwords */ 801 uint16_t hw_max_esverts; 802 uint16_t max_gsprims; 803 uint16_t max_out_verts; 804 uint16_t prim_amp_factor; 805 bool max_vert_out_per_gs_instance; 806 } ngg; 807 808 /* Shader key + LLVM IR + disassembly + statistics. 809 * Generated for debug contexts only. 810 */ 811 char *shader_log; 812 size_t shader_log_size; 813 814 struct gfx9_gs_info gs_info; 815 816 /* For save precompute context registers values. */ 817 union { 818 struct { 819 unsigned vgt_gsvs_ring_offset_1; 820 unsigned vgt_gsvs_ring_offset_2; 821 unsigned vgt_gsvs_ring_offset_3; 822 unsigned vgt_gsvs_ring_itemsize; 823 unsigned vgt_gs_max_vert_out; 824 unsigned vgt_gs_vert_itemsize; 825 unsigned vgt_gs_vert_itemsize_1; 826 unsigned vgt_gs_vert_itemsize_2; 827 unsigned vgt_gs_vert_itemsize_3; 828 unsigned vgt_gs_instance_cnt; 829 unsigned vgt_gs_onchip_cntl; 830 unsigned vgt_gs_max_prims_per_subgroup; 831 unsigned vgt_esgs_ring_itemsize; 832 unsigned spi_shader_pgm_rsrc3_gs; 833 unsigned spi_shader_pgm_rsrc4_gs; 834 } gs; 835 836 struct { 837 unsigned ge_max_output_per_subgroup; 838 unsigned ge_ngg_subgrp_cntl; 839 unsigned vgt_primitiveid_en; 840 unsigned vgt_gs_onchip_cntl; 841 unsigned vgt_gs_instance_cnt; 842 unsigned vgt_esgs_ring_itemsize; 843 unsigned spi_vs_out_config; 844 unsigned spi_shader_idx_format; 845 unsigned spi_shader_pos_format; 846 unsigned pa_cl_vte_cntl; 847 unsigned pa_cl_ngg_cntl; 848 unsigned vgt_gs_max_vert_out; /* for API GS */ 849 unsigned ge_pc_alloc; /* uconfig register */ 850 unsigned spi_shader_pgm_rsrc3_gs; 851 unsigned spi_shader_pgm_rsrc4_gs; 852 union si_vgt_stages_key vgt_stages; 853 } ngg; 854 855 struct { 856 unsigned vgt_gs_mode; 857 unsigned vgt_primitiveid_en; 858 unsigned vgt_reuse_off; 859 unsigned spi_vs_out_config; 860 unsigned spi_shader_pos_format; 861 unsigned pa_cl_vte_cntl; 862 unsigned ge_pc_alloc; /* uconfig register */ 863 } vs; 864 865 struct { 866 unsigned spi_ps_input_ena; 867 unsigned spi_ps_input_addr; 868 unsigned spi_baryc_cntl; 869 unsigned spi_ps_in_control; 870 unsigned spi_shader_z_format; 871 unsigned spi_shader_col_format; 872 unsigned cb_shader_mask; 873 unsigned num_interp; 874 } ps; 875 } ctx_reg; 876 877 /*For save precompute registers value */ 878 unsigned vgt_tf_param; /* VGT_TF_PARAM */ 879 unsigned vgt_vertex_reuse_block_cntl; /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 880 unsigned pa_cl_vs_out_cntl; 881 unsigned ge_cntl; 882}; 883 884struct si_shader_part { 885 struct si_shader_part *next; 886 union si_shader_part_key key; 887 struct si_shader_binary binary; 888 struct ac_shader_config config; 889}; 890 891/* si_shader.c */ 892bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, 893 struct si_shader *shader, struct pipe_debug_callback *debug); 894bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler *compiler, 895 struct si_shader *shader, struct pipe_debug_callback *debug); 896void si_shader_destroy(struct si_shader *shader); 897unsigned si_shader_io_get_unique_index_patch(unsigned semantic); 898unsigned si_shader_io_get_unique_index(unsigned semantic, bool is_varying); 899bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader, 900 uint64_t scratch_va); 901void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader, 902 struct pipe_debug_callback *debug, FILE *f, bool check_debug_option); 903void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shader *shader, 904 struct pipe_debug_callback *debug); 905void si_multiwave_lds_size_workaround(struct si_screen *sscreen, unsigned *lds_size); 906const char *si_get_shader_name(const struct si_shader *shader); 907void si_shader_binary_clean(struct si_shader_binary *binary); 908 909/* si_shader_llvm_gs.c */ 910struct si_shader *si_generate_gs_copy_shader(struct si_screen *sscreen, 911 struct ac_llvm_compiler *compiler, 912 struct si_shader_selector *gs_selector, 913 struct pipe_debug_callback *debug); 914 915/* si_shader_nir.c */ 916void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info); 917void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first); 918void si_nir_late_opts(nir_shader *nir); 919char *si_finalize_nir(struct pipe_screen *screen, void *nirptr); 920 921/* si_state_shaders.c */ 922void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs, 923 struct gfx9_gs_info *out); 924bool gfx10_is_ngg_passthrough(struct si_shader *shader); 925 926/* Inline helpers. */ 927 928/* Return the pointer to the main shader part's pointer. */ 929static inline struct si_shader **si_get_main_shader_part(struct si_shader_selector *sel, 930 const struct si_shader_key *key) 931{ 932 if (key->as_ls) 933 return &sel->main_shader_part_ls; 934 if (key->as_es && key->as_ngg) 935 return &sel->main_shader_part_ngg_es; 936 if (key->as_es) 937 return &sel->main_shader_part_es; 938 if (key->as_ngg) 939 return &sel->main_shader_part_ngg; 940 return &sel->main_shader_part; 941} 942 943static inline bool si_shader_uses_bindless_samplers(struct si_shader_selector *selector) 944{ 945 return selector ? selector->info.uses_bindless_samplers : false; 946} 947 948static inline bool si_shader_uses_bindless_images(struct si_shader_selector *selector) 949{ 950 return selector ? selector->info.uses_bindless_images : false; 951} 952 953static inline bool gfx10_edgeflags_have_effect(struct si_shader *shader) 954{ 955 if (shader->selector->info.stage == MESA_SHADER_VERTEX && 956 !shader->selector->info.base.vs.blit_sgprs_amd && 957 !(shader->key.opt.ngg_culling & SI_NGG_CULL_LINES)) 958 return true; 959 960 return false; 961} 962 963static inline bool gfx10_ngg_writes_user_edgeflags(struct si_shader *shader) 964{ 965 return gfx10_edgeflags_have_effect(shader) && 966 shader->selector->info.writes_edgeflag; 967} 968 969#ifdef __cplusplus 970} 971#endif 972 973#endif 974