brw_fs.h revision 01e04c3f
1/* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28#ifndef BRW_FS_H 29#define BRW_FS_H 30 31#include "brw_shader.h" 32#include "brw_ir_fs.h" 33#include "brw_fs_builder.h" 34#include "compiler/nir/nir.h" 35 36struct bblock_t; 37namespace { 38 struct acp_entry; 39} 40 41namespace brw { 42 class fs_live_variables; 43} 44 45struct brw_gs_compile; 46 47static inline fs_reg 48offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta) 49{ 50 return offset(reg, bld.dispatch_width(), delta); 51} 52 53#define UBO_START ((1 << 16) - 4) 54 55/** 56 * The fragment shader front-end. 57 * 58 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR. 59 */ 60class fs_visitor : public backend_shader 61{ 62public: 63 fs_visitor(const struct brw_compiler *compiler, void *log_data, 64 void *mem_ctx, 65 const void *key, 66 struct brw_stage_prog_data *prog_data, 67 struct gl_program *prog, 68 const nir_shader *shader, 69 unsigned dispatch_width, 70 int shader_time_index, 71 const struct brw_vue_map *input_vue_map = NULL); 72 fs_visitor(const struct brw_compiler *compiler, void *log_data, 73 void *mem_ctx, 74 struct brw_gs_compile *gs_compile, 75 struct brw_gs_prog_data *prog_data, 76 const nir_shader *shader, 77 int shader_time_index); 78 void init(); 79 ~fs_visitor(); 80 81 fs_reg vgrf(const glsl_type *const type); 82 void import_uniforms(fs_visitor *v); 83 void setup_uniform_clipplane_values(); 84 void compute_clip_distance(); 85 86 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld, 87 const fs_reg &dst, 88 const fs_reg &surf_index, 89 const fs_reg &varying_offset, 90 uint32_t const_offset); 91 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf); 92 93 bool run_fs(bool allow_spilling, bool do_rep_send); 94 bool run_vs(); 95 bool run_tcs_single_patch(); 96 bool run_tes(); 97 bool run_gs(); 98 bool run_cs(unsigned min_dispatch_width); 99 void optimize(); 100 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling); 101 void setup_fs_payload_gen4(); 102 void setup_fs_payload_gen6(); 103 void setup_vs_payload(); 104 void setup_gs_payload(); 105 void setup_cs_payload(); 106 void fixup_3src_null_dest(); 107 void assign_curb_setup(); 108 void calculate_urb_setup(); 109 void assign_urb_setup(); 110 void convert_attr_sources_to_hw_regs(fs_inst *inst); 111 void assign_vs_urb_setup(); 112 void assign_tcs_single_patch_urb_setup(); 113 void assign_tes_urb_setup(); 114 void assign_gs_urb_setup(); 115 bool assign_regs(bool allow_spilling, bool spill_all); 116 void assign_regs_trivial(); 117 void calculate_payload_ranges(int payload_node_count, 118 int *payload_last_use_ip); 119 void setup_payload_interference(struct ra_graph *g, int payload_reg_count, 120 int first_payload_node); 121 int choose_spill_reg(struct ra_graph *g); 122 void spill_reg(int spill_reg); 123 void split_virtual_grfs(); 124 bool compact_virtual_grfs(); 125 void assign_constant_locations(); 126 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index, 127 unsigned *out_pull_index); 128 void lower_constant_loads(); 129 void invalidate_live_intervals(); 130 void calculate_live_intervals(); 131 void calculate_register_pressure(); 132 void validate(); 133 bool opt_algebraic(); 134 bool opt_redundant_discard_jumps(); 135 bool opt_cse(); 136 bool opt_cse_local(bblock_t *block); 137 bool opt_copy_propagation(); 138 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry); 139 bool try_constant_propagate(fs_inst *inst, acp_entry *entry); 140 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block, 141 exec_list *acp); 142 bool opt_drop_redundant_mov_to_flags(); 143 bool opt_register_renaming(); 144 bool opt_bank_conflicts(); 145 unsigned bank_conflict_cycles(const fs_inst *inst) const; 146 bool register_coalesce(); 147 bool compute_to_mrf(); 148 bool eliminate_find_live_channel(); 149 bool dead_code_eliminate(); 150 bool remove_duplicate_mrf_writes(); 151 bool remove_extra_rounding_modes(); 152 153 bool opt_sampler_eot(); 154 bool virtual_grf_interferes(int a, int b); 155 void schedule_instructions(instruction_scheduler_mode mode); 156 void insert_gen4_send_dependency_workarounds(); 157 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block, 158 fs_inst *inst); 159 void insert_gen4_post_send_dependency_workarounds(bblock_t *block, 160 fs_inst *inst); 161 void vfail(const char *msg, va_list args); 162 void fail(const char *msg, ...); 163 void limit_dispatch_width(unsigned n, const char *msg); 164 void lower_uniform_pull_constant_loads(); 165 bool lower_load_payload(); 166 bool lower_pack(); 167 bool lower_conversions(); 168 bool lower_logical_sends(); 169 bool lower_integer_multiplication(); 170 bool lower_minmax(); 171 bool lower_simd_width(); 172 bool opt_combine_constants(); 173 174 void emit_dummy_fs(); 175 void emit_repclear_shader(); 176 void emit_fragcoord_interpolation(fs_reg wpos); 177 fs_reg *emit_frontfacing_interpolation(); 178 fs_reg *emit_samplepos_setup(); 179 fs_reg *emit_sampleid_setup(); 180 fs_reg *emit_samplemaskin_setup(); 181 void emit_interpolation_setup_gen4(); 182 void emit_interpolation_setup_gen6(); 183 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos); 184 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components, 185 const fs_reg &sampler); 186 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst); 187 fs_reg resolve_source_modifiers(const fs_reg &src); 188 void emit_discard_jump(); 189 bool opt_peephole_sel(); 190 bool opt_peephole_csel(); 191 bool opt_peephole_predicated_break(); 192 bool opt_saturate_propagation(); 193 bool opt_cmod_propagation(); 194 bool opt_zero_samples(); 195 196 void emit_nir_code(); 197 void nir_setup_outputs(); 198 void nir_setup_uniforms(); 199 void nir_emit_system_values(); 200 void nir_emit_impl(nir_function_impl *impl); 201 void nir_emit_cf_list(exec_list *list); 202 void nir_emit_if(nir_if *if_stmt); 203 void nir_emit_loop(nir_loop *loop); 204 void nir_emit_block(nir_block *block); 205 void nir_emit_instr(nir_instr *instr); 206 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr); 207 void nir_emit_load_const(const brw::fs_builder &bld, 208 nir_load_const_instr *instr); 209 void nir_emit_vs_intrinsic(const brw::fs_builder &bld, 210 nir_intrinsic_instr *instr); 211 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld, 212 nir_intrinsic_instr *instr); 213 void nir_emit_gs_intrinsic(const brw::fs_builder &bld, 214 nir_intrinsic_instr *instr); 215 void nir_emit_fs_intrinsic(const brw::fs_builder &bld, 216 nir_intrinsic_instr *instr); 217 void nir_emit_cs_intrinsic(const brw::fs_builder &bld, 218 nir_intrinsic_instr *instr); 219 fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld, 220 nir_intrinsic_instr *instr); 221 void nir_emit_intrinsic(const brw::fs_builder &bld, 222 nir_intrinsic_instr *instr); 223 void nir_emit_tes_intrinsic(const brw::fs_builder &bld, 224 nir_intrinsic_instr *instr); 225 void nir_emit_ssbo_atomic(const brw::fs_builder &bld, 226 int op, nir_intrinsic_instr *instr); 227 void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld, 228 int op, nir_intrinsic_instr *instr); 229 void nir_emit_shared_atomic(const brw::fs_builder &bld, 230 int op, nir_intrinsic_instr *instr); 231 void nir_emit_shared_atomic_float(const brw::fs_builder &bld, 232 int op, nir_intrinsic_instr *instr); 233 void nir_emit_texture(const brw::fs_builder &bld, 234 nir_tex_instr *instr); 235 void nir_emit_jump(const brw::fs_builder &bld, 236 nir_jump_instr *instr); 237 fs_reg get_nir_src(const nir_src &src); 238 fs_reg get_nir_src_imm(const nir_src &src); 239 fs_reg get_nir_dest(const nir_dest &dest); 240 fs_reg get_indirect_offset(nir_intrinsic_instr *instr); 241 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst, 242 unsigned wr_mask); 243 244 bool optimize_extract_to_float(nir_alu_instr *instr, 245 const fs_reg &result); 246 bool optimize_frontfacing_ternary(nir_alu_instr *instr, 247 const fs_reg &result); 248 249 void emit_alpha_test(); 250 fs_inst *emit_single_fb_write(const brw::fs_builder &bld, 251 fs_reg color1, fs_reg color2, 252 fs_reg src0_alpha, unsigned components); 253 void emit_fb_writes(); 254 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld, 255 const fs_reg &dst, unsigned target); 256 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg()); 257 void set_gs_stream_control_data_bits(const fs_reg &vertex_count, 258 unsigned stream_id); 259 void emit_gs_control_data_bits(const fs_reg &vertex_count); 260 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src); 261 void emit_gs_vertex(const nir_src &vertex_count_nir_src, 262 unsigned stream_id); 263 void emit_gs_thread_end(); 264 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src, 265 unsigned base_offset, const nir_src &offset_src, 266 unsigned num_components, unsigned first_component); 267 void emit_cs_terminate(); 268 fs_reg *emit_cs_work_group_id_setup(); 269 270 void emit_barrier(); 271 272 void emit_shader_time_begin(); 273 void emit_shader_time_end(); 274 void SHADER_TIME_ADD(const brw::fs_builder &bld, 275 int shader_time_subindex, 276 fs_reg value); 277 278 fs_reg get_timestamp(const brw::fs_builder &bld); 279 280 fs_reg interp_reg(int location, int channel); 281 282 int implied_mrf_writes(fs_inst *inst) const; 283 284 virtual void dump_instructions(); 285 virtual void dump_instructions(const char *name); 286 void dump_instruction(backend_instruction *inst); 287 void dump_instruction(backend_instruction *inst, FILE *file); 288 289 const void *const key; 290 const struct brw_sampler_prog_key_data *key_tex; 291 292 struct brw_gs_compile *gs_compile; 293 294 struct brw_stage_prog_data *prog_data; 295 struct gl_program *prog; 296 297 const struct brw_vue_map *input_vue_map; 298 299 int *virtual_grf_start; 300 int *virtual_grf_end; 301 brw::fs_live_variables *live_intervals; 302 303 int *regs_live_at_ip; 304 305 /** Number of uniform variable components visited. */ 306 unsigned uniforms; 307 308 /** Byte-offset for the next available spot in the scratch space buffer. */ 309 unsigned last_scratch; 310 311 /** 312 * Array mapping UNIFORM register numbers to the pull parameter index, 313 * or -1 if this uniform register isn't being uploaded as a pull constant. 314 */ 315 int *pull_constant_loc; 316 317 /** 318 * Array mapping UNIFORM register numbers to the push parameter index, 319 * or -1 if this uniform register isn't being uploaded as a push constant. 320 */ 321 int *push_constant_loc; 322 323 fs_reg subgroup_id; 324 fs_reg frag_depth; 325 fs_reg frag_stencil; 326 fs_reg sample_mask; 327 fs_reg outputs[VARYING_SLOT_MAX]; 328 fs_reg dual_src_output; 329 int first_non_payload_grf; 330 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */ 331 unsigned max_grf; 332 333 fs_reg *nir_locals; 334 fs_reg *nir_ssa_values; 335 fs_reg *nir_system_values; 336 337 bool failed; 338 char *fail_msg; 339 340 /** Register numbers for thread payload fields. */ 341 struct thread_payload { 342 uint8_t subspan_coord_reg[2]; 343 uint8_t source_depth_reg[2]; 344 uint8_t source_w_reg[2]; 345 uint8_t aa_dest_stencil_reg[2]; 346 uint8_t dest_depth_reg[2]; 347 uint8_t sample_pos_reg[2]; 348 uint8_t sample_mask_in_reg[2]; 349 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2]; 350 uint8_t local_invocation_id_reg[2]; 351 352 /** The number of thread payload registers the hardware will supply. */ 353 uint8_t num_regs; 354 } payload; 355 356 bool source_depth_to_render_target; 357 bool runtime_check_aads_emit; 358 359 fs_reg pixel_x; 360 fs_reg pixel_y; 361 fs_reg wpos_w; 362 fs_reg pixel_w; 363 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT]; 364 fs_reg shader_start_time; 365 fs_reg userplane[MAX_CLIP_PLANES]; 366 fs_reg final_gs_vertex_count; 367 fs_reg control_data_bits; 368 fs_reg invocation_id; 369 370 unsigned grf_used; 371 bool spilled_any_registers; 372 373 const unsigned dispatch_width; /**< 8, 16 or 32 */ 374 unsigned max_dispatch_width; 375 376 int shader_time_index; 377 378 unsigned promoted_constants; 379 brw::fs_builder bld; 380}; 381 382/** 383 * The fragment shader code generator. 384 * 385 * Translates FS IR to actual i965 assembly code. 386 */ 387class fs_generator 388{ 389public: 390 fs_generator(const struct brw_compiler *compiler, void *log_data, 391 void *mem_ctx, 392 struct brw_stage_prog_data *prog_data, 393 unsigned promoted_constants, 394 bool runtime_check_aads_emit, 395 gl_shader_stage stage); 396 ~fs_generator(); 397 398 void enable_debug(const char *shader_name); 399 int generate_code(const cfg_t *cfg, int dispatch_width); 400 const unsigned *get_assembly(); 401 402private: 403 void fire_fb_write(fs_inst *inst, 404 struct brw_reg payload, 405 struct brw_reg implied_header, 406 GLuint nr); 407 void generate_fb_write(fs_inst *inst, struct brw_reg payload); 408 void generate_fb_read(fs_inst *inst, struct brw_reg dst, 409 struct brw_reg payload); 410 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload); 411 void generate_urb_write(fs_inst *inst, struct brw_reg payload); 412 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload); 413 void generate_barrier(fs_inst *inst, struct brw_reg src); 414 bool generate_linterp(fs_inst *inst, struct brw_reg dst, 415 struct brw_reg *src); 416 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src, 417 struct brw_reg surface_index, 418 struct brw_reg sampler_index); 419 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst, 420 struct brw_reg src, 421 struct brw_reg surf_index); 422 void generate_ddx(const fs_inst *inst, 423 struct brw_reg dst, struct brw_reg src); 424 void generate_ddy(const fs_inst *inst, 425 struct brw_reg dst, struct brw_reg src); 426 void generate_scratch_write(fs_inst *inst, struct brw_reg src); 427 void generate_scratch_read(fs_inst *inst, struct brw_reg dst); 428 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst); 429 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst, 430 struct brw_reg index, 431 struct brw_reg offset); 432 void generate_uniform_pull_constant_load_gen7(fs_inst *inst, 433 struct brw_reg dst, 434 struct brw_reg surf_index, 435 struct brw_reg payload); 436 void generate_varying_pull_constant_load_gen4(fs_inst *inst, 437 struct brw_reg dst, 438 struct brw_reg index); 439 void generate_varying_pull_constant_load_gen7(fs_inst *inst, 440 struct brw_reg dst, 441 struct brw_reg index, 442 struct brw_reg offset); 443 void generate_mov_dispatch_to_flags(fs_inst *inst); 444 445 void generate_pixel_interpolator_query(fs_inst *inst, 446 struct brw_reg dst, 447 struct brw_reg src, 448 struct brw_reg msg_data, 449 unsigned msg_type); 450 451 void generate_set_sample_id(fs_inst *inst, 452 struct brw_reg dst, 453 struct brw_reg src0, 454 struct brw_reg src1); 455 456 void generate_discard_jump(fs_inst *inst); 457 458 void generate_pack_half_2x16_split(fs_inst *inst, 459 struct brw_reg dst, 460 struct brw_reg x, 461 struct brw_reg y); 462 void generate_unpack_half_2x16_split(fs_inst *inst, 463 struct brw_reg dst, 464 struct brw_reg src); 465 466 void generate_shader_time_add(fs_inst *inst, 467 struct brw_reg payload, 468 struct brw_reg offset, 469 struct brw_reg value); 470 471 void generate_mov_indirect(fs_inst *inst, 472 struct brw_reg dst, 473 struct brw_reg reg, 474 struct brw_reg indirect_byte_offset); 475 476 void generate_shuffle(fs_inst *inst, 477 struct brw_reg dst, 478 struct brw_reg src, 479 struct brw_reg idx); 480 481 void generate_quad_swizzle(const fs_inst *inst, 482 struct brw_reg dst, struct brw_reg src, 483 unsigned swiz); 484 485 bool patch_discard_jumps_to_fb_writes(); 486 487 const struct brw_compiler *compiler; 488 void *log_data; /* Passed to compiler->*_log functions */ 489 490 const struct gen_device_info *devinfo; 491 492 struct brw_codegen *p; 493 struct brw_stage_prog_data * const prog_data; 494 495 unsigned dispatch_width; /**< 8, 16 or 32 */ 496 497 exec_list discard_halt_patches; 498 unsigned promoted_constants; 499 bool runtime_check_aads_emit; 500 bool debug_flag; 501 const char *shader_name; 502 gl_shader_stage stage; 503 void *mem_ctx; 504}; 505 506namespace brw { 507 inline fs_reg 508 fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2], 509 brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1) 510 { 511 if (!regs[0]) 512 return fs_reg(); 513 514 if (bld.dispatch_width() > 16) { 515 const fs_reg tmp = bld.vgrf(type, n); 516 const brw::fs_builder hbld = bld.exec_all().group(16, 0); 517 const unsigned m = bld.dispatch_width() / hbld.dispatch_width(); 518 fs_reg *const components = new fs_reg[n * m]; 519 520 for (unsigned c = 0; c < n; c++) { 521 for (unsigned g = 0; g < m; g++) { 522 components[c * m + g] = 523 offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c); 524 } 525 } 526 527 hbld.LOAD_PAYLOAD(tmp, components, n * m, 0); 528 529 delete[] components; 530 return tmp; 531 532 } else { 533 return fs_reg(retype(brw_vec8_grf(regs[0], 0), type)); 534 } 535 } 536 537 /** 538 * Remove any modifiers from the \p i-th source region of the instruction, 539 * including negate, abs and any implicit type conversion to the execution 540 * type. Instead any source modifiers will be implemented as a separate 541 * MOV instruction prior to the original instruction. 542 */ 543 inline bool 544 lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i) 545 { 546 assert(inst->components_read(i) == 1); 547 const fs_builder ibld(v, block, inst); 548 const fs_reg tmp = ibld.vgrf(get_exec_type(inst)); 549 550 ibld.MOV(tmp, inst->src[i]); 551 inst->src[i] = tmp; 552 553 return true; 554 } 555} 556 557void shuffle_from_32bit_read(const brw::fs_builder &bld, 558 const fs_reg &dst, 559 const fs_reg &src, 560 uint32_t first_component, 561 uint32_t components); 562 563fs_reg shuffle_for_32bit_write(const brw::fs_builder &bld, 564 const fs_reg &src, 565 uint32_t first_component, 566 uint32_t components); 567 568fs_reg setup_imm_df(const brw::fs_builder &bld, 569 double v); 570 571fs_reg setup_imm_b(const brw::fs_builder &bld, 572 int8_t v); 573 574fs_reg setup_imm_ub(const brw::fs_builder &bld, 575 uint8_t v); 576 577enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode, 578 nir_intrinsic_op op); 579 580#endif /* BRW_FS_H */ 581