1/* 2 * Copyright 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <stdint.h> 25 26#define __gen_address_type uint64_t 27#define __gen_user_data void 28 29static uint64_t 30__gen_combine_address(__attribute__((unused)) void *data, 31 __attribute__((unused)) void *loc, uint64_t addr, 32 uint32_t delta) 33{ 34 return addr + delta; 35} 36 37#include "genxml/gen_macros.h" 38#include "genxml/genX_pack.h" 39 40#include "isl_priv.h" 41 42#if GFX_VER >= 7 43static const uint8_t isl_encode_halign(uint8_t halign) 44{ 45 switch (halign) { 46#if GFX_VERx10 >= 125 47 case 16: return HALIGN_16; 48 case 32: return HALIGN_32; 49 case 64: return HALIGN_64; 50 case 128: return HALIGN_128; 51#elif GFX_VER >= 8 52 case 4: return HALIGN_4; 53 case 8: return HALIGN_8; 54 case 16: return HALIGN_16; 55#else 56 case 4: return HALIGN_4; 57 case 8: return HALIGN_8; 58#endif 59 default: unreachable("Invalid halign"); 60 } 61} 62#endif 63 64#if GFX_VER >= 6 65static const uint8_t isl_encode_valign(uint8_t valign) 66{ 67 switch (valign) { 68#if GFX_VER >= 8 69 case 4: return VALIGN_4; 70 case 8: return VALIGN_8; 71 case 16: return VALIGN_16; 72#else 73 case 2: return VALIGN_2; 74 case 4: return VALIGN_4; 75#endif 76 default: unreachable("Invalid valign"); 77 } 78} 79#endif 80 81#if GFX_VER >= 8 82static const uint8_t isl_encode_tiling[] = { 83 [ISL_TILING_LINEAR] = LINEAR, 84 [ISL_TILING_X] = XMAJOR, 85#if GFX_VERx10 >= 125 86 [ISL_TILING_4] = TILE4, 87 [ISL_TILING_64] = TILE64, 88#else 89 [ISL_TILING_Y0] = YMAJOR, 90 [ISL_TILING_Yf] = YMAJOR, 91 [ISL_TILING_Ys] = YMAJOR, 92#endif 93#if GFX_VER <= 11 94 [ISL_TILING_W] = WMAJOR, 95#endif 96}; 97#endif 98 99#if GFX_VER >= 7 100static const uint32_t isl_encode_multisample_layout[] = { 101 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS, 102 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL, 103 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS, 104}; 105#endif 106 107#if GFX_VER >= 12 108static const uint32_t isl_encode_aux_mode[] = { 109 [ISL_AUX_USAGE_NONE] = AUX_NONE, 110 [ISL_AUX_USAGE_MC] = AUX_NONE, 111 [ISL_AUX_USAGE_MCS] = AUX_CCS_E, 112 [ISL_AUX_USAGE_GFX12_CCS_E] = AUX_CCS_E, 113 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, 114 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E, 115 [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE, 116 [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E, 117}; 118#elif GFX_VER >= 9 119static const uint32_t isl_encode_aux_mode[] = { 120 [ISL_AUX_USAGE_NONE] = AUX_NONE, 121 [ISL_AUX_USAGE_HIZ] = AUX_HIZ, 122 [ISL_AUX_USAGE_MCS] = AUX_CCS_D, 123 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D, 124 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, 125}; 126#elif GFX_VER >= 8 127static const uint32_t isl_encode_aux_mode[] = { 128 [ISL_AUX_USAGE_NONE] = AUX_NONE, 129 [ISL_AUX_USAGE_HIZ] = AUX_HIZ, 130 [ISL_AUX_USAGE_MCS] = AUX_MCS, 131 [ISL_AUX_USAGE_CCS_D] = AUX_MCS, 132}; 133#endif 134 135static uint8_t 136get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) 137{ 138 switch (dim) { 139 default: 140 unreachable("bad isl_surf_dim"); 141 case ISL_SURF_DIM_1D: 142 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); 143 return SURFTYPE_1D; 144 case ISL_SURF_DIM_2D: 145 if ((usage & ISL_SURF_USAGE_CUBE_BIT) && 146 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) { 147 /* We need SURFTYPE_CUBE to make cube sampling work */ 148 return SURFTYPE_CUBE; 149 } else { 150 /* Everything else (render and storage) treat cubes as plain 151 * 2D array textures 152 */ 153 return SURFTYPE_2D; 154 } 155 case ISL_SURF_DIM_3D: 156 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT)); 157 return SURFTYPE_3D; 158 } 159} 160 161/** 162 * Get the horizontal and vertical alignment in the units expected by the 163 * hardware. Note that this does NOT give you the actual hardware enum values 164 * but an index into the isl_encode_[hv]align arrays above. 165 */ 166UNUSED static struct isl_extent3d 167get_image_alignment(const struct isl_surf *surf) 168{ 169 if (GFX_VERx10 >= 125) { 170 if (surf->tiling == ISL_TILING_64) { 171 /* The hardware ignores the alignment values. Anyway, the surface's 172 * true alignment is likely outside the enum range of HALIGN* and 173 * VALIGN*. 174 */ 175 return isl_extent3d(128, 4, 1); 176 } else if (isl_format_get_layout(surf->format)->bpb % 3 == 0) { 177 /* On XeHP, RENDER_SURFACE_STATE.SurfaceHorizontalAlignment is in 178 * units of elements for 24, 48, and 96 bpb formats. 179 */ 180 return isl_surf_get_image_alignment_el(surf); 181 } else { 182 /* On XeHP, RENDER_SURFACE_STATE.SurfaceHorizontalAlignment is in 183 * units of bytes for formats that are powers of two. 184 */ 185 const uint32_t bs = isl_format_get_layout(surf->format)->bpb / 8; 186 return isl_extent3d(surf->image_alignment_el.w * bs, 187 surf->image_alignment_el.h, 188 surf->image_alignment_el.d); 189 } 190 } else if (GFX_VER >= 9) { 191 if (isl_tiling_is_std_y(surf->tiling) || 192 surf->dim_layout == ISL_DIM_LAYOUT_GFX9_1D) { 193 /* The hardware ignores the alignment values. Anyway, the surface's 194 * true alignment is likely outside the enum range of HALIGN* and 195 * VALIGN*. 196 */ 197 return isl_extent3d(4, 4, 1); 198 } else { 199 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units 200 * of surface elements (not pixels nor samples). For compressed formats, 201 * a "surface element" is defined as a compression block. For example, 202 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2 203 * format (ETC2 has a block height of 4), then the vertical alignment is 204 * 4 compression blocks or, equivalently, 16 pixels. 205 */ 206 return isl_surf_get_image_alignment_el(surf); 207 } 208 } else { 209 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in 210 * units of surface samples. For example, if SurfaceVerticalAlignment 211 * is VALIGN_4 and the surface is singlesampled, then for any surface 212 * format (compressed or not) the vertical alignment is 213 * 4 pixels. 214 */ 215 return isl_surf_get_image_alignment_sa(surf); 216 } 217} 218 219#if GFX_VER >= 8 220static uint32_t 221get_qpitch(const struct isl_surf *surf) 222{ 223 switch (surf->dim_layout) { 224 default: 225 unreachable("Bad isl_surf_dim"); 226 case ISL_DIM_LAYOUT_GFX4_2D: 227 if (GFX_VER >= 9) { 228 if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) { 229 /* This is rather annoying and completely undocumented. It 230 * appears that the hardware has a bug (or undocumented feature) 231 * regarding stencil buffers most likely related to the way 232 * W-tiling is handled as modified Y-tiling. If you bind a 3-D 233 * stencil buffer normally, and use texelFetch on it, the z or 234 * array index will get implicitly multiplied by 2 for no obvious 235 * reason. The fix appears to be to divide qpitch by 2 for 236 * W-tiled surfaces. 237 */ 238 return isl_surf_get_array_pitch_el_rows(surf) / 2; 239 } else { 240 return isl_surf_get_array_pitch_el_rows(surf); 241 } 242 } else { 243 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch 244 * 245 * "This field must be set to an integer multiple of the Surface 246 * Vertical Alignment. For compressed textures (BC*, FXT1, 247 * ETC*, and EAC* Surface Formats), this field is in units of 248 * rows in the uncompressed surface, and must be set to an 249 * integer multiple of the vertical alignment parameter "j" 250 * defined in the Common Surface Formats section." 251 */ 252 return isl_surf_get_array_pitch_sa_rows(surf); 253 } 254 case ISL_DIM_LAYOUT_GFX9_1D: 255 /* QPitch is usually expressed as rows of surface elements (where 256 * a surface element is an compression block or a single surface 257 * sample). Skylake 1D is an outlier. 258 * 259 * From the Skylake BSpec >> Memory Views >> Common Surface 260 * Formats >> Surface Layout and Tiling >> 1D Surfaces: 261 * 262 * Surface QPitch specifies the distance in pixels between array 263 * slices. 264 */ 265 return isl_surf_get_array_pitch_el(surf); 266 case ISL_DIM_LAYOUT_GFX4_3D: 267 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GFX4_3D since it uses a 268 * different pitch at each LOD. Also, the QPitch field is ignored for 269 * these surfaces. From the Broadwell PRM documentation for QPitch: 270 * 271 * This field specifies the distance in rows between array slices. It 272 * is used only in the following cases: 273 * - Surface Array is enabled OR 274 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled 275 * Surface Storage Format set to MSFMT_MSS OR 276 * - Surface Type is SURFTYPE_CUBE 277 * 278 * None of the three conditions above can possibly apply to a 3D surface 279 * so it is safe to just set QPitch to 0. 280 */ 281 return 0; 282 } 283} 284#endif /* GFX_VER >= 8 */ 285 286void 287isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, 288 const struct isl_surf_fill_state_info *restrict info) 289{ 290 struct GENX(RENDER_SURFACE_STATE) s = { 0 }; 291 292 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage); 293 294 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) 295 assert(isl_format_supports_rendering(dev->info, info->view->format)); 296 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) 297 assert(isl_format_supports_sampling(dev->info, info->view->format)); 298 299 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat 300 * 301 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*) 302 * format if the Surface Type is SURFTYPE_1D 303 */ 304 if (info->surf->dim == ISL_SURF_DIM_1D) 305 assert(!isl_format_is_compressed(info->view->format)); 306 307 if (isl_format_is_compressed(info->surf->format)) { 308 /* You're not allowed to make a view of a compressed format with any 309 * format other than the surface format. None of the userspace APIs 310 * allow for this directly and doing so would mess up a number of 311 * surface parameters such as Width, Height, and alignments. Ideally, 312 * we'd like to assert that the two formats match. However, we have an 313 * S3TC workaround that requires us to do reinterpretation. So assert 314 * that they're at least the same bpb and block size. 315 */ 316 ASSERTED const struct isl_format_layout *surf_fmtl = 317 isl_format_get_layout(info->surf->format); 318 ASSERTED const struct isl_format_layout *view_fmtl = 319 isl_format_get_layout(info->surf->format); 320 assert(surf_fmtl->bpb == view_fmtl->bpb); 321 assert(surf_fmtl->bw == view_fmtl->bw); 322 assert(surf_fmtl->bh == view_fmtl->bh); 323 } 324 325 s.SurfaceFormat = info->view->format; 326 327#if GFX_VER >= 12 328 /* The BSpec description of this field says: 329 * 330 * "This bit field, when set, indicates if the resource is created as 331 * Depth/Stencil resource." 332 * 333 * "SW must set this bit for any resource that was created with 334 * Depth/Stencil resource flag. Setting this bit allows HW to properly 335 * interpret the data-layout for various cases. For any resource that's 336 * created without Depth/Stencil resource flag, it must be reset." 337 * 338 * Even though the docs for this bit seem to imply that it's required for 339 * anything which might have been used for depth/stencil, empirical 340 * evidence suggests that it only affects CCS compression usage. There are 341 * a few things which back this up: 342 * 343 * 1. The docs are also pretty clear that this bit was added as part 344 * of enabling Gfx12 depth/stencil lossless compression. 345 * 346 * 2. The only new difference between depth/stencil and color images on 347 * Gfx12 (where the bit was added) is how they treat CCS compression. 348 * All other differences such as alignment requirements and MSAA layout 349 * are already covered by other bits. 350 * 351 * Under these assumptions, it makes sense for ISL to model this bit as 352 * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT 353 * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource 354 * == true. 355 */ 356 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || 357 info->aux_usage == ISL_AUX_USAGE_STC_CCS; 358#endif 359 360#if GFX_VER <= 5 361 s.ColorBufferComponentWriteDisables = info->write_disables; 362 s.ColorBlendEnable = info->blend_enable; 363#else 364 assert(info->write_disables == 0); 365#endif 366 367#if GFX_VERx10 == 75 368 s.IntegerSurfaceFormat = 369 isl_format_has_int_channel((enum isl_format) s.SurfaceFormat); 370#endif 371 372 assert(info->surf->logical_level0_px.width > 0 && 373 info->surf->logical_level0_px.height > 0); 374 375 s.Width = info->surf->logical_level0_px.width - 1; 376 s.Height = info->surf->logical_level0_px.height - 1; 377 378 /* In the gfx6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 379 * (Surface Arrays For all surfaces other than separate stencil buffer): 380 * 381 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value 382 * calculated in the equation above , for every other odd Surface Height 383 * starting from 1 i.e. 1,5,9,13" 384 * 385 * Since this Qpitch errata only impacts the sampler, we have to adjust the 386 * input for the rendering surface to achieve the same qpitch. For the 387 * affected heights, we increment the height by 1 for the rendering 388 * surface. 389 */ 390 if (GFX_VER == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && 391 info->surf->samples > 1 && 392 (info->surf->logical_level0_px.height % 4) == 1) 393 s.Height++; 394 395 switch (s.SurfaceType) { 396 case SURFTYPE_1D: 397 case SURFTYPE_2D: 398 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement: 399 * 400 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field 401 * must be set to zero if this surface is used with sampling engine 402 * messages." 403 * 404 * This restriction appears to exist only on Ivy Bridge. 405 */ 406 if (GFX_VERx10 == 70 && !ISL_DEV_IS_BAYTRAIL(dev) && 407 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) && 408 info->surf->samples > 1) 409 assert(info->view->base_array_layer == 0); 410 411 s.MinimumArrayElement = info->view->base_array_layer; 412 413 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: 414 * 415 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced 416 * by one for each increase from zero of Minimum Array Element. For 417 * example, if Minimum Array Element is set to 1024 on a 2D surface, 418 * the range of this field is reduced to [0,1023]. 419 * 420 * In other words, 'Depth' is the number of array layers. 421 */ 422 s.Depth = info->view->array_len - 1; 423 424 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent: 425 * 426 * For Render Target and Typed Dataport 1D and 2D Surfaces: 427 * This field must be set to the same value as the Depth field. 428 */ 429 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | 430 ISL_SURF_USAGE_STORAGE_BIT)) 431 s.RenderTargetViewExtent = s.Depth; 432 break; 433 case SURFTYPE_CUBE: 434 s.MinimumArrayElement = info->view->base_array_layer; 435 /* Same as SURFTYPE_2D, but divided by 6 */ 436 s.Depth = info->view->array_len / 6 - 1; 437 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | 438 ISL_SURF_USAGE_STORAGE_BIT)) 439 s.RenderTargetViewExtent = s.Depth; 440 break; 441 case SURFTYPE_3D: 442 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth: 443 * 444 * If the volume texture is MIP-mapped, this field specifies the 445 * depth of the base MIP level. 446 */ 447 s.Depth = info->surf->logical_level0_px.depth - 1; 448 449 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent: 450 * 451 * For Render Target and Typed Dataport 3D Surfaces: This field 452 * indicates the extent of the accessible 'R' coordinates minus 1 on 453 * the LOD currently being rendered to. 454 * 455 * The docs specify that this only matters for render targets and 456 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the 457 * Depth field has more bits than RenderTargetViewExtent so we can have 458 * textures with more levels than we can render to. In order to prevent 459 * assert-failures in the packing function below, we only set the field 460 * when it's actually going to be used by the hardware. 461 * 462 * Similaraly, the MinimumArrayElement field is ignored by all hardware 463 * prior to Sky Lake when texturing and we want it set to 0 anyway. 464 * Since it's already initialized to 0, we can just leave it alone for 465 * texture surfaces. 466 */ 467 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT | 468 ISL_SURF_USAGE_STORAGE_BIT)) { 469 s.MinimumArrayElement = info->view->base_array_layer; 470 s.RenderTargetViewExtent = info->view->array_len - 1; 471 } 472 break; 473 default: 474 unreachable("bad SurfaceType"); 475 } 476 477#if GFX_VER >= 12 478 /* Wa_1806565034: Only set SurfaceArray if arrayed surface is > 1. */ 479 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D && 480 info->view->array_len > 1; 481#elif GFX_VER >= 7 482 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D; 483#endif 484 485 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { 486 /* For render target surfaces, the hardware interprets field 487 * MIPCount/LOD as LOD. The Broadwell PRM says: 488 * 489 * MIPCountLOD defines the LOD that will be rendered into. 490 * SurfaceMinLOD is ignored. 491 */ 492 s.MIPCountLOD = info->view->base_level; 493 s.SurfaceMinLOD = 0; 494 } else { 495 /* For non render target surfaces, the hardware interprets field 496 * MIPCount/LOD as MIPCount. The range of levels accessible by the 497 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD]. 498 */ 499 s.SurfaceMinLOD = info->view->base_level; 500 s.MIPCountLOD = MAX(info->view->levels, 1) - 1; 501 } 502 503#if GFX_VER >= 9 504 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail 505 * Start LOD" to 15 to prevent the hardware from trying to use them. 506 */ 507 s.TiledResourceMode = NONE; 508 s.MipTailStartLOD = 15; 509#endif 510 511#if GFX_VER >= 6 512 const struct isl_extent3d image_align = get_image_alignment(info->surf); 513 s.SurfaceVerticalAlignment = isl_encode_valign(image_align.height); 514#if GFX_VER >= 7 515 s.SurfaceHorizontalAlignment = isl_encode_halign(image_align.width); 516#endif 517#endif 518 519 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GFX9_1D) { 520 /* For gfx9 1-D textures, surface pitch is ignored */ 521 s.SurfacePitch = 0; 522 } else { 523 s.SurfacePitch = info->surf->row_pitch_B - 1; 524 } 525 526#if GFX_VER >= 8 527 s.SurfaceQPitch = get_qpitch(info->surf) >> 2; 528#elif GFX_VER == 7 529 s.SurfaceArraySpacing = info->surf->array_pitch_span == 530 ISL_ARRAY_PITCH_SPAN_COMPACT; 531#endif 532 533#if GFX_VER >= 8 534 assert(GFX_VER < 12 || info->surf->tiling != ISL_TILING_W); 535 s.TileMode = isl_encode_tiling[info->surf->tiling]; 536#else 537 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, 538 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : 539 TILEWALK_XMAJOR, 540#endif 541 542#if GFX_VER >= 8 543 s.RenderCacheReadWriteMode = WriteOnlyCache; 544#else 545 s.RenderCacheReadWriteMode = 0; 546#endif 547 548#if GFX_VER >= 11 549 /* We've seen dEQP failures when enabling this bit with UINT formats, 550 * which particularly affects blorp_copy() operations. It shouldn't 551 * have any effect on UINT textures anyway, so disable it for them. 552 */ 553 s.EnableUnormPathInColorPipe = 554 !isl_format_has_int_channel(info->view->format); 555#endif 556 557 s.CubeFaceEnablePositiveZ = 1; 558 s.CubeFaceEnableNegativeZ = 1; 559 s.CubeFaceEnablePositiveY = 1; 560 s.CubeFaceEnableNegativeY = 1; 561 s.CubeFaceEnablePositiveX = 1; 562 s.CubeFaceEnableNegativeX = 1; 563 564#if GFX_VER >= 6 565 s.NumberofMultisamples = ffs(info->surf->samples) - 1; 566#if GFX_VER >= 7 567 s.MultisampledSurfaceStorageFormat = 568 isl_encode_multisample_layout[info->surf->msaa_layout]; 569#endif 570#endif 571 572#if (GFX_VERx10 >= 75) 573 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) 574 assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle)); 575 576 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r; 577 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g; 578 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b; 579 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a; 580#else 581 assert(isl_swizzle_is_identity(info->view->swizzle)); 582#endif 583 584 s.SurfaceBaseAddress = info->address; 585 586#if GFX_VER >= 6 587 s.MOCS = info->mocs; 588#endif 589 590#if GFX_VERx10 >= 45 591 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) { 592 /* There are fairly strict rules about when the offsets can be used. 593 * These are mostly taken from the Sky Lake PRM documentation for 594 * RENDER_SURFACE_STATE. 595 */ 596 assert(info->surf->tiling != ISL_TILING_LINEAR); 597 assert(info->surf->dim == ISL_SURF_DIM_2D); 598 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb)); 599 assert(info->surf->levels == 1); 600 assert(info->surf->logical_level0_px.array_len == 1); 601 assert(info->aux_usage == ISL_AUX_USAGE_NONE); 602 603 if (GFX_VER >= 8) { 604 /* Broadwell added more rules. */ 605 assert(info->surf->samples == 1); 606 if (isl_format_get_layout(info->view->format)->bpb == 8) 607 assert(info->x_offset_sa % 16 == 0); 608 if (isl_format_get_layout(info->view->format)->bpb == 16) 609 assert(info->x_offset_sa % 8 == 0); 610 } 611 612#if GFX_VER >= 7 613 s.SurfaceArray = false; 614#endif 615 } 616 617 const unsigned x_div = 4; 618 const unsigned y_div = GFX_VER >= 8 ? 4 : 2; 619 assert(info->x_offset_sa % x_div == 0); 620 assert(info->y_offset_sa % y_div == 0); 621 s.XOffset = info->x_offset_sa / x_div; 622 s.YOffset = info->y_offset_sa / y_div; 623#else 624 assert(info->x_offset_sa == 0); 625 assert(info->y_offset_sa == 0); 626#endif 627 628#if GFX_VER >= 7 629 if (info->aux_usage != ISL_AUX_USAGE_NONE) { 630 /* Check valid aux usages per-gen */ 631 if (GFX_VER >= 12) { 632 assert(info->aux_usage == ISL_AUX_USAGE_MCS || 633 info->aux_usage == ISL_AUX_USAGE_CCS_E || 634 info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E || 635 info->aux_usage == ISL_AUX_USAGE_MC || 636 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || 637 info->aux_usage == ISL_AUX_USAGE_MCS_CCS || 638 info->aux_usage == ISL_AUX_USAGE_STC_CCS); 639 } else if (GFX_VER >= 9) { 640 assert(info->aux_usage == ISL_AUX_USAGE_HIZ || 641 info->aux_usage == ISL_AUX_USAGE_MCS || 642 info->aux_usage == ISL_AUX_USAGE_CCS_D || 643 info->aux_usage == ISL_AUX_USAGE_CCS_E); 644 } else if (GFX_VER >= 8) { 645 assert(info->aux_usage == ISL_AUX_USAGE_HIZ || 646 info->aux_usage == ISL_AUX_USAGE_MCS || 647 info->aux_usage == ISL_AUX_USAGE_CCS_D); 648 } else if (GFX_VER >= 7) { 649 assert(info->aux_usage == ISL_AUX_USAGE_MCS || 650 info->aux_usage == ISL_AUX_USAGE_CCS_D); 651 } 652 653 /* The docs don't appear to say anything whatsoever about compression 654 * and the data port. Testing seems to indicate that the data port 655 * completely ignores the AuxiliarySurfaceMode field. 656 * 657 * On gfx12 HDC supports compression. 658 */ 659 if (GFX_VER < 12) 660 assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); 661 662 if (isl_surf_usage_is_depth(info->surf->usage)) 663 assert(isl_aux_usage_has_hiz(info->aux_usage)); 664 665 if (isl_surf_usage_is_stencil(info->surf->usage)) 666 assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS); 667 668 if (isl_aux_usage_has_hiz(info->aux_usage)) { 669 /* For Gfx8-10, there are some restrictions around sampling from HiZ. 670 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode 671 * say: 672 * 673 * "If this field is set to AUX_HIZ, Number of Multisamples must 674 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D." 675 * 676 * On Gfx12, the docs are a bit less obvious but the restriction is 677 * the same. The limitation isn't called out explicitly but the docs 678 * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode 679 * say: 680 * 681 * "If Number of multisamples > 1, programming this value means 682 * MSAA compression is enabled for that surface. Auxillary surface 683 * is MSC with tile y." 684 * 685 * Since this interpretation ignores whether the surface is 686 * depth/stencil or not and since multisampled depth buffers use 687 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS 688 * compression, this means that we can't even specify MSAA depth CCS 689 * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode. 690 */ 691 assert(info->surf->samples == 1); 692 693 /* The dimension must not be 3D */ 694 assert(info->surf->dim != ISL_SURF_DIM_3D); 695 696 /* The format must be one of the following: */ 697 switch (info->view->format) { 698 case ISL_FORMAT_R32_FLOAT: 699 case ISL_FORMAT_R24_UNORM_X8_TYPELESS: 700 case ISL_FORMAT_R16_UNORM: 701 break; 702 default: 703 assert(!"Incompatible HiZ Sampling format"); 704 break; 705 } 706 } 707 708#if GFX_VERx10 >= 125 709 s.RenderCompressionFormat = 710 isl_get_render_compression_format(info->surf->format); 711#endif 712#if GFX_VER >= 12 713 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC; 714#endif 715#if GFX_VER >= 8 716 s.AuxiliarySurfaceMode = isl_encode_aux_mode[info->aux_usage]; 717#else 718 s.MCSEnable = true; 719#endif 720 } 721 722 /* The auxiliary buffer info is filled when it's useable by the HW. 723 * 724 * Starting with Gfx12, the only form of compression that can be used 725 * with RENDER_SURFACE_STATE which requires an aux surface is MCS. 726 * HiZ still requires a surface but the HiZ surface can only be 727 * accessed through 3DSTATE_HIER_DEPTH_BUFFER. 728 * 729 * On all earlier hardware, an aux surface is required for all forms 730 * of compression. 731 */ 732 if ((GFX_VER < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) || 733 (GFX_VER >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) { 734 735 assert(info->aux_surf != NULL); 736 737 struct isl_tile_info tile_info; 738 isl_surf_get_tile_info(info->aux_surf, &tile_info); 739 uint32_t pitch_in_tiles = 740 info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width; 741 742 s.AuxiliarySurfaceBaseAddress = info->aux_address; 743 s.AuxiliarySurfacePitch = pitch_in_tiles - 1; 744 745#if GFX_VER >= 8 746 /* Auxiliary surfaces in ISL have compressed formats but the hardware 747 * doesn't expect our definition of the compression, it expects qpitch 748 * in units of samples on the main surface. 749 */ 750 s.AuxiliarySurfaceQPitch = 751 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2; 752#endif 753 } 754#endif 755 756#if GFX_VER >= 8 && GFX_VER < 11 757 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 758 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): 759 * 760 * This bit must be set for the following surface types: BC2_UNORM 761 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM 762 */ 763 if (GFX_VER >= 9 || dev->info->is_cherryview) { 764 switch (info->view->format) { 765 case ISL_FORMAT_BC2_UNORM: 766 case ISL_FORMAT_BC3_UNORM: 767 case ISL_FORMAT_BC5_UNORM: 768 case ISL_FORMAT_BC5_SNORM: 769 case ISL_FORMAT_BC7_UNORM: 770 s.SamplerL2BypassModeDisable = true; 771 break; 772 default: 773 /* From the SKL PRM, Programming Note under Sampler Output Channel 774 * Mapping: 775 * 776 * If a surface has an associated HiZ Auxilliary surface, the 777 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE 778 * must be set. 779 */ 780 if (GFX_VER >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ) 781 s.SamplerL2BypassModeDisable = true; 782 break; 783 } 784 } 785#endif 786 787 if (isl_aux_usage_has_fast_clears(info->aux_usage)) { 788 if (info->use_clear_address) { 789#if GFX_VER >= 10 790 s.ClearValueAddressEnable = true; 791 s.ClearValueAddress = info->clear_address; 792#else 793 unreachable("Gfx9 and earlier do not support indirect clear colors"); 794#endif 795 } 796 797#if GFX_VER == 11 798 /* 799 * From BXML > GT > Shared Functions > vol5c Shared Functions > 800 * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable: 801 * 802 * Project: Gfx11 803 * 804 * "Enables Pixel backend hw to convert clear values into native format 805 * and write back to clear address, so that display and sampler can use 806 * the converted value for resolving fast cleared RTs." 807 * 808 * Summary: 809 * Clear color conversion must be enabled if the clear color is stored 810 * indirectly and fast color clears are enabled. 811 */ 812 if (info->use_clear_address) { 813 s.ClearColorConversionEnable = true; 814 } 815#endif 816 817#if GFX_VER >= 12 818 assert(info->use_clear_address); 819#elif GFX_VER >= 9 820 if (!info->use_clear_address) { 821 s.RedClearColor = info->clear_color.u32[0]; 822 s.GreenClearColor = info->clear_color.u32[1]; 823 s.BlueClearColor = info->clear_color.u32[2]; 824 s.AlphaClearColor = info->clear_color.u32[3]; 825 } 826#elif GFX_VER >= 7 827 /* Prior to Sky Lake, we only have one bit for the clear color which 828 * gives us 0 or 1 in whatever the surface's format happens to be. 829 */ 830 if (isl_format_has_int_channel(info->view->format)) { 831 for (unsigned i = 0; i < 4; i++) { 832 assert(info->clear_color.u32[i] == 0 || 833 info->clear_color.u32[i] == 1); 834 } 835 s.RedClearColor = info->clear_color.u32[0] != 0; 836 s.GreenClearColor = info->clear_color.u32[1] != 0; 837 s.BlueClearColor = info->clear_color.u32[2] != 0; 838 s.AlphaClearColor = info->clear_color.u32[3] != 0; 839 } else { 840 for (unsigned i = 0; i < 4; i++) { 841 assert(info->clear_color.f32[i] == 0.0f || 842 info->clear_color.f32[i] == 1.0f); 843 } 844 s.RedClearColor = info->clear_color.f32[0] != 0.0f; 845 s.GreenClearColor = info->clear_color.f32[1] != 0.0f; 846 s.BlueClearColor = info->clear_color.f32[2] != 0.0f; 847 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f; 848 } 849#endif 850 } 851 852 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); 853} 854 855void 856isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, 857 const struct isl_buffer_fill_state_info *restrict info) 858{ 859 uint64_t buffer_size = info->size_B; 860 861 /* Uniform and Storage buffers need to have surface size not less that the 862 * aligned 32-bit size of the buffer. To calculate the array lenght on 863 * unsized arrays in StorageBuffer the last 2 bits store the padding size 864 * added to the surface, so we can calculate latter the original buffer 865 * size to know the number of elements. 866 * 867 * surface_size = isl_align(buffer_size, 4) + 868 * (isl_align(buffer_size) - buffer_size) 869 * 870 * buffer_size = (surface_size & ~3) - (surface_size & 3) 871 */ 872 if ((info->format == ISL_FORMAT_RAW || 873 info->stride_B < isl_format_get_layout(info->format)->bpb / 8) && 874 !info->is_scratch) { 875 assert(info->stride_B == 1); 876 uint64_t aligned_size = isl_align(buffer_size, 4); 877 buffer_size = aligned_size + (aligned_size - buffer_size); 878 } 879 880 uint32_t num_elements = buffer_size / info->stride_B; 881 882 assert(num_elements > 0); 883 if (info->format == ISL_FORMAT_RAW) { 884 assert(num_elements <= dev->max_buffer_size); 885 } else { 886 /* From the IVB PRM, SURFACE_STATE::Height, 887 * 888 * For typed buffer and structured buffer surfaces, the number 889 * of entries in the buffer ranges from 1 to 2^27. 890 */ 891 assert(num_elements <= (1ull << 27)); 892 } 893 894 struct GENX(RENDER_SURFACE_STATE) s = { 0, }; 895 896 s.SurfaceFormat = info->format; 897 898 s.SurfaceType = SURFTYPE_BUFFER; 899#if GFX_VERx10 >= 125 900 if (info->is_scratch) { 901 /* From the BSpec: 902 * 903 * "For surfaces of type SURFTYPE_SCRATCH, valid range of pitch is: 904 * [63,262143] -> [64B, 256KB]. Also, for SURFTYPE_SCRATCH, the 905 * pitch must be a multiple of 64bytes." 906 */ 907 assert(info->format == ISL_FORMAT_RAW); 908 assert(info->stride_B % 64 == 0); 909 assert(info->stride_B <= 256 * 1024); 910 s.SurfaceType = SURFTYPE_SCRATCH; 911 } 912#else 913 assert(!info->is_scratch); 914#endif 915 916 s.SurfacePitch = info->stride_B - 1; 917 918#if GFX_VER >= 6 919 s.SurfaceVerticalAlignment = isl_encode_valign(4); 920#if GFX_VERx10 >= 125 921 s.SurfaceHorizontalAlignment = isl_encode_halign(128); 922#elif GFX_VER >= 7 923 s.SurfaceHorizontalAlignment = isl_encode_halign(4); 924 s.SurfaceArray = false; 925#endif 926#endif 927 928#if GFX_VER >= 7 929 s.Height = ((num_elements - 1) >> 7) & 0x3fff; 930 s.Width = (num_elements - 1) & 0x7f; 931 s.Depth = ((num_elements - 1) >> 21) & 0x3ff; 932#else 933 s.Height = ((num_elements - 1) >> 7) & 0x1fff; 934 s.Width = (num_elements - 1) & 0x7f; 935 s.Depth = ((num_elements - 1) >> 20) & 0x7f; 936#endif 937 938 if (GFX_VER == 12 && dev->info->revision == 0) { 939 /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer 940 * textures with very close base addresses (delta < 64B) to corrupt each 941 * other. We can sort-of work around this by making small buffer 942 * textures 1D textures instead. This doesn't fix the problem for large 943 * buffer textures but the liklihood of large, overlapping, and very 944 * close buffer textures is fairly low and the point is to hack around 945 * the bug so we can run apps and tests. 946 */ 947 if (info->format != ISL_FORMAT_RAW && 948 info->stride_B == isl_format_get_layout(info->format)->bpb / 8 && 949 num_elements <= (1 << 14)) { 950 s.SurfaceType = SURFTYPE_1D; 951 s.Width = num_elements - 1; 952 s.Height = 0; 953 s.Depth = 0; 954 } 955 } 956 957#if GFX_VER >= 6 958 s.NumberofMultisamples = MULTISAMPLECOUNT_1; 959#endif 960 961#if (GFX_VER >= 8) 962 s.TileMode = LINEAR; 963#else 964 s.TiledSurface = false; 965#endif 966 967#if (GFX_VER >= 8) 968 s.RenderCacheReadWriteMode = WriteOnlyCache; 969#else 970 s.RenderCacheReadWriteMode = 0; 971#endif 972 973 s.SurfaceBaseAddress = info->address; 974#if GFX_VER >= 6 975 s.MOCS = info->mocs; 976#endif 977 978#if (GFX_VERx10 >= 75) 979 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r; 980 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g; 981 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b; 982 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a; 983#endif 984 985 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); 986} 987 988void 989isl_genX(null_fill_state)(void *state, 990 const struct isl_null_fill_state_info *restrict info) 991{ 992 struct GENX(RENDER_SURFACE_STATE) s = { 993 .SurfaceType = SURFTYPE_NULL, 994 /* We previously had this format set to B8G8R8A8_UNORM but ran into 995 * hangs on IVB. R32_UINT seems to work for everybody. 996 * 997 * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872 998 */ 999 .SurfaceFormat = ISL_FORMAT_R32_UINT, 1000#if GFX_VER >= 7 1001 .SurfaceArray = info->size.depth > 1, 1002#endif 1003#if GFX_VERx10 >= 125 1004 .TileMode = TILE4, 1005#elif GFX_VER >= 8 1006 .TileMode = YMAJOR, 1007#else 1008 .TiledSurface = true, 1009 .TileWalk = TILEWALK_YMAJOR, 1010#endif 1011#if GFX_VER == 7 1012 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared 1013 * Functions" 1014 * 1015 * RENDER_SURFACE_STATE::Surface Vertical Alignment 1016 * 1017 * "This field must be set to VALIGN_4 for all tiled Y Render Target 1018 * surfaces." 1019 * 1020 * Affect IVB, HSW. 1021 */ 1022 .SurfaceVerticalAlignment = VALIGN_4, 1023#endif 1024 .MIPCountLOD = info->levels, 1025 .Width = info->size.width - 1, 1026 .Height = info->size.height - 1, 1027 .Depth = info->size.depth - 1, 1028 .RenderTargetViewExtent = info->size.depth - 1, 1029#if GFX_VER <= 5 1030 .MinimumArrayElement = info->minimum_array_element, 1031 .ColorBufferComponentWriteDisables = 0xf, 1032#endif 1033 }; 1034 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s); 1035} 1036