1/**************************************************************************
2 *
3 * Copyright 2003 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29#include "main/glheader.h"
30#include "main/context.h"
31#include "main/macros.h"
32#include "main/enums.h"
33#include "main/fbobject.h"
34#include "main/dd.h"
35#include "main/state.h"
36#include "main/stencil.h"
37#include "main/viewport.h"
38#include "tnl/tnl.h"
39#include "tnl/t_context.h"
40
41#include "drivers/common/driverfuncs.h"
42
43#include "intel_fbo.h"
44#include "intel_screen.h"
45#include "intel_batchbuffer.h"
46#include "intel_buffers.h"
47
48#include "i915_context.h"
49#include "i915_reg.h"
50
51#define FILE_DEBUG_FLAG DEBUG_STATE
52
53void
54i915_update_stencil(struct gl_context * ctx)
55{
56   struct i915_context *i915 = I915_CONTEXT(ctx);
57   GLuint front_ref, front_writemask, front_mask;
58   GLenum front_func, front_fail, front_pass_z_fail, front_pass_z_pass;
59   GLuint back_ref, back_writemask, back_mask;
60   GLenum back_func, back_fail, back_pass_z_fail, back_pass_z_pass;
61   GLuint dirty = 0;
62
63   /* The 915 considers CW to be "front" for two-sided stencil, so choose
64    * appropriately.
65    */
66   /* _NEW_POLYGON | _NEW_STENCIL */
67   if (ctx->Polygon.FrontFace == GL_CW) {
68      front_ref = _mesa_get_stencil_ref(ctx, 0);
69      front_mask = ctx->Stencil.ValueMask[0];
70      front_writemask = ctx->Stencil.WriteMask[0];
71      front_func = ctx->Stencil.Function[0];
72      front_fail = ctx->Stencil.FailFunc[0];
73      front_pass_z_fail = ctx->Stencil.ZFailFunc[0];
74      front_pass_z_pass = ctx->Stencil.ZPassFunc[0];
75      back_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
76      back_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
77      back_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
78      back_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
79      back_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
80      back_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
81      back_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
82   } else {
83      front_ref = _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
84      front_mask = ctx->Stencil.ValueMask[ctx->Stencil._BackFace];
85      front_writemask = ctx->Stencil.WriteMask[ctx->Stencil._BackFace];
86      front_func = ctx->Stencil.Function[ctx->Stencil._BackFace];
87      front_fail = ctx->Stencil.FailFunc[ctx->Stencil._BackFace];
88      front_pass_z_fail = ctx->Stencil.ZFailFunc[ctx->Stencil._BackFace];
89      front_pass_z_pass = ctx->Stencil.ZPassFunc[ctx->Stencil._BackFace];
90      back_ref = _mesa_get_stencil_ref(ctx, 0);
91      back_mask = ctx->Stencil.ValueMask[0];
92      back_writemask = ctx->Stencil.WriteMask[0];
93      back_func = ctx->Stencil.Function[0];
94      back_fail = ctx->Stencil.FailFunc[0];
95      back_pass_z_fail = ctx->Stencil.ZFailFunc[0];
96      back_pass_z_pass = ctx->Stencil.ZPassFunc[0];
97   }
98#define set_ctx_bits(reg, mask, set) do{ \
99   GLuint dw = i915->state.Ctx[reg]; \
100   dw &= ~(mask); \
101   dw |= (set); \
102   dirty |= dw != i915->state.Ctx[reg]; \
103   i915->state.Ctx[reg] = dw; \
104} while(0)
105
106   /* Set front state. */
107   set_ctx_bits(I915_CTXREG_STATE4,
108                MODE4_ENABLE_STENCIL_TEST_MASK |
109                MODE4_ENABLE_STENCIL_WRITE_MASK,
110                ENABLE_STENCIL_TEST_MASK |
111                ENABLE_STENCIL_WRITE_MASK |
112                STENCIL_TEST_MASK(front_mask) |
113                STENCIL_WRITE_MASK(front_writemask));
114
115   set_ctx_bits(I915_CTXREG_LIS5,
116                S5_STENCIL_REF_MASK |
117                S5_STENCIL_TEST_FUNC_MASK |
118                S5_STENCIL_FAIL_MASK |
119                S5_STENCIL_PASS_Z_FAIL_MASK |
120                S5_STENCIL_PASS_Z_PASS_MASK,
121                (front_ref << S5_STENCIL_REF_SHIFT) |
122                (intel_translate_compare_func(front_func) << S5_STENCIL_TEST_FUNC_SHIFT) |
123                (intel_translate_stencil_op(front_fail) << S5_STENCIL_FAIL_SHIFT) |
124                (intel_translate_stencil_op(front_pass_z_fail) <<
125                 S5_STENCIL_PASS_Z_FAIL_SHIFT) |
126                (intel_translate_stencil_op(front_pass_z_pass) <<
127                 S5_STENCIL_PASS_Z_PASS_SHIFT));
128
129   /* Set back state if different from front. */
130   if (_mesa_stencil_is_two_sided(ctx)) {
131      set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
132                   BFO_STENCIL_REF_MASK |
133                   BFO_STENCIL_TEST_MASK |
134                   BFO_STENCIL_FAIL_MASK |
135                   BFO_STENCIL_PASS_Z_FAIL_MASK |
136                   BFO_STENCIL_PASS_Z_PASS_MASK,
137                   BFO_STENCIL_TWO_SIDE |
138                   (back_ref << BFO_STENCIL_REF_SHIFT) |
139                   (intel_translate_compare_func(back_func) << BFO_STENCIL_TEST_SHIFT) |
140                   (intel_translate_stencil_op(back_fail) << BFO_STENCIL_FAIL_SHIFT) |
141                   (intel_translate_stencil_op(back_pass_z_fail) <<
142                    BFO_STENCIL_PASS_Z_FAIL_SHIFT) |
143                   (intel_translate_stencil_op(back_pass_z_pass) <<
144                    BFO_STENCIL_PASS_Z_PASS_SHIFT));
145
146      set_ctx_bits(I915_CTXREG_BF_STENCIL_MASKS,
147                   BFM_STENCIL_TEST_MASK_MASK |
148                   BFM_STENCIL_WRITE_MASK_MASK,
149                   BFM_STENCIL_TEST_MASK(back_mask) |
150                   BFM_STENCIL_WRITE_MASK(back_writemask));
151   } else {
152      set_ctx_bits(I915_CTXREG_BF_STENCIL_OPS,
153                   BFO_STENCIL_TWO_SIDE, 0);
154   }
155
156#undef set_ctx_bits
157
158   if (dirty)
159      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
160}
161
162static void
163i915StencilFuncSeparate(struct gl_context * ctx, GLenum face, GLenum func, GLint ref,
164                        GLuint mask)
165{
166}
167
168static void
169i915StencilMaskSeparate(struct gl_context * ctx, GLenum face, GLuint mask)
170{
171}
172
173static void
174i915StencilOpSeparate(struct gl_context * ctx, GLenum face, GLenum fail, GLenum zfail,
175                      GLenum zpass)
176{
177}
178
179static void
180i915AlphaFunc(struct gl_context * ctx, GLenum func, GLfloat ref)
181{
182   struct i915_context *i915 = I915_CONTEXT(ctx);
183   int test = intel_translate_compare_func(func);
184   GLubyte refByte;
185   GLuint dw;
186
187   UNCLAMPED_FLOAT_TO_UBYTE(refByte, ref);
188
189   dw = i915->state.Ctx[I915_CTXREG_LIS6];
190   dw &= ~(S6_ALPHA_TEST_FUNC_MASK | S6_ALPHA_REF_MASK);
191   dw |= ((test << S6_ALPHA_TEST_FUNC_SHIFT) |
192	  (((GLuint) refByte) << S6_ALPHA_REF_SHIFT));
193   if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
194      i915->state.Ctx[I915_CTXREG_LIS6] = dw;
195      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
196   }
197}
198
199/* This function makes sure that the proper enables are
200 * set for LogicOp, Independent Alpha Blend, and Blending.
201 * It needs to be called from numerous places where we
202 * could change the LogicOp or Independent Alpha Blend without subsequent
203 * calls to glEnable.
204 */
205static void
206i915EvalLogicOpBlendState(struct gl_context * ctx)
207{
208   struct i915_context *i915 = I915_CONTEXT(ctx);
209   GLuint dw0, dw1;
210
211   dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
212   dw1 = i915->state.Ctx[I915_CTXREG_LIS6];
213
214   if (ctx->Color.ColorLogicOpEnabled) {
215      dw0 |= S5_LOGICOP_ENABLE;
216      dw1 &= ~S6_CBUF_BLEND_ENABLE;
217   }
218   else {
219      dw0 &= ~S5_LOGICOP_ENABLE;
220
221      if (ctx->Color.BlendEnabled) {
222         dw1 |= S6_CBUF_BLEND_ENABLE;
223      }
224      else {
225         dw1 &= ~S6_CBUF_BLEND_ENABLE;
226      }
227   }
228   if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
229       dw1 != i915->state.Ctx[I915_CTXREG_LIS6]) {
230      i915->state.Ctx[I915_CTXREG_LIS5] = dw0;
231      i915->state.Ctx[I915_CTXREG_LIS6] = dw1;
232
233      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
234   }
235}
236
237static void
238i915BlendColor(struct gl_context * ctx, const GLfloat color[4])
239{
240   struct i915_context *i915 = I915_CONTEXT(ctx);
241   GLubyte r, g, b, a;
242   GLuint dw;
243
244   DBG("%s\n", __func__);
245
246   UNCLAMPED_FLOAT_TO_UBYTE(r, color[RCOMP]);
247   UNCLAMPED_FLOAT_TO_UBYTE(g, color[GCOMP]);
248   UNCLAMPED_FLOAT_TO_UBYTE(b, color[BCOMP]);
249   UNCLAMPED_FLOAT_TO_UBYTE(a, color[ACOMP]);
250
251   dw = (a << 24) | (r << 16) | (g << 8) | b;
252   if (dw != i915->state.Blend[I915_BLENDREG_BLENDCOLOR1]) {
253      i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = dw;
254      I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
255   }
256}
257
258
259#define DST_BLND_FACT(f) ((f)<<S6_CBUF_DST_BLEND_FACT_SHIFT)
260#define SRC_BLND_FACT(f) ((f)<<S6_CBUF_SRC_BLEND_FACT_SHIFT)
261#define DST_ABLND_FACT(f) ((f)<<IAB_DST_FACTOR_SHIFT)
262#define SRC_ABLND_FACT(f) ((f)<<IAB_SRC_FACTOR_SHIFT)
263
264
265
266static GLuint
267translate_blend_equation(GLenum mode)
268{
269   switch (mode) {
270   case GL_FUNC_ADD:
271      return BLENDFUNC_ADD;
272   case GL_MIN:
273      return BLENDFUNC_MIN;
274   case GL_MAX:
275      return BLENDFUNC_MAX;
276   case GL_FUNC_SUBTRACT:
277      return BLENDFUNC_SUBTRACT;
278   case GL_FUNC_REVERSE_SUBTRACT:
279      return BLENDFUNC_REVERSE_SUBTRACT;
280   default:
281      return 0;
282   }
283}
284
285static void
286i915UpdateBlendState(struct gl_context * ctx)
287{
288   struct i915_context *i915 = I915_CONTEXT(ctx);
289   GLuint iab = (i915->state.Blend[I915_BLENDREG_IAB] &
290                 ~(IAB_SRC_FACTOR_MASK |
291                   IAB_DST_FACTOR_MASK |
292                   (BLENDFUNC_MASK << IAB_FUNC_SHIFT) | IAB_ENABLE));
293
294   GLuint lis6 = (i915->state.Ctx[I915_CTXREG_LIS6] &
295                  ~(S6_CBUF_SRC_BLEND_FACT_MASK |
296                    S6_CBUF_DST_BLEND_FACT_MASK | S6_CBUF_BLEND_FUNC_MASK));
297
298   GLuint eqRGB = ctx->Color.Blend[0].EquationRGB;
299   GLuint eqA = ctx->Color.Blend[0].EquationA;
300   GLuint srcRGB = ctx->Color.Blend[0].SrcRGB;
301   GLuint dstRGB = ctx->Color.Blend[0].DstRGB;
302   GLuint srcA = ctx->Color.Blend[0].SrcA;
303   GLuint dstA = ctx->Color.Blend[0].DstA;
304
305   if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
306      srcRGB = dstRGB = GL_ONE;
307   }
308
309   if (eqA == GL_MIN || eqA == GL_MAX) {
310      srcA = dstA = GL_ONE;
311   }
312
313   lis6 |= SRC_BLND_FACT(intel_translate_blend_factor(srcRGB));
314   lis6 |= DST_BLND_FACT(intel_translate_blend_factor(dstRGB));
315   lis6 |= translate_blend_equation(eqRGB) << S6_CBUF_BLEND_FUNC_SHIFT;
316
317   iab |= SRC_ABLND_FACT(intel_translate_blend_factor(srcA));
318   iab |= DST_ABLND_FACT(intel_translate_blend_factor(dstA));
319   iab |= translate_blend_equation(eqA) << IAB_FUNC_SHIFT;
320
321   if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
322      iab |= IAB_ENABLE;
323
324   if (iab != i915->state.Blend[I915_BLENDREG_IAB]) {
325      i915->state.Blend[I915_BLENDREG_IAB] = iab;
326      I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
327   }
328   if (lis6 != i915->state.Ctx[I915_CTXREG_LIS6]) {
329      i915->state.Ctx[I915_CTXREG_LIS6] = lis6;
330      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
331   }
332
333   /* This will catch a logicop blend equation */
334   i915EvalLogicOpBlendState(ctx);
335}
336
337
338static void
339i915BlendFuncSeparate(struct gl_context * ctx, GLenum srcRGB,
340                      GLenum dstRGB, GLenum srcA, GLenum dstA)
341{
342   i915UpdateBlendState(ctx);
343}
344
345
346static void
347i915BlendEquationSeparate(struct gl_context * ctx, GLenum eqRGB, GLenum eqA)
348{
349   i915UpdateBlendState(ctx);
350}
351
352
353static void
354i915DepthFunc(struct gl_context * ctx, GLenum func)
355{
356   struct i915_context *i915 = I915_CONTEXT(ctx);
357   int test = intel_translate_compare_func(func);
358   GLuint dw;
359
360   DBG("%s\n", __func__);
361
362   dw = i915->state.Ctx[I915_CTXREG_LIS6];
363   dw &= ~S6_DEPTH_TEST_FUNC_MASK;
364   dw |= test << S6_DEPTH_TEST_FUNC_SHIFT;
365   if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
366      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
367      i915->state.Ctx[I915_CTXREG_LIS6] = dw;
368   }
369}
370
371static void
372i915DepthMask(struct gl_context * ctx, GLboolean flag)
373{
374   struct i915_context *i915 = I915_CONTEXT(ctx);
375   GLuint dw;
376
377   DBG("%s flag (%d)\n", __func__, flag);
378
379   if (!ctx->DrawBuffer || !ctx->DrawBuffer->Visual.depthBits)
380      flag = false;
381
382   dw = i915->state.Ctx[I915_CTXREG_LIS6];
383   if (flag && ctx->Depth.Test)
384      dw |= S6_DEPTH_WRITE_ENABLE;
385   else
386      dw &= ~S6_DEPTH_WRITE_ENABLE;
387   if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
388      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
389      i915->state.Ctx[I915_CTXREG_LIS6] = dw;
390   }
391}
392
393
394
395/**
396 * Update the viewport transformation matrix.  Depends on:
397 *  - viewport pos/size
398 *  - depthrange
399 *  - window pos/size or FBO size
400 */
401void
402intelCalcViewport(struct gl_context * ctx)
403{
404   struct intel_context *intel = intel_context(ctx);
405   float scale[3], translate[3];
406
407   _mesa_get_viewport_xform(ctx, 0, scale, translate);
408
409   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
410      scale[1] = -scale[1];
411      translate[1] = ctx->DrawBuffer->Height - translate[1];
412   }
413
414   _math_matrix_viewport(&intel->ViewportMatrix,
415                         scale, translate, 1.0);
416}
417
418
419/** Called from ctx->Driver.DepthRange() */
420static void
421i915DepthRange(struct gl_context *ctx)
422{
423   intelCalcViewport(ctx);
424}
425
426
427/* =============================================================
428 * Polygon stipple
429 *
430 * The i915 supports a 4x4 stipple natively, GL wants 32x32.
431 * Fortunately stipple is usually a repeating pattern.
432 */
433static void
434i915PolygonStipple(struct gl_context * ctx, const GLubyte * mask)
435{
436   struct i915_context *i915 = I915_CONTEXT(ctx);
437   const GLubyte *m;
438   GLubyte p[4];
439   int i, j, k;
440   int active = (ctx->Polygon.StippleFlag &&
441                 i915->intel.reduced_primitive == GL_TRIANGLES);
442   GLuint newMask;
443
444   if (active) {
445      I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
446      i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
447   }
448
449   /* Use the already unpacked stipple data from the context rather than the
450    * uninterpreted mask passed in.
451    */
452   mask = (const GLubyte *)ctx->PolygonStipple;
453   m = mask;
454
455   p[0] = mask[12] & 0xf;
456   p[0] |= p[0] << 4;
457   p[1] = mask[8] & 0xf;
458   p[1] |= p[1] << 4;
459   p[2] = mask[4] & 0xf;
460   p[2] |= p[2] << 4;
461   p[3] = mask[0] & 0xf;
462   p[3] |= p[3] << 4;
463
464   for (k = 0; k < 8; k++)
465      for (j = 3; j >= 0; j--)
466         for (i = 0; i < 4; i++, m++)
467            if (*m != p[j]) {
468               i915->intel.hw_stipple = 0;
469               return;
470            }
471
472   newMask = (((p[0] & 0xf) << 0) |
473              ((p[1] & 0xf) << 4) |
474              ((p[2] & 0xf) << 8) | ((p[3] & 0xf) << 12));
475
476
477   if (newMask == 0xffff || newMask == 0x0) {
478      /* this is needed to make conform pass */
479      i915->intel.hw_stipple = 0;
480      return;
481   }
482
483   i915->state.Stipple[I915_STPREG_ST1] &= ~0xffff;
484   i915->state.Stipple[I915_STPREG_ST1] |= newMask;
485   i915->intel.hw_stipple = 1;
486
487   if (active)
488      i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
489}
490
491
492/* =============================================================
493 * Hardware clipping
494 */
495static void
496i915Scissor(struct gl_context * ctx)
497{
498   struct i915_context *i915 = I915_CONTEXT(ctx);
499   int x1, y1, x2, y2;
500
501   if (!ctx->DrawBuffer)
502      return;
503
504   DBG("%s %d,%d %dx%d\n", __func__,
505       ctx->Scissor.ScissorArray[0].X,     ctx->Scissor.ScissorArray[0].Y,
506       ctx->Scissor.ScissorArray[0].Width, ctx->Scissor.ScissorArray[0].Height);
507
508   if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
509      x1 = ctx->Scissor.ScissorArray[0].X;
510      y1 = ctx->DrawBuffer->Height - (ctx->Scissor.ScissorArray[0].Y
511                                      + ctx->Scissor.ScissorArray[0].Height);
512      x2 = ctx->Scissor.ScissorArray[0].X
513         + ctx->Scissor.ScissorArray[0].Width - 1;
514      y2 = y1 + ctx->Scissor.ScissorArray[0].Height - 1;
515      DBG("%s %d..%d,%d..%d (inverted)\n", __func__, x1, x2, y1, y2);
516   }
517   else {
518      /* FBO - not inverted
519       */
520      x1 = ctx->Scissor.ScissorArray[0].X;
521      y1 = ctx->Scissor.ScissorArray[0].Y;
522      x2 = ctx->Scissor.ScissorArray[0].X
523         + ctx->Scissor.ScissorArray[0].Width - 1;
524      y2 = ctx->Scissor.ScissorArray[0].Y
525         + ctx->Scissor.ScissorArray[0].Height - 1;
526      DBG("%s %d..%d,%d..%d (not inverted)\n", __func__, x1, x2, y1, y2);
527   }
528
529   x1 = CLAMP(x1, 0, ctx->DrawBuffer->Width - 1);
530   y1 = CLAMP(y1, 0, ctx->DrawBuffer->Height - 1);
531   x2 = CLAMP(x2, 0, ctx->DrawBuffer->Width - 1);
532   y2 = CLAMP(y2, 0, ctx->DrawBuffer->Height - 1);
533
534   DBG("%s %d..%d,%d..%d (clamped)\n", __func__, x1, x2, y1, y2);
535
536   I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
537   i915->state.Buffer[I915_DESTREG_SR1] = (y1 << 16) | (x1 & 0xffff);
538   i915->state.Buffer[I915_DESTREG_SR2] = (y2 << 16) | (x2 & 0xffff);
539}
540
541static void
542i915LogicOp(struct gl_context * ctx, enum gl_logicop_mode opcode)
543{
544   struct i915_context *i915 = I915_CONTEXT(ctx);
545
546   DBG("%s\n", __func__);
547
548   assert((unsigned)opcode <= 15);
549   I915_STATECHANGE(i915, I915_UPLOAD_CTX);
550   i915->state.Ctx[I915_CTXREG_STATE4] &= ~LOGICOP_MASK;
551   i915->state.Ctx[I915_CTXREG_STATE4] |= LOGIC_OP_FUNC(opcode);
552}
553
554
555
556static void
557i915CullFaceFrontFace(struct gl_context * ctx, GLenum unused)
558{
559   struct i915_context *i915 = I915_CONTEXT(ctx);
560   GLuint mode, dw;
561
562   DBG("%s %d\n", __func__,
563       ctx->DrawBuffer ? ctx->DrawBuffer->Name : 0);
564
565   if (!ctx->Polygon.CullFlag) {
566      mode = S4_CULLMODE_NONE;
567   }
568   else if (ctx->Polygon.CullFaceMode != GL_FRONT_AND_BACK) {
569      mode = S4_CULLMODE_CW;
570
571      if (ctx->DrawBuffer && _mesa_is_user_fbo(ctx->DrawBuffer))
572         mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
573      if (ctx->Polygon.CullFaceMode == GL_FRONT)
574         mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
575      if (ctx->Polygon.FrontFace != GL_CCW)
576         mode ^= (S4_CULLMODE_CW ^ S4_CULLMODE_CCW);
577   }
578   else {
579      mode = S4_CULLMODE_BOTH;
580   }
581
582   dw = i915->state.Ctx[I915_CTXREG_LIS4];
583   dw &= ~S4_CULLMODE_MASK;
584   dw |= mode;
585   if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
586      i915->state.Ctx[I915_CTXREG_LIS4] = dw;
587      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
588   }
589}
590
591static void
592i915LineWidth(struct gl_context * ctx, GLfloat widthf)
593{
594   struct i915_context *i915 = I915_CONTEXT(ctx);
595   int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_LINE_WIDTH_MASK;
596   int width;
597
598   DBG("%s\n", __func__);
599
600   width = (int) (widthf * 2);
601   width = CLAMP(width, 1, 0xf);
602   lis4 |= width << S4_LINE_WIDTH_SHIFT;
603
604   if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
605      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
606      i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
607   }
608}
609
610static void
611i915PointSize(struct gl_context * ctx, GLfloat size)
612{
613   struct i915_context *i915 = I915_CONTEXT(ctx);
614   int lis4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_POINT_WIDTH_MASK;
615   GLint point_size = (int) round(size);
616
617   DBG("%s\n", __func__);
618
619   point_size = CLAMP(point_size, 1, 255);
620   lis4 |= point_size << S4_POINT_WIDTH_SHIFT;
621
622   if (lis4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
623      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
624      i915->state.Ctx[I915_CTXREG_LIS4] = lis4;
625   }
626}
627
628
629static void
630i915PointParameterfv(struct gl_context * ctx, GLenum pname, const GLfloat *params)
631{
632   struct i915_context *i915 = I915_CONTEXT(ctx);
633
634   switch (pname) {
635   case GL_POINT_SPRITE_COORD_ORIGIN:
636      /* This could be supported, but it would require modifying the fragment
637       * program to invert the y component of the texture coordinate by
638       * inserting a 'SUB tc.y, {1.0}.xxxx, tc' instruction.
639       */
640      FALLBACK(&i915->intel, I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN,
641	       (params[0] != GL_UPPER_LEFT));
642      break;
643   }
644}
645
646void
647i915_update_sprite_point_enable(struct gl_context *ctx)
648{
649   struct intel_context *intel = intel_context(ctx);
650   /* _NEW_PROGRAM */
651   struct i915_fragment_program *p =
652      (struct i915_fragment_program *) ctx->FragmentProgram._Current;
653   const GLbitfield64 inputsRead = p->FragProg.info.inputs_read;
654   struct i915_context *i915 = i915_context(ctx);
655   GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
656   GLuint coord_replace_bits = 0x0;
657
658   /* _NEW_POINT */
659   if (ctx->Point.PointSprite)
660      coord_replace_bits = ctx->Point.CoordReplace;
661
662   GLuint tex_coord_unit_bits =
663      (GLuint)((inputsRead & VARYING_BITS_TEX_ANY) >> VARYING_SLOT_TEX0);
664
665   /*
666    * Here we can't enable the SPRITE_POINT_ENABLE bit when the mis-match
667    * of tex_coord_unit_bits and coord_replace_bits, or this will make all
668    * the other non-point-sprite coords(like varying inputs, as we now use
669    * tex coord to implement varying inputs) be replaced to value (0, 0)-(1, 1).
670    *
671    * Thus, do fallback when needed.
672    */
673   FALLBACK(intel, I915_FALLBACK_COORD_REPLACE,
674            coord_replace_bits && coord_replace_bits != tex_coord_unit_bits);
675
676   s4 &= ~S4_SPRITE_POINT_ENABLE;
677   s4 |= (coord_replace_bits && coord_replace_bits == tex_coord_unit_bits) ?
678         S4_SPRITE_POINT_ENABLE : 0;
679   if (s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
680      i915->state.Ctx[I915_CTXREG_LIS4] = s4;
681      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
682   }
683}
684
685
686/* =============================================================
687 * Color masks
688 */
689
690static void
691i915ColorMask(struct gl_context * ctx,
692              GLboolean r, GLboolean g, GLboolean b, GLboolean a)
693{
694   struct i915_context *i915 = I915_CONTEXT(ctx);
695   GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK;
696
697   DBG("%s r(%d) g(%d) b(%d) a(%d)\n", __func__, r, g, b,
698       a);
699
700   if (!r)
701      tmp |= S5_WRITEDISABLE_RED;
702   if (!g)
703      tmp |= S5_WRITEDISABLE_GREEN;
704   if (!b)
705      tmp |= S5_WRITEDISABLE_BLUE;
706   if (!a)
707      tmp |= S5_WRITEDISABLE_ALPHA;
708
709   if (tmp != i915->state.Ctx[I915_CTXREG_LIS5]) {
710      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
711      i915->state.Ctx[I915_CTXREG_LIS5] = tmp;
712   }
713}
714
715static void
716update_specular(struct gl_context * ctx)
717{
718   /* A hack to trigger the rebuild of the fragment program.
719    */
720   intel_context(ctx)->NewGLState |= _NEW_TEXTURE;
721}
722
723static void
724i915LightModelfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
725{
726   DBG("%s\n", __func__);
727
728   if (pname == GL_LIGHT_MODEL_COLOR_CONTROL) {
729      update_specular(ctx);
730   }
731}
732
733static void
734i915ShadeModel(struct gl_context * ctx, GLenum mode)
735{
736   struct i915_context *i915 = I915_CONTEXT(ctx);
737   I915_STATECHANGE(i915, I915_UPLOAD_CTX);
738
739   if (mode == GL_SMOOTH) {
740      i915->state.Ctx[I915_CTXREG_LIS4] &= ~(S4_FLATSHADE_ALPHA |
741                                             S4_FLATSHADE_COLOR |
742                                             S4_FLATSHADE_SPECULAR);
743   }
744   else {
745      i915->state.Ctx[I915_CTXREG_LIS4] |= (S4_FLATSHADE_ALPHA |
746                                            S4_FLATSHADE_COLOR |
747                                            S4_FLATSHADE_SPECULAR);
748   }
749}
750
751/* =============================================================
752 * Fog
753 *
754 * This empty function remains because _mesa_init_driver_state calls
755 * dd_function_table::Fogfv unconditionally.  We have to have some function
756 * there so that it doesn't try to call a NULL pointer.
757 */
758static void
759i915Fogfv(struct gl_context * ctx, GLenum pname, const GLfloat * param)
760{
761   (void) ctx;
762   (void) pname;
763   (void) param;
764}
765
766/* =============================================================
767 */
768
769static void
770i915Enable(struct gl_context * ctx, GLenum cap, GLboolean state)
771{
772   struct i915_context *i915 = I915_CONTEXT(ctx);
773   GLuint dw;
774
775   switch (cap) {
776   case GL_TEXTURE_2D:
777      break;
778
779   case GL_LIGHTING:
780   case GL_COLOR_SUM:
781      update_specular(ctx);
782      break;
783
784   case GL_ALPHA_TEST:
785      dw = i915->state.Ctx[I915_CTXREG_LIS6];
786      if (state)
787         dw |= S6_ALPHA_TEST_ENABLE;
788      else
789         dw &= ~S6_ALPHA_TEST_ENABLE;
790      if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
791	 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
792	 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
793      }
794      break;
795
796   case GL_BLEND:
797      i915EvalLogicOpBlendState(ctx);
798      break;
799
800   case GL_COLOR_LOGIC_OP:
801      i915EvalLogicOpBlendState(ctx);
802
803      /* Logicop doesn't seem to work at 16bpp:
804       */
805      if (ctx->Visual.rgbBits == 16)
806         FALLBACK(&i915->intel, I915_FALLBACK_LOGICOP, state);
807      break;
808
809   case GL_FRAGMENT_PROGRAM_ARB:
810      break;
811
812   case GL_DITHER:
813      dw = i915->state.Ctx[I915_CTXREG_LIS5];
814      if (state)
815         dw |= S5_COLOR_DITHER_ENABLE;
816      else
817         dw &= ~S5_COLOR_DITHER_ENABLE;
818      if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
819	 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
820	 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
821      }
822      break;
823
824   case GL_DEPTH_TEST:
825      dw = i915->state.Ctx[I915_CTXREG_LIS6];
826
827      if (!ctx->DrawBuffer || !ctx->DrawBuffer->Visual.depthBits)
828	 state = false;
829
830      if (state)
831         dw |= S6_DEPTH_TEST_ENABLE;
832      else
833         dw &= ~S6_DEPTH_TEST_ENABLE;
834      if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
835	 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
836	 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
837      }
838
839      i915DepthMask(ctx, ctx->Depth.Mask);
840      break;
841
842   case GL_SCISSOR_TEST:
843      I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
844      if (state)
845         i915->state.Buffer[I915_DESTREG_SENABLE] =
846            (_3DSTATE_SCISSOR_ENABLE_CMD | ENABLE_SCISSOR_RECT);
847      else
848         i915->state.Buffer[I915_DESTREG_SENABLE] =
849            (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
850      break;
851
852   case GL_LINE_SMOOTH:
853      dw = i915->state.Ctx[I915_CTXREG_LIS4];
854      if (state)
855         dw |= S4_LINE_ANTIALIAS_ENABLE;
856      else
857         dw &= ~S4_LINE_ANTIALIAS_ENABLE;
858      if (dw != i915->state.Ctx[I915_CTXREG_LIS4]) {
859	 i915->state.Ctx[I915_CTXREG_LIS4] = dw;
860	 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
861      }
862      break;
863
864   case GL_CULL_FACE:
865      i915CullFaceFrontFace(ctx, 0);
866      break;
867
868   case GL_STENCIL_TEST:
869      if (!ctx->DrawBuffer || !ctx->DrawBuffer->Visual.stencilBits)
870	 state = false;
871
872      dw = i915->state.Ctx[I915_CTXREG_LIS5];
873      if (state)
874	 dw |= (S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
875      else
876	 dw &= ~(S5_STENCIL_TEST_ENABLE | S5_STENCIL_WRITE_ENABLE);
877      if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
878	 i915->state.Ctx[I915_CTXREG_LIS5] = dw;
879	 I915_STATECHANGE(i915, I915_UPLOAD_CTX);
880      }
881      break;
882
883   case GL_POLYGON_STIPPLE:
884      /* The stipple command worked on my 855GM box, but not my 845G.
885       * I'll do more testing later to find out exactly which hardware
886       * supports it.  Disabled for now.
887       */
888      if (i915->intel.hw_stipple &&
889          i915->intel.reduced_primitive == GL_TRIANGLES) {
890         I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
891         if (state)
892            i915->state.Stipple[I915_STPREG_ST1] |= ST1_ENABLE;
893         else
894            i915->state.Stipple[I915_STPREG_ST1] &= ~ST1_ENABLE;
895      }
896      break;
897
898   case GL_POLYGON_SMOOTH:
899      break;
900
901   case GL_POINT_SPRITE:
902      /* Handle it at i915_update_sprite_point_enable () */
903      break;
904
905   case GL_POINT_SMOOTH:
906      break;
907
908   default:
909      ;
910   }
911}
912
913
914static void
915i915_init_packets(struct i915_context *i915)
916{
917   /* Zero all state */
918   memset(&i915->state, 0, sizeof(i915->state));
919
920
921   {
922      I915_STATECHANGE(i915, I915_UPLOAD_CTX);
923      I915_STATECHANGE(i915, I915_UPLOAD_BLEND);
924      /* Probably don't want to upload all this stuff every time one
925       * piece changes.
926       */
927      i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
928                                         I1_LOAD_S(2) | I1_LOAD_S(3) |
929                                         I1_LOAD_S(4) | I1_LOAD_S(5) |
930                                         I1_LOAD_S(6) | (4));
931      i915->state.Ctx[I915_CTXREG_LIS2] = 0;
932      i915->state.Ctx[I915_CTXREG_LIS4] = 0;
933      i915->state.Ctx[I915_CTXREG_LIS3] = 0;
934      i915->state.Ctx[I915_CTXREG_LIS5] = 0;
935
936      if (i915->intel.ctx.Visual.rgbBits == 16)
937         i915->state.Ctx[I915_CTXREG_LIS5] |= S5_COLOR_DITHER_ENABLE;
938
939
940      i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE |
941                                           (2 << S6_TRISTRIP_PV_SHIFT));
942
943      i915->state.Ctx[I915_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
944                                             ENABLE_LOGIC_OP_FUNC |
945                                             LOGIC_OP_FUNC(LOGICOP_COPY) |
946                                             ENABLE_STENCIL_TEST_MASK |
947                                             STENCIL_TEST_MASK(0xff) |
948                                             ENABLE_STENCIL_WRITE_MASK |
949                                             STENCIL_WRITE_MASK(0xff));
950
951      i915->state.Blend[I915_BLENDREG_IAB] =
952         (_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | IAB_MODIFY_ENABLE |
953          IAB_MODIFY_FUNC | IAB_MODIFY_SRC_FACTOR | IAB_MODIFY_DST_FACTOR);
954
955      i915->state.Blend[I915_BLENDREG_BLENDCOLOR0] =
956         _3DSTATE_CONST_BLEND_COLOR_CMD;
957      i915->state.Blend[I915_BLENDREG_BLENDCOLOR1] = 0;
958
959      i915->state.Ctx[I915_CTXREG_BF_STENCIL_MASKS] =
960	 _3DSTATE_BACKFACE_STENCIL_MASKS |
961	 BFM_ENABLE_STENCIL_TEST_MASK |
962	 BFM_ENABLE_STENCIL_WRITE_MASK |
963	 (0xff << BFM_STENCIL_WRITE_MASK_SHIFT) |
964	 (0xff << BFM_STENCIL_TEST_MASK_SHIFT);
965      i915->state.Ctx[I915_CTXREG_BF_STENCIL_OPS] =
966	 _3DSTATE_BACKFACE_STENCIL_OPS |
967	 BFO_ENABLE_STENCIL_REF |
968	 BFO_ENABLE_STENCIL_FUNCS |
969	 BFO_ENABLE_STENCIL_TWO_SIDE;
970   }
971
972   {
973      I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
974      i915->state.Stipple[I915_STPREG_ST0] = _3DSTATE_STIPPLE;
975   }
976
977   {
978      i915->state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
979
980      /* scissor */
981      i915->state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
982      i915->state.Buffer[I915_DESTREG_SR1] = 0;
983      i915->state.Buffer[I915_DESTREG_SR2] = 0;
984      i915->state.Buffer[I915_DESTREG_SENABLE] =
985         (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
986   }
987
988   i915->state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |
989      ENABLE_POINT_RASTER_RULE |
990      OGL_POINT_RASTER_RULE |
991      ENABLE_LINE_STRIP_PROVOKE_VRTX |
992      ENABLE_TRI_FAN_PROVOKE_VRTX |
993      LINE_STRIP_PROVOKE_VRTX(1) |
994      TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D;
995
996#if 0
997   {
998      I915_STATECHANGE(i915, I915_UPLOAD_DEFAULTS);
999      i915->state.Default[I915_DEFREG_C0] = _3DSTATE_DEFAULT_DIFFUSE;
1000      i915->state.Default[I915_DEFREG_C1] = 0;
1001      i915->state.Default[I915_DEFREG_S0] = _3DSTATE_DEFAULT_SPECULAR;
1002      i915->state.Default[I915_DEFREG_S1] = 0;
1003      i915->state.Default[I915_DEFREG_Z0] = _3DSTATE_DEFAULT_Z;
1004      i915->state.Default[I915_DEFREG_Z1] = 0;
1005   }
1006#endif
1007
1008
1009   /* These will be emitted every at the head of every buffer, unless
1010    * we get hardware contexts working.
1011    */
1012   i915->state.active = (I915_UPLOAD_PROGRAM |
1013                         I915_UPLOAD_STIPPLE |
1014                         I915_UPLOAD_CTX |
1015                         I915_UPLOAD_BLEND |
1016                         I915_UPLOAD_BUFFERS |
1017			 I915_UPLOAD_INVARIENT |
1018			 I915_UPLOAD_RASTER_RULES);
1019}
1020
1021void
1022i915_update_provoking_vertex(struct gl_context * ctx)
1023{
1024   struct i915_context *i915 = I915_CONTEXT(ctx);
1025
1026   I915_STATECHANGE(i915, I915_UPLOAD_CTX);
1027   i915->state.Ctx[I915_CTXREG_LIS6] &= ~(S6_TRISTRIP_PV_MASK);
1028
1029   I915_STATECHANGE(i915, I915_UPLOAD_RASTER_RULES);
1030   i915->state.RasterRules[I915_RASTER_RULES] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK |
1031						   TRI_FAN_PROVOKE_VRTX_MASK);
1032
1033   /* _NEW_LIGHT */
1034   if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION) {
1035      i915->state.RasterRules[I915_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1036						     TRI_FAN_PROVOKE_VRTX(2));
1037      i915->state.Ctx[I915_CTXREG_LIS6] |= (2 << S6_TRISTRIP_PV_SHIFT);
1038   } else {
1039      i915->state.RasterRules[I915_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1040						     TRI_FAN_PROVOKE_VRTX(1));
1041      i915->state.Ctx[I915_CTXREG_LIS6] |= (0 << S6_TRISTRIP_PV_SHIFT);
1042    }
1043}
1044
1045/* Fallback to swrast for select and feedback.
1046 */
1047static void
1048i915RenderMode(struct gl_context *ctx, GLenum mode)
1049{
1050   struct intel_context *intel = intel_context(ctx);
1051   FALLBACK(intel, INTEL_FALLBACK_RENDERMODE, (mode != GL_RENDER));
1052}
1053
1054void
1055i915InitStateFunctions(struct dd_function_table *functions)
1056{
1057   functions->AlphaFunc = i915AlphaFunc;
1058   functions->BlendColor = i915BlendColor;
1059   functions->BlendEquationSeparate = i915BlendEquationSeparate;
1060   functions->BlendFuncSeparate = i915BlendFuncSeparate;
1061   functions->ColorMask = i915ColorMask;
1062   functions->CullFace = i915CullFaceFrontFace;
1063   functions->DepthFunc = i915DepthFunc;
1064   functions->DepthMask = i915DepthMask;
1065   functions->Enable = i915Enable;
1066   functions->Fogfv = i915Fogfv;
1067   functions->FrontFace = i915CullFaceFrontFace;
1068   functions->LightModelfv = i915LightModelfv;
1069   functions->LineWidth = i915LineWidth;
1070   functions->LogicOpcode = i915LogicOp;
1071   functions->PointSize = i915PointSize;
1072   functions->PointParameterfv = i915PointParameterfv;
1073   functions->PolygonStipple = i915PolygonStipple;
1074   functions->RenderMode = i915RenderMode;
1075   functions->Scissor = i915Scissor;
1076   functions->ShadeModel = i915ShadeModel;
1077   functions->StencilFuncSeparate = i915StencilFuncSeparate;
1078   functions->StencilMaskSeparate = i915StencilMaskSeparate;
1079   functions->StencilOpSeparate = i915StencilOpSeparate;
1080   functions->DepthRange = i915DepthRange;
1081}
1082
1083
1084void
1085i915InitState(struct i915_context *i915)
1086{
1087   struct gl_context *ctx = &i915->intel.ctx;
1088
1089   i915_init_packets(i915);
1090
1091   _mesa_init_driver_state(ctx);
1092}
1093