1/* 2 * Copyright 2003 VMware, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "main/mtypes.h" 27#include "main/blit.h" 28#include "main/context.h" 29#include "main/enums.h" 30#include "main/fbobject.h" 31 32#include "brw_context.h" 33#include "brw_defines.h" 34#include "brw_blit.h" 35#include "brw_buffers.h" 36#include "brw_fbo.h" 37#include "brw_batch.h" 38#include "brw_mipmap_tree.h" 39 40#define FILE_DEBUG_FLAG DEBUG_BLIT 41 42static void 43brw_miptree_set_alpha_to_one(struct brw_context *brw, 44 struct brw_mipmap_tree *mt, 45 int x, int y, int width, int height); 46 47static GLuint translate_raster_op(enum gl_logicop_mode logicop) 48{ 49 return logicop | (logicop << 4); 50} 51 52static uint32_t 53br13_for_cpp(int cpp) 54{ 55 switch (cpp) { 56 case 16: 57 return BR13_32323232; 58 case 8: 59 return BR13_16161616; 60 case 4: 61 return BR13_8888; 62 case 2: 63 return BR13_565; 64 case 1: 65 return BR13_8; 66 default: 67 unreachable("not reached"); 68 } 69} 70 71/** 72 * Emits the packet for switching the blitter from X to Y tiled or back. 73 * 74 * This has to be called in a single BEGIN_BATCH_BLT_TILED() / 75 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as 76 * part of the power context, not a render context, and if the batchbuffer was 77 * to get flushed between setting and blitting, or blitting and restoring, our 78 * tiling state would leak into other unsuspecting applications (like the X 79 * server). 80 */ 81static uint32_t * 82set_blitter_tiling(struct brw_context *brw, 83 bool dst_y_tiled, bool src_y_tiled, 84 uint32_t *__map) 85{ 86 const struct intel_device_info *devinfo = &brw->screen->devinfo; 87 const unsigned n_dwords = devinfo->ver >= 8 ? 5 : 4; 88 assert(devinfo->ver >= 6); 89 90 /* Idle the blitter before we update how tiling is interpreted. */ 91 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); 92 OUT_BATCH(0); 93 OUT_BATCH(0); 94 OUT_BATCH(0); 95 if (n_dwords == 5) 96 OUT_BATCH(0); 97 98 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); 99 OUT_BATCH(BCS_SWCTRL); 100 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | 101 (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) | 102 (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0)); 103 return __map; 104} 105#define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map) 106 107#define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \ 108 unsigned set_tiling_batch_size = 0; \ 109 if (dst_y_tiled || src_y_tiled) { \ 110 if (devinfo->ver >= 8) \ 111 set_tiling_batch_size = 16; \ 112 else \ 113 set_tiling_batch_size = 14; \ 114 } \ 115 BEGIN_BATCH_BLT(n + set_tiling_batch_size); \ 116 if (dst_y_tiled || src_y_tiled) \ 117 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled) 118 119#define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \ 120 if (dst_y_tiled || src_y_tiled) \ 121 SET_BLITTER_TILING(brw, false, false); \ 122 ADVANCE_BATCH() 123 124bool 125brw_miptree_blit_compatible_formats(mesa_format src, mesa_format dst) 126{ 127 /* The BLT doesn't handle sRGB conversion */ 128 assert(src == _mesa_get_srgb_format_linear(src)); 129 assert(dst == _mesa_get_srgb_format_linear(dst)); 130 131 /* No swizzle or format conversions possible, except... */ 132 if (src == dst) 133 return true; 134 135 /* ...we can either discard the alpha channel when going from A->X, 136 * or we can fill the alpha channel with 0xff when going from X->A 137 */ 138 if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM) 139 return (dst == MESA_FORMAT_B8G8R8A8_UNORM || 140 dst == MESA_FORMAT_B8G8R8X8_UNORM); 141 142 if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM) 143 return (dst == MESA_FORMAT_R8G8B8A8_UNORM || 144 dst == MESA_FORMAT_R8G8B8X8_UNORM); 145 146 /* We can also discard alpha when going from A2->X2 for 2 bit alpha, 147 * however we can't fill the alpha channel with two 1 bits when going 148 * from X2->A2, because brw_miptree_set_alpha_to_one() is not yet 149 * ready for this / can only handle 8 bit alpha. 150 */ 151 if (src == MESA_FORMAT_B10G10R10A2_UNORM) 152 return (dst == MESA_FORMAT_B10G10R10A2_UNORM || 153 dst == MESA_FORMAT_B10G10R10X2_UNORM); 154 155 if (src == MESA_FORMAT_R10G10B10A2_UNORM) 156 return (dst == MESA_FORMAT_R10G10B10A2_UNORM || 157 dst == MESA_FORMAT_R10G10B10X2_UNORM); 158 159 return false; 160} 161 162static void 163get_blit_intratile_offset_el(const struct brw_context *brw, 164 struct brw_mipmap_tree *mt, 165 uint32_t total_x_offset_el, 166 uint32_t total_y_offset_el, 167 uint64_t *tile_offset_B, 168 uint32_t *x_offset_el, 169 uint32_t *y_offset_el) 170{ 171 ASSERTED uint32_t z_offset_el, array_offset; 172 isl_tiling_get_intratile_offset_el(mt->surf.tiling, mt->surf.dim, 173 mt->surf.msaa_layout, 174 mt->cpp * 8, mt->surf.samples, 175 mt->surf.row_pitch_B, 176 mt->surf.array_pitch_el_rows, 177 total_x_offset_el, total_y_offset_el, 0, 0, 178 tile_offset_B, 179 x_offset_el, y_offset_el, 180 &z_offset_el, &array_offset); 181 assert(z_offset_el == 0); 182 assert(array_offset == 0); 183 184 if (mt->surf.tiling == ISL_TILING_LINEAR) { 185 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress: 186 * 187 * "Base address of the destination surface: X=0, Y=0. Lower 32bits 188 * of the 48bit addressing. When Src Tiling is enabled (Bit_15 189 * enabled), this address must be 4KB-aligned. When Tiling is not 190 * enabled, this address should be CL (64byte) aligned." 191 * 192 * The offsets we get from ISL in the tiled case are already aligned. 193 * In the linear case, we need to do some of our own aligning. 194 */ 195 uint32_t delta = *tile_offset_B & 63; 196 assert(delta % mt->cpp == 0); 197 *tile_offset_B -= delta; 198 *x_offset_el += delta / mt->cpp; 199 } else { 200 assert(*tile_offset_B % 4096 == 0); 201 } 202} 203 204static bool 205alignment_valid(struct brw_context *brw, unsigned offset, 206 enum isl_tiling tiling) 207{ 208 const struct intel_device_info *devinfo = &brw->screen->devinfo; 209 210 /* Tiled buffers must be page-aligned (4K). */ 211 if (tiling != ISL_TILING_LINEAR) 212 return (offset & 4095) == 0; 213 214 /* On Gfx8+, linear buffers must be cacheline-aligned. */ 215 if (devinfo->ver >= 8) 216 return (offset & 63) == 0; 217 218 return true; 219} 220 221static uint32_t 222xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling, 223 uint32_t cpp) 224{ 225 uint32_t CMD = 0; 226 227 assert(cpp <= 4); 228 switch (cpp) { 229 case 1: 230 case 2: 231 CMD = XY_SRC_COPY_BLT_CMD; 232 break; 233 case 4: 234 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 235 break; 236 default: 237 unreachable("not reached"); 238 } 239 240 if (dst_tiling != ISL_TILING_LINEAR) 241 CMD |= XY_DST_TILED; 242 243 if (src_tiling != ISL_TILING_LINEAR) 244 CMD |= XY_SRC_TILED; 245 246 return CMD; 247} 248 249/* Copy BitBlt 250 */ 251static bool 252emit_copy_blit(struct brw_context *brw, 253 GLuint cpp, 254 int32_t src_pitch, 255 struct brw_bo *src_buffer, 256 GLuint src_offset, 257 enum isl_tiling src_tiling, 258 int32_t dst_pitch, 259 struct brw_bo *dst_buffer, 260 GLuint dst_offset, 261 enum isl_tiling dst_tiling, 262 GLshort src_x, GLshort src_y, 263 GLshort dst_x, GLshort dst_y, 264 GLshort w, GLshort h, 265 enum gl_logicop_mode logic_op) 266{ 267 const struct intel_device_info *devinfo = &brw->screen->devinfo; 268 GLuint CMD, BR13; 269 int dst_y2 = dst_y + h; 270 int dst_x2 = dst_x + w; 271 bool dst_y_tiled = dst_tiling == ISL_TILING_Y0; 272 bool src_y_tiled = src_tiling == ISL_TILING_Y0; 273 uint32_t src_tile_w, src_tile_h; 274 uint32_t dst_tile_w, dst_tile_h; 275 276 if ((dst_y_tiled || src_y_tiled) && devinfo->ver < 6) 277 return false; 278 279 const unsigned bo_sizes = dst_buffer->size + src_buffer->size; 280 281 /* do space check before going any further */ 282 if (!brw_batch_has_aperture_space(brw, bo_sizes)) 283 brw_batch_flush(brw); 284 285 if (!brw_batch_has_aperture_space(brw, bo_sizes)) 286 return false; 287 288 unsigned length = devinfo->ver >= 8 ? 10 : 8; 289 290 brw_batch_require_space(brw, length * 4); 291 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 292 __func__, 293 src_buffer, src_pitch, src_offset, src_x, src_y, 294 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 295 296 isl_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h); 297 isl_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h); 298 299 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width 300 * (X direction width of the Tile). This is ensured while allocating the 301 * buffer object. 302 */ 303 assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0); 304 assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0); 305 306 /* For big formats (such as floating point), do the copy using 16 or 307 * 32bpp and multiply the coordinates. 308 */ 309 if (cpp > 4) { 310 if (cpp % 4 == 2) { 311 dst_x *= cpp / 2; 312 dst_x2 *= cpp / 2; 313 src_x *= cpp / 2; 314 cpp = 2; 315 } else { 316 assert(cpp % 4 == 0); 317 dst_x *= cpp / 4; 318 dst_x2 *= cpp / 4; 319 src_x *= cpp / 4; 320 cpp = 4; 321 } 322 } 323 324 if (!alignment_valid(brw, dst_offset, dst_tiling)) 325 return false; 326 if (!alignment_valid(brw, src_offset, src_tiling)) 327 return false; 328 329 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop 330 * the low bits. Offsets must be naturally aligned. 331 */ 332 if (src_pitch % 4 != 0 || src_offset % cpp != 0 || 333 dst_pitch % 4 != 0 || dst_offset % cpp != 0) 334 return false; 335 336 assert(cpp <= 4); 337 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16; 338 339 CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp); 340 341 /* For tiled source and destination, pitch value should be specified 342 * as a number of Dwords. 343 */ 344 if (dst_tiling != ISL_TILING_LINEAR) 345 dst_pitch /= 4; 346 347 if (src_tiling != ISL_TILING_LINEAR) 348 src_pitch /= 4; 349 350 if (dst_y2 <= dst_y || dst_x2 <= dst_x) 351 return true; 352 353 assert(dst_x < dst_x2); 354 assert(dst_y < dst_y2); 355 356 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled); 357 OUT_BATCH(CMD | (length - 2)); 358 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 359 OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X)); 360 OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X)); 361 if (devinfo->ver >= 8) { 362 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset); 363 } else { 364 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset); 365 } 366 OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X)); 367 OUT_BATCH((uint16_t)src_pitch); 368 if (devinfo->ver >= 8) { 369 OUT_RELOC64(src_buffer, 0, src_offset); 370 } else { 371 OUT_RELOC(src_buffer, 0, src_offset); 372 } 373 374 ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled); 375 376 brw_emit_mi_flush(brw); 377 378 return true; 379} 380 381static bool 382emit_miptree_blit(struct brw_context *brw, 383 struct brw_mipmap_tree *src_mt, 384 uint32_t src_x, uint32_t src_y, 385 struct brw_mipmap_tree *dst_mt, 386 uint32_t dst_x, uint32_t dst_y, 387 uint32_t width, uint32_t height, 388 bool reverse, enum gl_logicop_mode logicop) 389{ 390 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics 391 * Data Size Limitations): 392 * 393 * The BLT engine is capable of transferring very large quantities of 394 * graphics data. Any graphics data read from and written to the 395 * destination is permitted to represent a number of pixels that 396 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line 397 * at the destination. The maximum number of pixels that may be 398 * represented per scan line’s worth of graphics data depends on the 399 * color depth. 400 * 401 * The blitter's pitch is a signed 16-bit integer, but measured in bytes 402 * for linear surfaces and DWords for tiled surfaces. So the maximum 403 * pitch is 32k linear and 128k tiled. 404 */ 405 if (brw_miptree_blt_pitch(src_mt) >= 32768 || 406 brw_miptree_blt_pitch(dst_mt) >= 32768) { 407 perf_debug("Falling back due to >= 32k/128k pitch\n"); 408 return false; 409 } 410 411 /* We need to split the blit into chunks that each fit within the blitter's 412 * restrictions. We can't use a chunk size of 32768 because we need to 413 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's 414 * a nice round power of two, big enough that performance won't suffer, and 415 * small enough to guarantee everything fits. 416 */ 417 const uint32_t max_chunk_size = 16384; 418 419 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) { 420 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) { 421 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x); 422 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y); 423 424 uint64_t src_offset; 425 uint32_t src_tile_x, src_tile_y; 426 get_blit_intratile_offset_el(brw, src_mt, 427 src_x + chunk_x, src_y + chunk_y, 428 &src_offset, &src_tile_x, &src_tile_y); 429 430 uint64_t dst_offset; 431 uint32_t dst_tile_x, dst_tile_y; 432 get_blit_intratile_offset_el(brw, dst_mt, 433 dst_x + chunk_x, dst_y + chunk_y, 434 &dst_offset, &dst_tile_x, &dst_tile_y); 435 436 if (!emit_copy_blit(brw, 437 src_mt->cpp, 438 reverse ? -src_mt->surf.row_pitch_B : 439 src_mt->surf.row_pitch_B, 440 src_mt->bo, src_mt->offset + src_offset, 441 src_mt->surf.tiling, 442 dst_mt->surf.row_pitch_B, 443 dst_mt->bo, dst_mt->offset + dst_offset, 444 dst_mt->surf.tiling, 445 src_tile_x, src_tile_y, 446 dst_tile_x, dst_tile_y, 447 chunk_w, chunk_h, 448 logicop)) { 449 /* If this is ever going to fail, it will fail on the first chunk */ 450 assert(chunk_x == 0 && chunk_y == 0); 451 return false; 452 } 453 } 454 } 455 456 return true; 457} 458 459/** 460 * Implements a rectangular block transfer (blit) of pixels between two 461 * miptrees. 462 * 463 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous, 464 * but limited, pitches and sizes allowed. 465 * 466 * The src/dst coordinates are relative to the given level/slice of the 467 * miptree. 468 * 469 * If @src_flip or @dst_flip is set, then the rectangle within that miptree 470 * will be inverted (including scanline order) when copying. This is common 471 * in GL when copying between window system and user-created 472 * renderbuffers/textures. 473 */ 474bool 475brw_miptree_blit(struct brw_context *brw, 476 struct brw_mipmap_tree *src_mt, 477 int src_level, int src_slice, 478 uint32_t src_x, uint32_t src_y, bool src_flip, 479 struct brw_mipmap_tree *dst_mt, 480 int dst_level, int dst_slice, 481 uint32_t dst_x, uint32_t dst_y, bool dst_flip, 482 uint32_t width, uint32_t height, 483 enum gl_logicop_mode logicop) 484{ 485 /* The blitter doesn't understand multisampling at all. */ 486 if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1) 487 return false; 488 489 /* No sRGB decode or encode is done by the hardware blitter, which is 490 * consistent with what we want in many callers (glCopyTexSubImage(), 491 * texture validation, etc.). 492 */ 493 mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format); 494 mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format); 495 496 /* The blitter doesn't support doing any format conversions. We do also 497 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into 498 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A 499 * channel to 1.0 at the end. Also trivially ARGB2101010 to XRGB2101010, 500 * but not XRGB2101010 to ARGB2101010 yet. 501 */ 502 if (!brw_miptree_blit_compatible_formats(src_format, dst_format)) { 503 perf_debug("%s: Can't use hardware blitter from %s to %s, " 504 "falling back.\n", __func__, 505 _mesa_get_format_name(src_format), 506 _mesa_get_format_name(dst_format)); 507 return false; 508 } 509 510 /* The blitter has no idea about HiZ or fast color clears, so we need to 511 * resolve the miptrees before we do anything. 512 */ 513 brw_miptree_access_raw(brw, src_mt, src_level, src_slice, false); 514 brw_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true); 515 516 if (src_flip) { 517 const unsigned h0 = src_mt->surf.phys_level0_sa.height; 518 src_y = minify(h0, src_level - src_mt->first_level) - src_y - height; 519 } 520 521 if (dst_flip) { 522 const unsigned h0 = dst_mt->surf.phys_level0_sa.height; 523 dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height; 524 } 525 526 uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y; 527 brw_miptree_get_image_offset(src_mt, src_level, src_slice, 528 &src_image_x, &src_image_y); 529 brw_miptree_get_image_offset(dst_mt, dst_level, dst_slice, 530 &dst_image_x, &dst_image_y); 531 src_x += src_image_x; 532 src_y += src_image_y; 533 dst_x += dst_image_x; 534 dst_y += dst_image_y; 535 536 if (!emit_miptree_blit(brw, src_mt, src_x, src_y, 537 dst_mt, dst_x, dst_y, width, height, 538 src_flip != dst_flip, logicop)) { 539 return false; 540 } 541 542 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */ 543 if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 && 544 _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) { 545 brw_miptree_set_alpha_to_one(brw, dst_mt, dst_x, dst_y, width, height); 546 } 547 548 return true; 549} 550 551bool 552brw_miptree_copy(struct brw_context *brw, 553 struct brw_mipmap_tree *src_mt, 554 int src_level, int src_slice, 555 uint32_t src_x, uint32_t src_y, 556 struct brw_mipmap_tree *dst_mt, 557 int dst_level, int dst_slice, 558 uint32_t dst_x, uint32_t dst_y, 559 uint32_t src_width, uint32_t src_height) 560{ 561 /* The blitter doesn't understand multisampling at all. */ 562 if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1) 563 return false; 564 565 if (src_mt->format == MESA_FORMAT_S_UINT8) 566 return false; 567 568 /* The blitter has no idea about HiZ or fast color clears, so we need to 569 * resolve the miptrees before we do anything. 570 */ 571 brw_miptree_access_raw(brw, src_mt, src_level, src_slice, false); 572 brw_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true); 573 574 uint32_t src_image_x, src_image_y; 575 brw_miptree_get_image_offset(src_mt, src_level, src_slice, 576 &src_image_x, &src_image_y); 577 578 if (_mesa_is_format_compressed(src_mt->format)) { 579 GLuint bw, bh; 580 _mesa_get_format_block_size(src_mt->format, &bw, &bh); 581 582 /* Compressed textures need not have dimensions that are a multiple of 583 * the block size. Rectangles in compressed textures do need to be a 584 * multiple of the block size. The one exception is that the right and 585 * bottom edges may be at the right or bottom edge of the miplevel even 586 * if it's not aligned. 587 */ 588 assert(src_x % bw == 0); 589 assert(src_y % bh == 0); 590 591 assert(src_width % bw == 0 || 592 src_x + src_width == 593 minify(src_mt->surf.logical_level0_px.width, src_level)); 594 assert(src_height % bh == 0 || 595 src_y + src_height == 596 minify(src_mt->surf.logical_level0_px.height, src_level)); 597 598 src_x /= (int)bw; 599 src_y /= (int)bh; 600 src_width = DIV_ROUND_UP(src_width, (int)bw); 601 src_height = DIV_ROUND_UP(src_height, (int)bh); 602 } 603 src_x += src_image_x; 604 src_y += src_image_y; 605 606 uint32_t dst_image_x, dst_image_y; 607 brw_miptree_get_image_offset(dst_mt, dst_level, dst_slice, 608 &dst_image_x, &dst_image_y); 609 610 if (_mesa_is_format_compressed(dst_mt->format)) { 611 GLuint bw, bh; 612 _mesa_get_format_block_size(dst_mt->format, &bw, &bh); 613 614 assert(dst_x % bw == 0); 615 assert(dst_y % bh == 0); 616 617 dst_x /= (int)bw; 618 dst_y /= (int)bh; 619 } 620 dst_x += dst_image_x; 621 dst_y += dst_image_y; 622 623 return emit_miptree_blit(brw, src_mt, src_x, src_y, 624 dst_mt, dst_x, dst_y, 625 src_width, src_height, false, COLOR_LOGICOP_COPY); 626} 627 628bool 629brw_emit_immediate_color_expand_blit(struct brw_context *brw, 630 GLuint cpp, 631 GLubyte *src_bits, GLuint src_size, 632 GLuint fg_color, 633 GLshort dst_pitch, 634 struct brw_bo *dst_buffer, 635 GLuint dst_offset, 636 enum isl_tiling dst_tiling, 637 GLshort x, GLshort y, 638 GLshort w, GLshort h, 639 enum gl_logicop_mode logic_op) 640{ 641 const struct intel_device_info *devinfo = &brw->screen->devinfo; 642 int dwords = ALIGN(src_size, 8) / 4; 643 uint32_t opcode, br13, blit_cmd; 644 645 if (dst_tiling != ISL_TILING_LINEAR) { 646 if (dst_offset & 4095) 647 return false; 648 if (dst_tiling == ISL_TILING_Y0) 649 return false; 650 } 651 652 assert((unsigned) logic_op <= 0x0f); 653 assert(dst_pitch > 0); 654 655 if (w < 0 || h < 0) 656 return true; 657 658 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 659 __func__, 660 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 661 662 unsigned xy_setup_blt_length = devinfo->ver >= 8 ? 10 : 8; 663 brw_batch_require_space(brw, (xy_setup_blt_length * 4) + 664 (3 * 4) + dwords * 4); 665 666 opcode = XY_SETUP_BLT_CMD; 667 if (cpp == 4) 668 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 669 if (dst_tiling != ISL_TILING_LINEAR) { 670 opcode |= XY_DST_TILED; 671 dst_pitch /= 4; 672 } 673 674 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 675 br13 |= br13_for_cpp(cpp); 676 677 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 678 if (dst_tiling != ISL_TILING_LINEAR) 679 blit_cmd |= XY_DST_TILED; 680 681 BEGIN_BATCH_BLT(xy_setup_blt_length + 3); 682 OUT_BATCH(opcode | (xy_setup_blt_length - 2)); 683 OUT_BATCH(br13); 684 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 685 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 686 if (devinfo->ver >= 8) { 687 OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset); 688 } else { 689 OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset); 690 } 691 OUT_BATCH(0); /* bg */ 692 OUT_BATCH(fg_color); /* fg */ 693 OUT_BATCH(0); /* pattern base addr */ 694 if (devinfo->ver >= 8) 695 OUT_BATCH(0); 696 697 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 698 OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X)); 699 OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X)); 700 ADVANCE_BATCH(); 701 702 brw_batch_data(brw, src_bits, dwords * 4); 703 704 brw_emit_mi_flush(brw); 705 706 return true; 707} 708 709/** 710 * Used to initialize the alpha value of an ARGB8888 miptree after copying 711 * into it from an XRGB8888 source. 712 * 713 * This is very common with glCopyTexImage2D(). Note that the coordinates are 714 * relative to the start of the miptree, not relative to a slice within the 715 * miptree. 716 */ 717static void 718brw_miptree_set_alpha_to_one(struct brw_context *brw, 719 struct brw_mipmap_tree *mt, 720 int x, int y, int width, int height) 721{ 722 const struct intel_device_info *devinfo = &brw->screen->devinfo; 723 uint32_t BR13, CMD; 724 int pitch, cpp; 725 726 pitch = mt->surf.row_pitch_B; 727 cpp = mt->cpp; 728 729 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 730 __func__, mt->bo, pitch, x, y, width, height); 731 732 /* Note: Currently only handles 8 bit alpha channel. Extension to < 8 Bit 733 * alpha channel would be likely possible via ROP code 0xfa instead of 0xf0 734 * and writing a suitable bit-mask instead of 0xffffffff. 735 */ 736 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 737 CMD = XY_COLOR_BLT_CMD; 738 CMD |= XY_BLT_WRITE_ALPHA; 739 740 if (mt->surf.tiling != ISL_TILING_LINEAR) { 741 CMD |= XY_DST_TILED; 742 pitch /= 4; 743 } 744 BR13 |= pitch; 745 746 /* do space check before going any further */ 747 if (!brw_batch_has_aperture_space(brw, mt->bo->size)) 748 brw_batch_flush(brw); 749 750 unsigned length = devinfo->ver >= 8 ? 7 : 6; 751 const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0; 752 753 /* We need to split the blit into chunks that each fit within the blitter's 754 * restrictions. We can't use a chunk size of 32768 because we need to 755 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's 756 * a nice round power of two, big enough that performance won't suffer, and 757 * small enough to guarantee everything fits. 758 */ 759 const uint32_t max_chunk_size = 16384; 760 761 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) { 762 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) { 763 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x); 764 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y); 765 766 uint64_t offset_B; 767 uint32_t tile_x, tile_y; 768 get_blit_intratile_offset_el(brw, mt, 769 x + chunk_x, y + chunk_y, 770 &offset_B, &tile_x, &tile_y); 771 772 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false); 773 OUT_BATCH(CMD | (length - 2)); 774 OUT_BATCH(BR13); 775 OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) | 776 SET_FIELD(x + chunk_x, BLT_X)); 777 OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) | 778 SET_FIELD(x + chunk_x + chunk_w, BLT_X)); 779 if (devinfo->ver >= 8) { 780 OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset_B); 781 } else { 782 OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset_B); 783 } 784 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ 785 ADVANCE_BATCH_TILED(dst_y_tiled, false); 786 } 787 } 788 789 brw_emit_mi_flush(brw); 790} 791