1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * \file brw_tcs.c
26 *
27 * Tessellation control shader state upload code.
28 */
29
30#include "brw_context.h"
31#include "compiler/brw_nir.h"
32#include "brw_program.h"
33#include "brw_state.h"
34#include "program/prog_parameter.h"
35#include "nir_builder.h"
36
37static bool
38brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
39                     struct brw_program *tep, struct brw_tcs_prog_key *key)
40{
41   struct gl_context *ctx = &brw->ctx;
42   const struct brw_compiler *compiler = brw->screen->compiler;
43   const struct intel_device_info *devinfo = compiler->devinfo;
44   struct brw_stage_state *stage_state = &brw->tcs.base;
45   nir_shader *nir;
46   struct brw_tcs_prog_data prog_data;
47   bool start_busy = false;
48   double start_time = 0;
49
50   void *mem_ctx = ralloc_context(NULL);
51   if (tcp) {
52      nir = nir_shader_clone(mem_ctx, tcp->program.nir);
53   } else {
54      const nir_shader_compiler_options *options =
55         ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
56      nir = brw_nir_create_passthrough_tcs(mem_ctx, compiler, options, key);
57   }
58
59   memset(&prog_data, 0, sizeof(prog_data));
60
61   if (tcp) {
62      brw_assign_common_binding_table_offsets(devinfo, &tcp->program,
63                                              &prog_data.base.base, 0);
64
65      brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tcp->program,
66                                  &prog_data.base.base,
67                                  compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
68      if (brw->can_push_ubos) {
69         brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
70                                    prog_data.base.base.ubo_ranges);
71      }
72   } else {
73      /* Upload the Patch URB Header as the first two uniforms.
74       * Do the annoying scrambling so the shader doesn't have to.
75       */
76      assert(nir->num_uniforms == 32);
77      prog_data.base.base.param = rzalloc_array(mem_ctx, uint32_t, 8);
78      prog_data.base.base.nr_params = 8;
79
80      uint32_t *param = prog_data.base.base.param;
81      for (int i = 0; i < 8; i++)
82         param[i] = BRW_PARAM_BUILTIN_ZERO;
83
84      if (key->tes_primitive_mode == GL_QUADS) {
85         for (int i = 0; i < 4; i++)
86            param[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
87
88         param[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
89         param[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y;
90      } else if (key->tes_primitive_mode == GL_TRIANGLES) {
91         for (int i = 0; i < 3; i++)
92            param[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
93
94         param[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
95      } else {
96         assert(key->tes_primitive_mode == GL_ISOLINES);
97         param[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y;
98         param[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X;
99      }
100   }
101
102   int st_index = -1;
103   if (INTEL_DEBUG(DEBUG_SHADER_TIME) && tep)
104      st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
105
106   if (unlikely(brw->perf_debug)) {
107      start_busy = brw->batch.last_bo && brw_bo_busy(brw->batch.last_bo);
108      start_time = get_time();
109   }
110
111   char *error_str;
112   const unsigned *program =
113      brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index,
114                      NULL, &error_str);
115   if (program == NULL) {
116      if (tep) {
117         tep->program.sh.data->LinkStatus = LINKING_FAILURE;
118         ralloc_strcat(&tep->program.sh.data->InfoLog, error_str);
119      }
120
121      _mesa_problem(NULL, "Failed to compile tessellation control shader: "
122                    "%s\n", error_str);
123
124      ralloc_free(mem_ctx);
125      return false;
126   }
127
128   if (unlikely(brw->perf_debug)) {
129      if (tcp) {
130         if (tcp->compiled_once) {
131            brw_debug_recompile(brw, MESA_SHADER_TESS_CTRL, tcp->program.Id,
132                                &key->base);
133         }
134         tcp->compiled_once = true;
135      }
136
137      if (start_busy && !brw_bo_busy(brw->batch.last_bo)) {
138         perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
139                    (get_time() - start_time) * 1000);
140      }
141   }
142
143   /* Scratch space is used for register spilling */
144   brw_alloc_stage_scratch(brw, stage_state,
145                           prog_data.base.base.total_scratch);
146
147   /* The param and pull_param arrays will be freed by the shader cache. */
148   ralloc_steal(NULL, prog_data.base.base.param);
149   ralloc_steal(NULL, prog_data.base.base.pull_param);
150   brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG,
151                    key, sizeof(*key),
152                    program, prog_data.base.base.program_size,
153                    &prog_data, sizeof(prog_data),
154                    &stage_state->prog_offset, &brw->tcs.base.prog_data);
155   ralloc_free(mem_ctx);
156
157   return true;
158}
159
160void
161brw_tcs_populate_key(struct brw_context *brw,
162                     struct brw_tcs_prog_key *key)
163{
164   const struct intel_device_info *devinfo = &brw->screen->devinfo;
165   const struct brw_compiler *compiler = brw->screen->compiler;
166   struct brw_program *tcp =
167      (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
168   struct brw_program *tep =
169      (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
170   struct gl_program *tes_prog = &tep->program;
171
172   uint64_t per_vertex_slots = tes_prog->info.inputs_read;
173   uint32_t per_patch_slots = tes_prog->info.patch_inputs_read;
174
175   memset(key, 0, sizeof(*key));
176
177   if (tcp) {
178      struct gl_program *prog = &tcp->program;
179      per_vertex_slots |= prog->info.outputs_written;
180      per_patch_slots |= prog->info.patch_outputs_written;
181   }
182
183   if (devinfo->ver < 8 || !tcp || compiler->use_tcs_8_patch)
184      key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices;
185   key->outputs_written = per_vertex_slots;
186   key->patch_outputs_written = per_patch_slots;
187
188   /* We need to specialize our code generation for tessellation levels
189    * based on the domain the DS is expecting to tessellate.
190    */
191   key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
192   key->quads_workaround = devinfo->ver < 9 &&
193                           tep->program.info.tess.primitive_mode == GL_QUADS &&
194                           tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
195
196   if (tcp) {
197      /* _NEW_TEXTURE */
198      brw_populate_base_prog_key(&brw->ctx, tcp, &key->base);
199   }
200}
201
202void
203brw_upload_tcs_prog(struct brw_context *brw)
204{
205   struct brw_stage_state *stage_state = &brw->tcs.base;
206   struct brw_tcs_prog_key key;
207   /* BRW_NEW_TESS_PROGRAMS */
208   struct brw_program *tcp =
209      (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
210   ASSERTED struct brw_program *tep =
211      (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
212   assert(tep);
213
214   if (!brw_state_dirty(brw,
215                        _NEW_TEXTURE,
216                        BRW_NEW_PATCH_PRIMITIVE |
217                        BRW_NEW_TESS_PROGRAMS))
218      return;
219
220   brw_tcs_populate_key(brw, &key);
221
222   if (brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG, &key, sizeof(key),
223                        &stage_state->prog_offset, &brw->tcs.base.prog_data,
224                        true))
225      return;
226
227   if (brw_disk_cache_upload_program(brw, MESA_SHADER_TESS_CTRL))
228      return;
229
230   tcp = (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
231   if (tcp)
232      tcp->id = key.base.program_string_id;
233
234   ASSERTED bool success = brw_codegen_tcs_prog(brw, tcp, tep, &key);
235   assert(success);
236}
237
238void
239brw_tcs_populate_default_key(const struct brw_compiler *compiler,
240                             struct brw_tcs_prog_key *key,
241                             struct gl_shader_program *sh_prog,
242                             struct gl_program *prog)
243{
244   const struct intel_device_info *devinfo = compiler->devinfo;
245   struct brw_program *btcp = brw_program(prog);
246   const struct gl_linked_shader *tes =
247      sh_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
248
249   memset(key, 0, sizeof(*key));
250
251   brw_populate_default_base_prog_key(devinfo, btcp, &key->base);
252
253   /* Guess that the input and output patches have the same dimensionality. */
254   if (devinfo->ver < 8 || compiler->use_tcs_8_patch)
255      key->input_vertices = prog->info.tess.tcs_vertices_out;
256
257   if (tes) {
258      key->tes_primitive_mode = tes->Program->info.tess.primitive_mode;
259      key->quads_workaround = devinfo->ver < 9 &&
260                              tes->Program->info.tess.primitive_mode == GL_QUADS &&
261                              tes->Program->info.tess.spacing == TESS_SPACING_EQUAL;
262   } else {
263      key->tes_primitive_mode = GL_TRIANGLES;
264   }
265
266   key->outputs_written = prog->nir->info.outputs_written;
267   key->patch_outputs_written = prog->nir->info.patch_outputs_written;
268}
269
270bool
271brw_tcs_precompile(struct gl_context *ctx,
272                   struct gl_shader_program *shader_prog,
273                   struct gl_program *prog)
274{
275   struct brw_context *brw = brw_context(ctx);
276   const struct brw_compiler *compiler = brw->screen->compiler;
277   struct brw_tcs_prog_key key;
278   uint32_t old_prog_offset = brw->tcs.base.prog_offset;
279   struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
280   bool success;
281
282   struct brw_program *btcp = brw_program(prog);
283   const struct gl_linked_shader *tes =
284      shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
285   struct brw_program *btep = tes ? brw_program(tes->Program) : NULL;
286
287   brw_tcs_populate_default_key(compiler, &key, shader_prog, prog);
288
289   success = brw_codegen_tcs_prog(brw, btcp, btep, &key);
290
291   brw->tcs.base.prog_offset = old_prog_offset;
292   brw->tcs.base.prog_data = old_prog_data;
293
294   return success;
295}
296