1/* 2 * Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 * Intel funded Tungsten Graphics to 4 * develop this 3D driver. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sublicense, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26#include "brw_context.h" 27#include "brw_wm.h" 28#include "brw_state.h" 29#include "main/enums.h" 30#include "main/formats.h" 31#include "main/fbobject.h" 32#include "main/samplerobj.h" 33#include "main/framebuffer.h" 34#include "program/prog_parameter.h" 35#include "program/program.h" 36#include "brw_mipmap_tree.h" 37#include "brw_image.h" 38#include "brw_fbo.h" 39#include "compiler/brw_nir.h" 40#include "brw_program.h" 41 42#include "util/ralloc.h" 43#include "util/u_math.h" 44 45static void 46assign_fs_binding_table_offsets(const struct intel_device_info *devinfo, 47 const struct gl_program *prog, 48 const struct brw_wm_prog_key *key, 49 struct brw_wm_prog_data *prog_data) 50{ 51 /* Render targets implicitly start at surface index 0. Even if there are 52 * no color regions, we still perform an FB write to a null render target, 53 * which will be surface 0. 54 */ 55 uint32_t next_binding_table_offset = MAX2(key->nr_color_regions, 1); 56 57 next_binding_table_offset = 58 brw_assign_common_binding_table_offsets(devinfo, prog, &prog_data->base, 59 next_binding_table_offset); 60 61 if (prog->nir->info.outputs_read && !key->coherent_fb_fetch) { 62 prog_data->binding_table.render_target_read_start = 63 next_binding_table_offset; 64 next_binding_table_offset += key->nr_color_regions; 65 } 66 67 /* Update the binding table size */ 68 prog_data->base.binding_table.size_bytes = next_binding_table_offset * 4; 69} 70 71static bool 72brw_codegen_wm_prog(struct brw_context *brw, 73 struct brw_program *fp, 74 struct brw_wm_prog_key *key, 75 struct brw_vue_map *vue_map) 76{ 77 const struct intel_device_info *devinfo = &brw->screen->devinfo; 78 void *mem_ctx = ralloc_context(NULL); 79 struct brw_wm_prog_data prog_data; 80 const GLuint *program; 81 bool start_busy = false; 82 double start_time = 0; 83 84 nir_shader *nir = nir_shader_clone(mem_ctx, fp->program.nir); 85 86 memset(&prog_data, 0, sizeof(prog_data)); 87 88 /* Use ALT floating point mode for ARB programs so that 0^0 == 1. */ 89 if (fp->program.info.is_arb_asm) 90 prog_data.base.use_alt_mode = true; 91 92 assign_fs_binding_table_offsets(devinfo, &fp->program, key, &prog_data); 93 94 if (!fp->program.info.is_arb_asm) { 95 brw_nir_setup_glsl_uniforms(mem_ctx, nir, &fp->program, 96 &prog_data.base, true); 97 if (brw->can_push_ubos) { 98 brw_nir_analyze_ubo_ranges(brw->screen->compiler, nir, 99 NULL, prog_data.base.ubo_ranges); 100 } 101 } else { 102 brw_nir_setup_arb_uniforms(mem_ctx, nir, &fp->program, &prog_data.base); 103 104 if (INTEL_DEBUG(DEBUG_WM)) 105 brw_dump_arb_asm("fragment", &fp->program); 106 } 107 108 if (unlikely(brw->perf_debug)) { 109 start_busy = (brw->batch.last_bo && 110 brw_bo_busy(brw->batch.last_bo)); 111 start_time = get_time(); 112 } 113 114 struct brw_compile_fs_params params = { 115 .nir = nir, 116 .key = key, 117 .prog_data = &prog_data, 118 119 .allow_spilling = true, 120 .vue_map = vue_map, 121 122 .log_data = brw, 123 }; 124 125 if (INTEL_DEBUG(DEBUG_SHADER_TIME)) { 126 params.shader_time = true; 127 params.shader_time_index8 = 128 brw_get_shader_time_index(brw, &fp->program, ST_FS8, 129 !fp->program.info.is_arb_asm); 130 params.shader_time_index16 = 131 brw_get_shader_time_index(brw, &fp->program, ST_FS16, 132 !fp->program.info.is_arb_asm); 133 params.shader_time_index32 = 134 brw_get_shader_time_index(brw, &fp->program, ST_FS32, 135 !fp->program.info.is_arb_asm); 136 } 137 138 program = brw_compile_fs(brw->screen->compiler, mem_ctx, ¶ms); 139 140 if (program == NULL) { 141 if (!fp->program.info.is_arb_asm) { 142 fp->program.sh.data->LinkStatus = LINKING_FAILURE; 143 ralloc_strcat(&fp->program.sh.data->InfoLog, params.error_str); 144 } 145 146 _mesa_problem(NULL, "Failed to compile fragment shader: %s\n", params.error_str); 147 148 ralloc_free(mem_ctx); 149 return false; 150 } 151 152 if (unlikely(brw->perf_debug)) { 153 if (fp->compiled_once) { 154 brw_debug_recompile(brw, MESA_SHADER_FRAGMENT, fp->program.Id, 155 &key->base); 156 } 157 fp->compiled_once = true; 158 159 if (start_busy && !brw_bo_busy(brw->batch.last_bo)) { 160 perf_debug("FS compile took %.03f ms and stalled the GPU\n", 161 (get_time() - start_time) * 1000); 162 } 163 } 164 165 brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch); 166 167 if (INTEL_DEBUG(DEBUG_WM) && fp->program.info.is_arb_asm) 168 fprintf(stderr, "\n"); 169 170 /* The param and pull_param arrays will be freed by the shader cache. */ 171 ralloc_steal(NULL, prog_data.base.param); 172 ralloc_steal(NULL, prog_data.base.pull_param); 173 brw_upload_cache(&brw->cache, BRW_CACHE_FS_PROG, 174 key, sizeof(struct brw_wm_prog_key), 175 program, prog_data.base.program_size, 176 &prog_data, sizeof(prog_data), 177 &brw->wm.base.prog_offset, &brw->wm.base.prog_data); 178 179 ralloc_free(mem_ctx); 180 181 return true; 182} 183 184static uint8_t 185gfx6_gather_workaround(GLenum internalformat) 186{ 187 switch (internalformat) { 188 case GL_R8I: return WA_SIGN | WA_8BIT; 189 case GL_R8UI: return WA_8BIT; 190 case GL_R16I: return WA_SIGN | WA_16BIT; 191 case GL_R16UI: return WA_16BIT; 192 default: 193 /* Note that even though GL_R32I and GL_R32UI have format overrides in 194 * the surface state, there is no shader w/a required. 195 */ 196 return 0; 197 } 198} 199 200static void 201brw_populate_sampler_prog_key_data(struct gl_context *ctx, 202 const struct gl_program *prog, 203 struct brw_sampler_prog_key_data *key) 204{ 205 struct brw_context *brw = brw_context(ctx); 206 const struct intel_device_info *devinfo = &brw->screen->devinfo; 207 GLbitfield mask = prog->SamplersUsed; 208 209 while (mask) { 210 const int s = u_bit_scan(&mask); 211 212 key->swizzles[s] = SWIZZLE_NOOP; 213 key->scale_factors[s] = 0.0f; 214 215 int unit_id = prog->SamplerUnits[s]; 216 const struct gl_texture_unit *unit = &ctx->Texture.Unit[unit_id]; 217 218 if (unit->_Current && unit->_Current->Target != GL_TEXTURE_BUFFER) { 219 const struct gl_texture_object *t = unit->_Current; 220 const struct gl_texture_image *img = t->Image[0][t->Attrib.BaseLevel]; 221 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit_id); 222 223 const bool alpha_depth = t->Attrib.DepthMode == GL_ALPHA && 224 (img->_BaseFormat == GL_DEPTH_COMPONENT || 225 img->_BaseFormat == GL_DEPTH_STENCIL); 226 227 /* Haswell handles texture swizzling as surface format overrides 228 * (except for GL_ALPHA); all other platforms need MOVs in the shader. 229 */ 230 if (alpha_depth || (devinfo->verx10 <= 70)) 231 key->swizzles[s] = brw_get_texture_swizzle(ctx, t); 232 233 if (devinfo->ver < 8 && 234 sampler->Attrib.MinFilter != GL_NEAREST && 235 sampler->Attrib.MagFilter != GL_NEAREST) { 236 if (sampler->Attrib.WrapS == GL_CLAMP) 237 key->gl_clamp_mask[0] |= 1 << s; 238 if (sampler->Attrib.WrapT == GL_CLAMP) 239 key->gl_clamp_mask[1] |= 1 << s; 240 if (sampler->Attrib.WrapR == GL_CLAMP) 241 key->gl_clamp_mask[2] |= 1 << s; 242 } 243 244 /* gather4 for RG32* is broken in multiple ways on Gfx7. */ 245 if (devinfo->ver == 7 && prog->info.uses_texture_gather) { 246 switch (img->InternalFormat) { 247 case GL_RG32I: 248 case GL_RG32UI: { 249 /* We have to override the format to R32G32_FLOAT_LD. 250 * This means that SCS_ALPHA and SCS_ONE will return 0x3f8 251 * (1.0) rather than integer 1. This needs shader hacks. 252 * 253 * On Ivybridge, we whack W (alpha) to ONE in our key's 254 * swizzle. On Haswell, we look at the original texture 255 * swizzle, and use XYZW with channels overridden to ONE, 256 * leaving normal texture swizzling to SCS. 257 */ 258 unsigned src_swizzle = 259 devinfo->is_haswell ? t->Attrib._Swizzle : key->swizzles[s]; 260 for (int i = 0; i < 4; i++) { 261 unsigned src_comp = GET_SWZ(src_swizzle, i); 262 if (src_comp == SWIZZLE_ONE || src_comp == SWIZZLE_W) { 263 key->swizzles[i] &= ~(0x7 << (3 * i)); 264 key->swizzles[i] |= SWIZZLE_ONE << (3 * i); 265 } 266 } 267 } 268 FALLTHROUGH; 269 case GL_RG32F: 270 /* The channel select for green doesn't work - we have to 271 * request blue. Haswell can use SCS for this, but Ivybridge 272 * needs a shader workaround. 273 */ 274 if (!devinfo->is_haswell) 275 key->gather_channel_quirk_mask |= 1 << s; 276 break; 277 } 278 } 279 280 /* Gfx6's gather4 is broken for UINT/SINT; we treat them as 281 * UNORM/FLOAT instead and fix it in the shader. 282 */ 283 if (devinfo->ver == 6 && prog->info.uses_texture_gather) { 284 key->gfx6_gather_wa[s] = gfx6_gather_workaround(img->InternalFormat); 285 } 286 287 /* If this is a multisample sampler, and uses the CMS MSAA layout, 288 * then we need to emit slightly different code to first sample the 289 * MCS surface. 290 */ 291 struct brw_texture_object *intel_tex = 292 brw_texture_object((struct gl_texture_object *)t); 293 294 /* From gfx9 onwards some single sampled buffers can also be 295 * compressed. These don't need ld2dms sampling along with mcs fetch. 296 */ 297 if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) { 298 assert(devinfo->ver >= 7); 299 assert(intel_tex->mt->surf.samples > 1); 300 assert(intel_tex->mt->aux_buf); 301 assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY); 302 key->compressed_multisample_layout_mask |= 1 << s; 303 304 if (intel_tex->mt->surf.samples >= 16) { 305 assert(devinfo->ver >= 9); 306 key->msaa_16 |= 1 << s; 307 } 308 } 309 310 if (t->Target == GL_TEXTURE_EXTERNAL_OES && intel_tex->planar_format) { 311 312 /* Setup possible scaling factor. */ 313 key->scale_factors[s] = intel_tex->planar_format->scaling_factor; 314 315 switch (intel_tex->planar_format->components) { 316 case __DRI_IMAGE_COMPONENTS_Y_UV: 317 key->y_uv_image_mask |= 1 << s; 318 break; 319 case __DRI_IMAGE_COMPONENTS_Y_U_V: 320 key->y_u_v_image_mask |= 1 << s; 321 break; 322 case __DRI_IMAGE_COMPONENTS_Y_XUXV: 323 key->yx_xuxv_image_mask |= 1 << s; 324 break; 325 case __DRI_IMAGE_COMPONENTS_Y_UXVX: 326 key->xy_uxvx_image_mask |= 1 << s; 327 break; 328 case __DRI_IMAGE_COMPONENTS_AYUV: 329 key->ayuv_image_mask |= 1 << s; 330 break; 331 case __DRI_IMAGE_COMPONENTS_XYUV: 332 key->xyuv_image_mask |= 1 << s; 333 break; 334 default: 335 break; 336 } 337 338 switch (intel_tex->yuv_color_space) { 339 case __DRI_YUV_COLOR_SPACE_ITU_REC709: 340 key->bt709_mask |= 1 << s; 341 break; 342 case __DRI_YUV_COLOR_SPACE_ITU_REC2020: 343 key->bt2020_mask |= 1 << s; 344 break; 345 default: 346 break; 347 } 348 } 349 350 } 351 } 352} 353 354void 355brw_populate_base_prog_key(struct gl_context *ctx, 356 const struct brw_program *prog, 357 struct brw_base_prog_key *key) 358{ 359 key->program_string_id = prog->id; 360 key->subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM; 361 brw_populate_sampler_prog_key_data(ctx, &prog->program, &key->tex); 362} 363 364void 365brw_populate_default_base_prog_key(const struct intel_device_info *devinfo, 366 const struct brw_program *prog, 367 struct brw_base_prog_key *key) 368{ 369 key->program_string_id = prog->id; 370 key->subgroup_size_type = BRW_SUBGROUP_SIZE_UNIFORM; 371 brw_setup_tex_for_precompile(devinfo, &key->tex, &prog->program); 372} 373 374static bool 375brw_wm_state_dirty(const struct brw_context *brw) 376{ 377 return brw_state_dirty(brw, 378 _NEW_BUFFERS | 379 _NEW_COLOR | 380 _NEW_DEPTH | 381 _NEW_FRAG_CLAMP | 382 _NEW_HINT | 383 _NEW_LIGHT | 384 _NEW_LINE | 385 _NEW_MULTISAMPLE | 386 _NEW_POLYGON | 387 _NEW_STENCIL | 388 _NEW_TEXTURE, 389 BRW_NEW_FRAGMENT_PROGRAM | 390 BRW_NEW_REDUCED_PRIMITIVE | 391 BRW_NEW_STATS_WM | 392 BRW_NEW_VUE_MAP_GEOM_OUT); 393} 394 395void 396brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key) 397{ 398 const struct intel_device_info *devinfo = &brw->screen->devinfo; 399 struct gl_context *ctx = &brw->ctx; 400 /* BRW_NEW_FRAGMENT_PROGRAM */ 401 const struct gl_program *prog = brw->programs[MESA_SHADER_FRAGMENT]; 402 const struct brw_program *fp = brw_program_const(prog); 403 GLuint lookup = 0; 404 GLuint line_aa; 405 406 memset(key, 0, sizeof(*key)); 407 408 /* Build the index for table lookup 409 */ 410 if (devinfo->ver < 6) { 411 struct brw_renderbuffer *depth_irb = 412 brw_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); 413 414 /* _NEW_COLOR */ 415 if (prog->info.fs.uses_discard || ctx->Color.AlphaEnabled) { 416 lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT; 417 } 418 419 if (prog->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { 420 lookup |= BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT; 421 } 422 423 /* _NEW_DEPTH */ 424 if (depth_irb && ctx->Depth.Test) { 425 lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT; 426 427 if (brw_depth_writes_enabled(brw)) 428 lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT; 429 } 430 431 /* _NEW_STENCIL | _NEW_BUFFERS */ 432 if (brw->stencil_enabled) { 433 lookup |= BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT; 434 435 if (ctx->Stencil.WriteMask[0] || 436 ctx->Stencil.WriteMask[ctx->Stencil._BackFace]) 437 lookup |= BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT; 438 } 439 key->iz_lookup = lookup; 440 } 441 442 line_aa = BRW_WM_AA_NEVER; 443 444 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */ 445 if (ctx->Line.SmoothFlag) { 446 if (brw->reduced_primitive == GL_LINES) { 447 line_aa = BRW_WM_AA_ALWAYS; 448 } 449 else if (brw->reduced_primitive == GL_TRIANGLES) { 450 if (ctx->Polygon.FrontMode == GL_LINE) { 451 line_aa = BRW_WM_AA_SOMETIMES; 452 453 if (ctx->Polygon.BackMode == GL_LINE || 454 (ctx->Polygon.CullFlag && 455 ctx->Polygon.CullFaceMode == GL_BACK)) 456 line_aa = BRW_WM_AA_ALWAYS; 457 } 458 else if (ctx->Polygon.BackMode == GL_LINE) { 459 line_aa = BRW_WM_AA_SOMETIMES; 460 461 if ((ctx->Polygon.CullFlag && 462 ctx->Polygon.CullFaceMode == GL_FRONT)) 463 line_aa = BRW_WM_AA_ALWAYS; 464 } 465 } 466 } 467 468 key->line_aa = line_aa; 469 470 /* _NEW_HINT */ 471 key->high_quality_derivatives = 472 prog->info.uses_fddx_fddy && 473 ctx->Hint.FragmentShaderDerivative == GL_NICEST; 474 475 if (devinfo->ver < 6) 476 key->stats_wm = brw->stats_wm; 477 478 /* _NEW_LIGHT */ 479 key->flat_shade = 480 (prog->info.inputs_read & (VARYING_BIT_COL0 | VARYING_BIT_COL1)) && 481 (ctx->Light.ShadeModel == GL_FLAT); 482 483 /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */ 484 key->clamp_fragment_color = ctx->Color._ClampFragmentColor; 485 486 /* _NEW_TEXTURE */ 487 brw_populate_base_prog_key(ctx, fp, &key->base); 488 489 /* _NEW_BUFFERS */ 490 key->nr_color_regions = ctx->DrawBuffer->_NumColorDrawBuffers; 491 492 /* _NEW_COLOR */ 493 key->force_dual_color_blend = brw->dual_color_blend_by_location && 494 (ctx->Color.BlendEnabled & 1) && ctx->Color._BlendUsesDualSrc & 0x1; 495 496 /* _NEW_MULTISAMPLE, _NEW_BUFFERS */ 497 key->alpha_to_coverage = _mesa_is_alpha_to_coverage_enabled(ctx); 498 499 /* _NEW_COLOR, _NEW_BUFFERS */ 500 key->alpha_test_replicate_alpha = 501 ctx->DrawBuffer->_NumColorDrawBuffers > 1 && 502 _mesa_is_alpha_test_enabled(ctx); 503 504 /* _NEW_BUFFERS _NEW_MULTISAMPLE */ 505 /* Ignore sample qualifier while computing this flag. */ 506 if (ctx->Multisample.Enabled) { 507 key->persample_interp = 508 ctx->Multisample.SampleShading && 509 (ctx->Multisample.MinSampleShadingValue * 510 _mesa_geometric_samples(ctx->DrawBuffer) > 1); 511 512 key->multisample_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1; 513 } 514 515 key->ignore_sample_mask_out = !key->multisample_fbo; 516 517 /* BRW_NEW_VUE_MAP_GEOM_OUT */ 518 if (devinfo->ver < 6 || util_bitcount64(prog->info.inputs_read & 519 BRW_FS_VARYING_INPUT_MASK) > 16) { 520 key->input_slots_valid = brw->vue_map_geom_out.slots_valid; 521 } 522 523 /* _NEW_COLOR | _NEW_BUFFERS */ 524 /* Pre-gfx6, the hardware alpha test always used each render 525 * target's alpha to do alpha test, as opposed to render target 0's alpha 526 * like GL requires. Fix that by building the alpha test into the 527 * shader, and we'll skip enabling the fixed function alpha test. 528 */ 529 if (devinfo->ver < 6 && ctx->DrawBuffer->_NumColorDrawBuffers > 1 && 530 ctx->Color.AlphaEnabled) { 531 key->alpha_test_func = ctx->Color.AlphaFunc; 532 key->alpha_test_ref = ctx->Color.AlphaRef; 533 } 534 535 /* Whether reads from the framebuffer should behave coherently. */ 536 key->coherent_fb_fetch = ctx->Extensions.EXT_shader_framebuffer_fetch; 537} 538 539void 540brw_upload_wm_prog(struct brw_context *brw) 541{ 542 struct brw_wm_prog_key key; 543 struct brw_program *fp = 544 (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT]; 545 546 if (!brw_wm_state_dirty(brw)) 547 return; 548 549 brw_wm_populate_key(brw, &key); 550 551 if (brw_search_cache(&brw->cache, BRW_CACHE_FS_PROG, &key, sizeof(key), 552 &brw->wm.base.prog_offset, &brw->wm.base.prog_data, 553 true)) 554 return; 555 556 if (brw_disk_cache_upload_program(brw, MESA_SHADER_FRAGMENT)) 557 return; 558 559 fp = (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT]; 560 fp->id = key.base.program_string_id; 561 562 ASSERTED bool success = brw_codegen_wm_prog(brw, fp, &key, 563 &brw->vue_map_geom_out); 564 assert(success); 565} 566 567void 568brw_wm_populate_default_key(const struct brw_compiler *compiler, 569 struct brw_wm_prog_key *key, 570 struct gl_program *prog) 571{ 572 const struct intel_device_info *devinfo = compiler->devinfo; 573 574 memset(key, 0, sizeof(*key)); 575 576 brw_populate_default_base_prog_key(devinfo, brw_program(prog), 577 &key->base); 578 579 uint64_t outputs_written = prog->info.outputs_written; 580 581 if (devinfo->ver < 6) { 582 if (prog->info.fs.uses_discard) 583 key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT; 584 585 if (outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) 586 key->iz_lookup |= BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT; 587 588 /* Just assume depth testing. */ 589 key->iz_lookup |= BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT; 590 key->iz_lookup |= BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT; 591 } 592 593 if (devinfo->ver < 6 || util_bitcount64(prog->info.inputs_read & 594 BRW_FS_VARYING_INPUT_MASK) > 16) { 595 key->input_slots_valid = prog->info.inputs_read | VARYING_BIT_POS; 596 } 597 598 key->nr_color_regions = util_bitcount64(outputs_written & 599 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH) | 600 BITFIELD64_BIT(FRAG_RESULT_STENCIL) | 601 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK))); 602 603 /* Whether reads from the framebuffer should behave coherently. */ 604 key->coherent_fb_fetch = devinfo->ver >= 9; 605} 606 607bool 608brw_fs_precompile(struct gl_context *ctx, struct gl_program *prog) 609{ 610 struct brw_context *brw = brw_context(ctx); 611 const struct intel_device_info *devinfo = &brw->screen->devinfo; 612 struct brw_wm_prog_key key; 613 614 struct brw_program *bfp = brw_program(prog); 615 616 brw_wm_populate_default_key(brw->screen->compiler, &key, prog); 617 618 /* check brw_wm_populate_default_key coherent_fb_fetch setting */ 619 assert(key.coherent_fb_fetch == 620 ctx->Extensions.EXT_shader_framebuffer_fetch); 621 622 uint32_t old_prog_offset = brw->wm.base.prog_offset; 623 struct brw_stage_prog_data *old_prog_data = brw->wm.base.prog_data; 624 625 struct brw_vue_map vue_map; 626 if (devinfo->ver < 6) { 627 brw_compute_vue_map(&brw->screen->devinfo, &vue_map, 628 prog->info.inputs_read | VARYING_BIT_POS, 629 false, 1); 630 } 631 632 bool success = brw_codegen_wm_prog(brw, bfp, &key, &vue_map); 633 634 brw->wm.base.prog_offset = old_prog_offset; 635 brw->wm.base.prog_data = old_prog_data; 636 637 return success; 638} 639