17ec681f3Smrg/*
27ec681f3Smrg * XML DRI client-side driver configuration
37ec681f3Smrg * Copyright (C) 2003 Felix Kuehling
47ec681f3Smrg *
57ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
67ec681f3Smrg * copy of this software and associated documentation files (the "Software"),
77ec681f3Smrg * to deal in the Software without restriction, including without limitation
87ec681f3Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
97ec681f3Smrg * and/or sell copies of the Software, and to permit persons to whom the
107ec681f3Smrg * Software is furnished to do so, subject to the following conditions:
117ec681f3Smrg *
127ec681f3Smrg * The above copyright notice and this permission notice shall be included
137ec681f3Smrg * in all copies or substantial portions of the Software.
147ec681f3Smrg *
157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
167ec681f3Smrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
187ec681f3Smrg * FELIX KUEHLING, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
197ec681f3Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
207ec681f3Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
217ec681f3Smrg * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
227ec681f3Smrg *
237ec681f3Smrg */
247ec681f3Smrg/**
257ec681f3Smrg * \file driconf.h
267ec681f3Smrg * \brief Pool of common options
277ec681f3Smrg * \author Felix Kuehling
287ec681f3Smrg *
297ec681f3Smrg * This file defines macros that can be used to construct
307ec681f3Smrg * driConfigOptions in the drivers.
317ec681f3Smrg */
327ec681f3Smrg
337ec681f3Smrg#ifndef __DRICONF_H
347ec681f3Smrg#define __DRICONF_H
357ec681f3Smrg
367ec681f3Smrg#include "xmlconfig.h"
377ec681f3Smrg
387ec681f3Smrg/*
397ec681f3Smrg * generic macros
407ec681f3Smrg */
417ec681f3Smrg
427ec681f3Smrg/** \brief Names a section of related options to follow */
437ec681f3Smrg#define DRI_CONF_SECTION(text) { .desc = text, .info = { .type = DRI_SECTION } },
447ec681f3Smrg#define DRI_CONF_SECTION_END
457ec681f3Smrg
467ec681f3Smrg/** \brief End an option description */
477ec681f3Smrg#define DRI_CONF_OPT_END },
487ec681f3Smrg
497ec681f3Smrg/** \brief A verbal description (empty version) */
507ec681f3Smrg#define DRI_CONF_DESC(text) .desc = text,
517ec681f3Smrg
527ec681f3Smrg/** \brief A verbal description of an enum value */
537ec681f3Smrg#define DRI_CONF_ENUM(_value,text) { .value = _value, .desc = text },
547ec681f3Smrg
557ec681f3Smrg#define DRI_CONF_RANGE_I(min, max)              \
567ec681f3Smrg      .range = {                                \
577ec681f3Smrg         .start = { ._int = min },              \
587ec681f3Smrg         .end = { ._int = max },                \
597ec681f3Smrg      }                                         \
607ec681f3Smrg
617ec681f3Smrg#define DRI_CONF_RANGE_F(min, max)              \
627ec681f3Smrg      .range = {                                \
637ec681f3Smrg         .start = { ._float = min },            \
647ec681f3Smrg         .end = { ._float = max },              \
657ec681f3Smrg      }                                         \
667ec681f3Smrg
677ec681f3Smrg/**
687ec681f3Smrg * \brief A boolean option definition, with the default value passed in as a
697ec681f3Smrg * string
707ec681f3Smrg */
717ec681f3Smrg
727ec681f3Smrg#define DRI_CONF_OPT_B(_name, def, _desc) {                     \
737ec681f3Smrg      .desc = _desc,                                            \
747ec681f3Smrg      .info = {                                                 \
757ec681f3Smrg         .name = #_name,                                        \
767ec681f3Smrg         .type = DRI_BOOL,                                      \
777ec681f3Smrg      },                                                        \
787ec681f3Smrg      .value = { ._bool = def },                                \
797ec681f3Smrg   },
807ec681f3Smrg
817ec681f3Smrg#define DRI_CONF_OPT_I(_name, def, min, max, _desc) {           \
827ec681f3Smrg      .desc = _desc,                                            \
837ec681f3Smrg      .info = {                                                 \
847ec681f3Smrg         .name = #_name,                                        \
857ec681f3Smrg         .type = DRI_INT,                                       \
867ec681f3Smrg         DRI_CONF_RANGE_I(min, max),                            \
877ec681f3Smrg      },                                                        \
887ec681f3Smrg      .value = { ._int = def },                                 \
897ec681f3Smrg   },
907ec681f3Smrg
917ec681f3Smrg#define DRI_CONF_OPT_F(_name, def, min, max, _desc) {           \
927ec681f3Smrg      .desc = _desc,                                            \
937ec681f3Smrg      .info = {                                                 \
947ec681f3Smrg         .name = #_name,                                        \
957ec681f3Smrg         .type = DRI_FLOAT,                                     \
967ec681f3Smrg         DRI_CONF_RANGE_F(min, max),                            \
977ec681f3Smrg      },                                                        \
987ec681f3Smrg      .value = { ._float = def },                               \
997ec681f3Smrg   },
1007ec681f3Smrg
1017ec681f3Smrg#define DRI_CONF_OPT_E(_name, def, min, max, _desc, values) {   \
1027ec681f3Smrg      .desc = _desc,                                            \
1037ec681f3Smrg      .info = {                                                 \
1047ec681f3Smrg         .name = #_name,                                        \
1057ec681f3Smrg         .type = DRI_ENUM,                                      \
1067ec681f3Smrg         DRI_CONF_RANGE_I(min, max),                            \
1077ec681f3Smrg      },                                                        \
1087ec681f3Smrg      .value = { ._int = def },                                 \
1097ec681f3Smrg      .enums = { values },                                      \
1107ec681f3Smrg   },
1117ec681f3Smrg
1127ec681f3Smrg#define DRI_CONF_OPT_S(_name, def, _desc) {                     \
1137ec681f3Smrg      .desc = _desc,                                            \
1147ec681f3Smrg      .info = {                                                 \
1157ec681f3Smrg         .name = #_name,                                        \
1167ec681f3Smrg         .type = DRI_STRING,                                    \
1177ec681f3Smrg      },                                                        \
1187ec681f3Smrg      .value = { ._string = #def },                             \
1197ec681f3Smrg   },
1207ec681f3Smrg
1217ec681f3Smrg#define DRI_CONF_OPT_S_NODEF(_name, _desc) {                    \
1227ec681f3Smrg      .desc = _desc,                                            \
1237ec681f3Smrg      .info = {                                                 \
1247ec681f3Smrg         .name = #_name,                                        \
1257ec681f3Smrg         .type = DRI_STRING,                                    \
1267ec681f3Smrg      },                                                        \
1277ec681f3Smrg      .value = { ._string = "" },                               \
1287ec681f3Smrg   },
1297ec681f3Smrg
1307ec681f3Smrg/**
1317ec681f3Smrg * \brief Debugging options
1327ec681f3Smrg */
1337ec681f3Smrg#define DRI_CONF_SECTION_DEBUG DRI_CONF_SECTION("Debugging")
1347ec681f3Smrg
1357ec681f3Smrg#define DRI_CONF_ALWAYS_FLUSH_BATCH(def) \
1367ec681f3Smrg   DRI_CONF_OPT_B(always_flush_batch, def,                              \
1377ec681f3Smrg                  "Enable flushing batchbuffer after each draw call")
1387ec681f3Smrg
1397ec681f3Smrg#define DRI_CONF_ALWAYS_FLUSH_CACHE(def) \
1407ec681f3Smrg   DRI_CONF_OPT_B(always_flush_cache, def, \
1417ec681f3Smrg                  "Enable flushing GPU caches with each draw call")
1427ec681f3Smrg
1437ec681f3Smrg#define DRI_CONF_DISABLE_THROTTLING(def) \
1447ec681f3Smrg   DRI_CONF_OPT_B(disable_throttling, def, \
1457ec681f3Smrg                  "Disable throttling on first batch after flush")
1467ec681f3Smrg
1477ec681f3Smrg#define DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN(def) \
1487ec681f3Smrg   DRI_CONF_OPT_B(force_glsl_extensions_warn, def, \
1497ec681f3Smrg                  "Force GLSL extension default behavior to 'warn'")
1507ec681f3Smrg
1517ec681f3Smrg#define DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED(def) \
1527ec681f3Smrg   DRI_CONF_OPT_B(disable_blend_func_extended, def, \
1537ec681f3Smrg                  "Disable dual source blending")
1547ec681f3Smrg
1557ec681f3Smrg#define DRI_CONF_DISABLE_ARB_GPU_SHADER5(def) \
1567ec681f3Smrg   DRI_CONF_OPT_B(disable_arb_gpu_shader5, def, \
1577ec681f3Smrg                  "Disable GL_ARB_gpu_shader5")
1587ec681f3Smrg
1597ec681f3Smrg#define DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION(def) \
1607ec681f3Smrg   DRI_CONF_OPT_B(dual_color_blend_by_location, def, \
1617ec681f3Smrg                  "Identify dual color blending sources by location rather than index")
1627ec681f3Smrg
1637ec681f3Smrg#define DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS(def) \
1647ec681f3Smrg   DRI_CONF_OPT_B(disable_glsl_line_continuations, def, \
1657ec681f3Smrg                  "Disable backslash-based line continuations in GLSL source")
1667ec681f3Smrg
1677ec681f3Smrg#define DRI_CONF_FORCE_GLSL_VERSION(def) \
1687ec681f3Smrg   DRI_CONF_OPT_I(force_glsl_version, def, 0, 999, \
1697ec681f3Smrg                  "Force a default GLSL version for shaders that lack an explicit #version line")
1707ec681f3Smrg
1717ec681f3Smrg#define DRI_CONF_ALLOW_EXTRA_PP_TOKENS(def) \
1727ec681f3Smrg   DRI_CONF_OPT_B(allow_extra_pp_tokens, def, \
1737ec681f3Smrg                  "Allow extra tokens at end of preprocessor directives.")
1747ec681f3Smrg
1757ec681f3Smrg#define DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER(def) \
1767ec681f3Smrg   DRI_CONF_OPT_B(allow_glsl_extension_directive_midshader, def, \
1777ec681f3Smrg                  "Allow GLSL #extension directives in the middle of shaders")
1787ec681f3Smrg
1797ec681f3Smrg#define DRI_CONF_ALLOW_GLSL_120_SUBSET_IN_110(def) \
1807ec681f3Smrg   DRI_CONF_OPT_B(allow_glsl_120_subset_in_110, def, \
1817ec681f3Smrg                  "Allow a subset of GLSL 1.20 in GLSL 1.10 as needed by SPECviewperf13")
1827ec681f3Smrg
1837ec681f3Smrg#define DRI_CONF_ALLOW_GLSL_BUILTIN_CONST_EXPRESSION(def) \
1847ec681f3Smrg   DRI_CONF_OPT_B(allow_glsl_builtin_const_expression, def, \
1857ec681f3Smrg                  "Allow builtins as part of constant expressions")
1867ec681f3Smrg
1877ec681f3Smrg#define DRI_CONF_ALLOW_GLSL_RELAXED_ES(def) \
1887ec681f3Smrg   DRI_CONF_OPT_B(allow_glsl_relaxed_es, def, \
1897ec681f3Smrg                  "Allow some relaxation of GLSL ES shader restrictions")
1907ec681f3Smrg
1917ec681f3Smrg#define DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION(def) \
1927ec681f3Smrg   DRI_CONF_OPT_B(allow_glsl_builtin_variable_redeclaration, def, \
1937ec681f3Smrg                  "Allow GLSL built-in variables to be redeclared verbatim")
1947ec681f3Smrg
1957ec681f3Smrg#define DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(def) \
1967ec681f3Smrg   DRI_CONF_OPT_B(allow_higher_compat_version, def, \
1977ec681f3Smrg                  "Allow a higher compat profile (version 3.1+) for apps that request it")
1987ec681f3Smrg
1997ec681f3Smrg#define DRI_CONF_FORCE_GLSL_ABS_SQRT(def) \
2007ec681f3Smrg   DRI_CONF_OPT_B(force_glsl_abs_sqrt, def,                             \
2017ec681f3Smrg                  "Force computing the absolute value for sqrt() and inversesqrt()")
2027ec681f3Smrg
2037ec681f3Smrg#define DRI_CONF_GLSL_CORRECT_DERIVATIVES_AFTER_DISCARD(def) \
2047ec681f3Smrg   DRI_CONF_OPT_B(glsl_correct_derivatives_after_discard, def, \
2057ec681f3Smrg                  "Implicit and explicit derivatives after a discard behave as if the discard didn't happen")
2067ec681f3Smrg
2077ec681f3Smrg#define DRI_CONF_GLSL_IGNORE_WRITE_TO_READONLY_VAR(def) \
2087ec681f3Smrg   DRI_CONF_OPT_B(glsl_ignore_write_to_readonly_var, def, \
2097ec681f3Smrg                  "Forces the GLSL compiler to ignore writes to readonly vars rather than throwing an error")
2107ec681f3Smrg
2117ec681f3Smrg#define DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH(def) \
2127ec681f3Smrg   DRI_CONF_OPT_B(allow_glsl_cross_stage_interpolation_mismatch, def,   \
2137ec681f3Smrg                  "Allow interpolation qualifier mismatch across shader stages")
2147ec681f3Smrg
2157ec681f3Smrg#define DRI_CONF_ALLOW_DRAW_OUT_OF_ORDER(def) \
2167ec681f3Smrg   DRI_CONF_OPT_B(allow_draw_out_of_order, def, \
2177ec681f3Smrg                  "Allow out-of-order draw optimizations. Set when Z fighting doesn't have to be accurate.")
2187ec681f3Smrg
2197ec681f3Smrg#define DRI_CONF_FORCE_GL_VENDOR() \
2207ec681f3Smrg   DRI_CONF_OPT_S_NODEF(force_gl_vendor, "Override GPU vendor string.")
2217ec681f3Smrg
2227ec681f3Smrg#define DRI_CONF_FORCE_GL_RENDERER() \
2237ec681f3Smrg   DRI_CONF_OPT_S_NODEF(force_gl_renderer, "Override GPU renderer string.")
2247ec681f3Smrg
2257ec681f3Smrg#define DRI_CONF_FORCE_COMPAT_PROFILE(def) \
2267ec681f3Smrg   DRI_CONF_OPT_B(force_compat_profile, def, \
2277ec681f3Smrg                  "Force an OpenGL compatibility context")
2287ec681f3Smrg
2297ec681f3Smrg#define DRI_CONF_OVERRIDE_VRAM_SIZE() \
2307ec681f3Smrg   DRI_CONF_OPT_I(override_vram_size, -1, -1, 2147483647, \
2317ec681f3Smrg                  "Override the VRAM size advertised to the application in MiB (-1 = default)")
2327ec681f3Smrg
2337ec681f3Smrg#define DRI_CONF_FORCE_GL_NAMES_REUSE(def) \
2347ec681f3Smrg   DRI_CONF_OPT_B(force_gl_names_reuse, def, "Force GL names reuse")
2357ec681f3Smrg
2367ec681f3Smrg#define DRI_CONF_TRANSCODE_ETC(def) \
2377ec681f3Smrg   DRI_CONF_OPT_B(transcode_etc, def, "Transcode ETC formats to DXTC if unsupported")
2387ec681f3Smrg
2397ec681f3Smrg#define DRI_CONF_TRANSCODE_ASTC(def) \
2407ec681f3Smrg   DRI_CONF_OPT_B(transcode_astc, def, "Transcode ASTC formats to DXTC if unsupported")
2417ec681f3Smrg
2427ec681f3Smrg#define DRI_CONF_GLX_EXTENSION_OVERRIDE() \
2437ec681f3Smrg   DRI_CONF_OPT_S_NODEF(glx_extension_override, \
2447ec681f3Smrg                  "Allow enabling/disabling a list of GLX extensions")
2457ec681f3Smrg
2467ec681f3Smrg#define DRI_CONF_INDIRECT_GL_EXTENSION_OVERRIDE() \
2477ec681f3Smrg   DRI_CONF_OPT_S_NODEF(indirect_gl_extension_override, \
2487ec681f3Smrg                  "Allow enabling/disabling a list of indirect-GL extensions")
2497ec681f3Smrg
2507ec681f3Smrg#define DRI_CONF_DISABLE_PROTECTED_CONTENT_CHECK(def) \
2517ec681f3Smrg   DRI_CONF_OPT_B(disable_protected_content_check, def, \
2527ec681f3Smrg                  "Don't reject image import if protected_content attribute doesn't match")
2537ec681f3Smrg
2547ec681f3Smrg#define DRI_CONF_IGNORE_MAP_UNSYNCHRONIZED(def) \
2557ec681f3Smrg   DRI_CONF_OPT_B(ignore_map_unsynchronized, def, \
2567ec681f3Smrg                  "Ignore GL_MAP_UNSYNCHRONIZED_BIT, workaround for games that use it incorrectly")
2577ec681f3Smrg
2587ec681f3Smrg/**
2597ec681f3Smrg * \brief Image quality-related options
2607ec681f3Smrg */
2617ec681f3Smrg#define DRI_CONF_SECTION_QUALITY DRI_CONF_SECTION("Image Quality")
2627ec681f3Smrg
2637ec681f3Smrg#define DRI_CONF_PRECISE_TRIG(def) \
2647ec681f3Smrg   DRI_CONF_OPT_B(precise_trig, def, \
2657ec681f3Smrg                  "Prefer accuracy over performance in trig functions")
2667ec681f3Smrg
2677ec681f3Smrg#define DRI_CONF_PP_CELSHADE(def) \
2687ec681f3Smrg   DRI_CONF_OPT_E(pp_celshade, def, 0, 1, \
2697ec681f3Smrg                  "A post-processing filter to cel-shade the output", \
2707ec681f3Smrg                  { 0 } )
2717ec681f3Smrg
2727ec681f3Smrg#define DRI_CONF_PP_NORED(def) \
2737ec681f3Smrg   DRI_CONF_OPT_E(pp_nored, def, 0, 1, \
2747ec681f3Smrg                  "A post-processing filter to remove the red channel", \
2757ec681f3Smrg                  { 0 } )
2767ec681f3Smrg
2777ec681f3Smrg#define DRI_CONF_PP_NOGREEN(def) \
2787ec681f3Smrg   DRI_CONF_OPT_E(pp_nogreen, def, 0, 1, \
2797ec681f3Smrg                  "A post-processing filter to remove the green channel", \
2807ec681f3Smrg                  { 0 } )
2817ec681f3Smrg
2827ec681f3Smrg#define DRI_CONF_PP_NOBLUE(def) \
2837ec681f3Smrg   DRI_CONF_OPT_E(pp_noblue, def, 0, 1, \
2847ec681f3Smrg                  "A post-processing filter to remove the blue channel", \
2857ec681f3Smrg                  { 0 } )
2867ec681f3Smrg
2877ec681f3Smrg#define DRI_CONF_PP_JIMENEZMLAA(def,min,max) \
2887ec681f3Smrg   DRI_CONF_OPT_I(pp_jimenezmlaa, def, min, max, \
2897ec681f3Smrg                  "Morphological anti-aliasing based on Jimenez' MLAA. 0 to disable, 8 for default quality")
2907ec681f3Smrg
2917ec681f3Smrg#define DRI_CONF_PP_JIMENEZMLAA_COLOR(def,min,max) \
2927ec681f3Smrg   DRI_CONF_OPT_I(pp_jimenezmlaa_color, def, min, max, \
2937ec681f3Smrg                  "Morphological anti-aliasing based on Jimenez' MLAA. 0 to disable, 8 for default quality. Color version, usable with 2d GL apps")
2947ec681f3Smrg
2957ec681f3Smrg/**
2967ec681f3Smrg * \brief Performance-related options
2977ec681f3Smrg */
2987ec681f3Smrg#define DRI_CONF_SECTION_PERFORMANCE DRI_CONF_SECTION("Performance")
2997ec681f3Smrg
3007ec681f3Smrg#define DRI_CONF_VBLANK_NEVER 0
3017ec681f3Smrg#define DRI_CONF_VBLANK_DEF_INTERVAL_0 1
3027ec681f3Smrg#define DRI_CONF_VBLANK_DEF_INTERVAL_1 2
3037ec681f3Smrg#define DRI_CONF_VBLANK_ALWAYS_SYNC 3
3047ec681f3Smrg#define DRI_CONF_VBLANK_MODE(def) \
3057ec681f3Smrg   DRI_CONF_OPT_E(vblank_mode, def, 0, 3, \
3067ec681f3Smrg                  "Synchronization with vertical refresh (swap intervals)", \
3077ec681f3Smrg                  DRI_CONF_ENUM(0,"Never synchronize with vertical refresh, ignore application's choice") \
3087ec681f3Smrg                  DRI_CONF_ENUM(1,"Initial swap interval 0, obey application's choice") \
3097ec681f3Smrg                  DRI_CONF_ENUM(2,"Initial swap interval 1, obey application's choice") \
3107ec681f3Smrg                  DRI_CONF_ENUM(3,"Always synchronize with vertical refresh, application chooses the minimum swap interval"))
3117ec681f3Smrg
3127ec681f3Smrg#define DRI_CONF_ADAPTIVE_SYNC(def) \
3137ec681f3Smrg   DRI_CONF_OPT_B(adaptive_sync,def, \
3147ec681f3Smrg                  "Adapt the monitor sync to the application performance (when possible)")
3157ec681f3Smrg
3167ec681f3Smrg#define DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST(def) \
3177ec681f3Smrg   DRI_CONF_OPT_B(vk_wsi_force_bgra8_unorm_first, def, \
3187ec681f3Smrg                  "Force vkGetPhysicalDeviceSurfaceFormatsKHR to return VK_FORMAT_B8G8R8A8_UNORM as the first format")
3197ec681f3Smrg
3207ec681f3Smrg#define DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(def) \
3217ec681f3Smrg   DRI_CONF_OPT_I(vk_x11_override_min_image_count, def, 0, 999, \
3227ec681f3Smrg                  "Override the VkSurfaceCapabilitiesKHR::minImageCount (0 = no override)")
3237ec681f3Smrg
3247ec681f3Smrg#define DRI_CONF_VK_X11_STRICT_IMAGE_COUNT(def) \
3257ec681f3Smrg   DRI_CONF_OPT_B(vk_x11_strict_image_count, def, \
3267ec681f3Smrg                  "Force the X11 WSI to create exactly the number of image specified by the application in VkSwapchainCreateInfoKHR::minImageCount")
3277ec681f3Smrg
3287ec681f3Smrg#define DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT(def) \
3297ec681f3Smrg   DRI_CONF_OPT_B(vk_x11_ensure_min_image_count, def, \
3307ec681f3Smrg                  "Force the X11 WSI to create at least the number of image specified by the driver in VkSurfaceCapabilitiesKHR::minImageCount")
3317ec681f3Smrg
3327ec681f3Smrg#define DRI_CONF_VK_XWAYLAND_WAIT_READY(def) \
3337ec681f3Smrg   DRI_CONF_OPT_B(vk_xwayland_wait_ready, def, \
3347ec681f3Smrg                  "Wait for fences before submitting buffers to Xwayland")
3357ec681f3Smrg
3367ec681f3Smrg#define DRI_CONF_MESA_GLTHREAD(def) \
3377ec681f3Smrg   DRI_CONF_OPT_B(mesa_glthread, def, \
3387ec681f3Smrg                  "Enable offloading GL driver work to a separate thread")
3397ec681f3Smrg
3407ec681f3Smrg#define DRI_CONF_MESA_NO_ERROR(def) \
3417ec681f3Smrg   DRI_CONF_OPT_B(mesa_no_error, def, \
3427ec681f3Smrg                  "Disable GL driver error checking")
3437ec681f3Smrg
3447ec681f3Smrg
3457ec681f3Smrg/**
3467ec681f3Smrg * \brief Miscellaneous configuration options
3477ec681f3Smrg */
3487ec681f3Smrg#define DRI_CONF_SECTION_MISCELLANEOUS DRI_CONF_SECTION("Miscellaneous")
3497ec681f3Smrg
3507ec681f3Smrg#define DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER(def) \
3517ec681f3Smrg   DRI_CONF_OPT_B(always_have_depth_buffer, def, \
3527ec681f3Smrg                  "Create all visuals with a depth buffer")
3537ec681f3Smrg
3547ec681f3Smrg#define DRI_CONF_GLSL_ZERO_INIT(def) \
3557ec681f3Smrg   DRI_CONF_OPT_B(glsl_zero_init, def, \
3567ec681f3Smrg                  "Force uninitialized variables to default to zero")
3577ec681f3Smrg
3587ec681f3Smrg#define DRI_CONF_VS_POSITION_ALWAYS_INVARIANT(def) \
3597ec681f3Smrg   DRI_CONF_OPT_B(vs_position_always_invariant, def, \
3607ec681f3Smrg                  "Force the vertex shader's gl_Position output to be considered 'invariant'")
3617ec681f3Smrg
3627ec681f3Smrg#define DRI_CONF_VS_POSITION_ALWAYS_PRECISE(def) \
3637ec681f3Smrg   DRI_CONF_OPT_B(vs_position_always_precise, def, \
3647ec681f3Smrg                  "Force the vertex shader's gl_Position output to be considered 'precise'")
3657ec681f3Smrg
3667ec681f3Smrg#define DRI_CONF_ALLOW_RGB10_CONFIGS(def) \
3677ec681f3Smrg   DRI_CONF_OPT_B(allow_rgb10_configs, def, \
3687ec681f3Smrg                  "Allow exposure of visuals and fbconfigs with rgb10a2 formats")
3697ec681f3Smrg
3707ec681f3Smrg#define DRI_CONF_ALLOW_RGB565_CONFIGS(def) \
3717ec681f3Smrg   DRI_CONF_OPT_B(allow_rgb565_configs, def, \
3727ec681f3Smrg                  "Allow exposure of visuals and fbconfigs with rgb565 formats")
3737ec681f3Smrg
3747ec681f3Smrg#define DRI_CONF_FORCE_INTEGER_TEX_NEAREST(def) \
3757ec681f3Smrg   DRI_CONF_OPT_B(force_integer_tex_nearest, def, \
3767ec681f3Smrg                  "Force integer textures to use nearest filtering")
3777ec681f3Smrg
3787ec681f3Smrg/**
3797ec681f3Smrg * \brief Initialization configuration options
3807ec681f3Smrg */
3817ec681f3Smrg#define DRI_CONF_SECTION_INITIALIZATION DRI_CONF_SECTION("Initialization")
3827ec681f3Smrg
3837ec681f3Smrg#define DRI_CONF_DEVICE_ID_PATH_TAG() \
3847ec681f3Smrg   DRI_CONF_OPT_S_NODEF(device_id, "Define the graphic device to use if possible")
3857ec681f3Smrg
3867ec681f3Smrg#define DRI_CONF_DRI_DRIVER() \
3877ec681f3Smrg   DRI_CONF_OPT_S_NODEF(dri_driver, "Override the DRI driver to load")
3887ec681f3Smrg
3897ec681f3Smrg/**
3907ec681f3Smrg * \brief Gallium-Nine specific configuration options
3917ec681f3Smrg */
3927ec681f3Smrg
3937ec681f3Smrg#define DRI_CONF_SECTION_NINE DRI_CONF_SECTION("Gallium Nine")
3947ec681f3Smrg
3957ec681f3Smrg#define DRI_CONF_NINE_THROTTLE(def) \
3967ec681f3Smrg   DRI_CONF_OPT_I(throttle_value, def, 0, 0, \
3977ec681f3Smrg                  "Define the throttling value. -1 for no throttling, -2 for default (usually 2), 0 for glfinish behaviour")
3987ec681f3Smrg
3997ec681f3Smrg#define DRI_CONF_NINE_THREADSUBMIT(def) \
4007ec681f3Smrg   DRI_CONF_OPT_B(thread_submit, def, \
4017ec681f3Smrg                  "Use an additional thread to submit buffers.")
4027ec681f3Smrg
4037ec681f3Smrg#define DRI_CONF_NINE_OVERRIDEVENDOR(def) \
4047ec681f3Smrg   DRI_CONF_OPT_I(override_vendorid, def, 0, 0, \
4057ec681f3Smrg                  "Define the vendor_id to report. This allows faking another hardware vendor.")
4067ec681f3Smrg
4077ec681f3Smrg#define DRI_CONF_NINE_ALLOWDISCARDDELAYEDRELEASE(def) \
4087ec681f3Smrg   DRI_CONF_OPT_B(discard_delayed_release, def, \
4097ec681f3Smrg                  "Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).")
4107ec681f3Smrg
4117ec681f3Smrg#define DRI_CONF_NINE_TEARFREEDISCARD(def) \
4127ec681f3Smrg   DRI_CONF_OPT_B(tearfree_discard, def, \
4137ec681f3Smrg                  "Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. true by default.")
4147ec681f3Smrg
4157ec681f3Smrg#define DRI_CONF_NINE_CSMT(def) \
4167ec681f3Smrg   DRI_CONF_OPT_I(csmt_force, def, 0, 0, \
4177ec681f3Smrg                  "If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.")
4187ec681f3Smrg
4197ec681f3Smrg#define DRI_CONF_NINE_DYNAMICTEXTUREWORKAROUND(def) \
4207ec681f3Smrg   DRI_CONF_OPT_B(dynamic_texture_workaround, def, \
4217ec681f3Smrg                  "If set to true, use a ram intermediate buffer for dynamic textures. Increases ram usage, which can cause out of memory issues, but can fix glitches for some games.")
4227ec681f3Smrg
4237ec681f3Smrg#define DRI_CONF_NINE_SHADERINLINECONSTANTS(def) \
4247ec681f3Smrg   DRI_CONF_OPT_B(shader_inline_constants, def, \
4257ec681f3Smrg                  "If set to true, recompile shaders with integer or boolean constants when the values are known. Can cause stutter, but can increase slightly performance.")
4267ec681f3Smrg
4277ec681f3Smrg#define DRI_CONF_NINE_SHMEM_LIMIT() \
4287ec681f3Smrg   DRI_CONF_OPT_I(texture_memory_limit, 128, 0, 0, \
4297ec681f3Smrg                  "In MB the limit of virtual memory used for textures until shmem files are unmapped (default 128MB, 32bits only). If negative disables shmem. Set to a low amount to reduce virtual memory usage, but can incur a small perf hit if too low.")
4307ec681f3Smrg
4317ec681f3Smrg#define DRI_CONF_NINE_FORCESWRENDERINGONCPU(def) \
4327ec681f3Smrg   DRI_CONF_OPT_B(force_sw_rendering_on_cpu, def, \
4337ec681f3Smrg                  "If set to false, emulates software rendering on the requested device, else uses a software renderer.")
4347ec681f3Smrg
4357ec681f3Smrg/**
4367ec681f3Smrg * \brief radeonsi specific configuration options
4377ec681f3Smrg */
4387ec681f3Smrg
4397ec681f3Smrg#define DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(def) \
4407ec681f3Smrg   DRI_CONF_OPT_B(radeonsi_assume_no_z_fights, def, \
4417ec681f3Smrg                  "Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)")
4427ec681f3Smrg
4437ec681f3Smrg#define DRI_CONF_RADEONSI_COMMUTATIVE_BLEND_ADD(def) \
4447ec681f3Smrg   DRI_CONF_OPT_B(radeonsi_commutative_blend_add, def, \
4457ec681f3Smrg                  "Commutative additive blending optimizations (may cause rendering errors)")
4467ec681f3Smrg
4477ec681f3Smrg#define DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS(def) \
4487ec681f3Smrg   DRI_CONF_OPT_B(radeonsi_zerovram, def, \
4497ec681f3Smrg                  "Zero all vram allocations")
4507ec681f3Smrg
4517ec681f3Smrg#define DRI_CONF_V3D_NONMSAA_TEXTURE_SIZE_LIMIT(def) \
4527ec681f3Smrg   DRI_CONF_OPT_B(v3d_nonmsaa_texture_size_limit, def, \
4537ec681f3Smrg                  "Report the non-MSAA-only texture size limit")
4547ec681f3Smrg
4557ec681f3Smrg/**
4567ec681f3Smrg * \brief virgl specific configuration options
4577ec681f3Smrg */
4587ec681f3Smrg
4597ec681f3Smrg#define DRI_CONF_GLES_EMULATE_BGRA(def) \
4607ec681f3Smrg   DRI_CONF_OPT_B(gles_emulate_bgra, def, \
4617ec681f3Smrg                  "On GLES emulate BGRA formats by using a swizzled RGBA format")
4627ec681f3Smrg
4637ec681f3Smrg#define DRI_CONF_GLES_APPLY_BGRA_DEST_SWIZZLE(def) \
4647ec681f3Smrg   DRI_CONF_OPT_B(gles_apply_bgra_dest_swizzle, def, \
4657ec681f3Smrg                  "When the BGRA formats are emulated by using swizzled RGBA formats on GLES apply the swizzle when writing")
4667ec681f3Smrg
4677ec681f3Smrg#define DRI_CONF_GLES_SAMPLES_PASSED_VALUE(def, minimum, maximum) \
4687ec681f3Smrg   DRI_CONF_OPT_I(gles_samples_passed_value, def, minimum, maximum, \
4697ec681f3Smrg                  "GL_SAMPLES_PASSED value when emulated by GL_ANY_SAMPLES_PASSED")
4707ec681f3Smrg
4717ec681f3Smrg/**
4727ec681f3Smrg * \brief RADV specific configuration options
4737ec681f3Smrg */
4747ec681f3Smrg
4757ec681f3Smrg#define DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING(def) \
4767ec681f3Smrg   DRI_CONF_OPT_B(radv_report_llvm9_version_string, def, \
4777ec681f3Smrg                  "Report LLVM 9.0.1 for games that apply shader workarounds if missing (for ACO only)")
4787ec681f3Smrg
4797ec681f3Smrg#define DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP(def) \
4807ec681f3Smrg   DRI_CONF_OPT_B(radv_enable_mrt_output_nan_fixup, def, \
4817ec681f3Smrg                  "Replace NaN outputs from fragment shaders with zeroes for floating point render target")
4827ec681f3Smrg
4837ec681f3Smrg#define DRI_CONF_RADV_NO_DYNAMIC_BOUNDS(def) \
4847ec681f3Smrg   DRI_CONF_OPT_B(radv_no_dynamic_bounds, def, \
4857ec681f3Smrg                  "Disabling bounds checking for dynamic buffer descriptors")
4867ec681f3Smrg
4877ec681f3Smrg#define DRI_CONF_RADV_DISABLE_SHRINK_IMAGE_STORE(def) \
4887ec681f3Smrg   DRI_CONF_OPT_B(radv_disable_shrink_image_store, def, \
4897ec681f3Smrg                  "Disabling shrinking of image stores based on the format")
4907ec681f3Smrg
4917ec681f3Smrg#define DRI_CONF_RADV_ABSOLUTE_DEPTH_BIAS(def) \
4927ec681f3Smrg   DRI_CONF_OPT_B(radv_absolute_depth_bias, def, \
4937ec681f3Smrg                  "Consider depthBiasConstantFactor an absolute depth bias (like D3D9)")
4947ec681f3Smrg
4957ec681f3Smrg#define DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(def) \
4967ec681f3Smrg   DRI_CONF_OPT_I(radv_override_uniform_offset_alignment, def, 0, 128, \
4977ec681f3Smrg                  "Override the minUniformBufferOffsetAlignment exposed to the application. (0 = default)")
4987ec681f3Smrg
4997ec681f3Smrg#define DRI_CONF_RADV_ZERO_VRAM(def) \
5007ec681f3Smrg   DRI_CONF_OPT_B(radv_zero_vram, def, \
5017ec681f3Smrg                  "Initialize to zero all VRAM allocations")
5027ec681f3Smrg
5037ec681f3Smrg#define DRI_CONF_RADV_LOWER_DISCARD_TO_DEMOTE(def) \
5047ec681f3Smrg   DRI_CONF_OPT_B(radv_lower_discard_to_demote, def, \
5057ec681f3Smrg                  "Lower discard instructions to demote")
5067ec681f3Smrg
5077ec681f3Smrg#define DRI_CONF_RADV_INVARIANT_GEOM(def) \
5087ec681f3Smrg   DRI_CONF_OPT_B(radv_invariant_geom, def, \
5097ec681f3Smrg                  "Mark geometry-affecting outputs as invariant")
5107ec681f3Smrg
5117ec681f3Smrg#define DRI_CONF_RADV_DISABLE_TC_COMPAT_HTILE_GENERAL(def) \
5127ec681f3Smrg   DRI_CONF_OPT_B(radv_disable_tc_compat_htile_general, def, \
5137ec681f3Smrg                  "Disable TC-compat HTILE in GENERAL layout")
5147ec681f3Smrg
5157ec681f3Smrg#define DRI_CONF_RADV_DISABLE_DCC(def) \
5167ec681f3Smrg   DRI_CONF_OPT_B(radv_disable_dcc, def, \
5177ec681f3Smrg                  "Disable DCC for color images")
5187ec681f3Smrg
5197ec681f3Smrg#define DRI_CONF_RADV_REPORT_APU_AS_DGPU(def) \
5207ec681f3Smrg   DRI_CONF_OPT_B(radv_report_apu_as_dgpu, def, \
5217ec681f3Smrg                  "Report APUs as discrete GPUs instead of integrated GPUs")
5227ec681f3Smrg
5237ec681f3Smrg#define DRI_CONF_RADV_DISABLE_HTILE_LAYERS(def) \
5247ec681f3Smrg   DRI_CONF_OPT_B(radv_disable_htile_layers, def, \
5257ec681f3Smrg                  "Disable HTILE for layered depth/stencil formats")
5267ec681f3Smrg
5277ec681f3Smrg#endif
528