1#ifndef _KGSL_DRM_H_
2#define _KGSL_DRM_H_
3
4#include "drm.h"
5
6#define DRM_KGSL_GEM_CREATE 0x00
7#define DRM_KGSL_GEM_PREP   0x01
8#define DRM_KGSL_GEM_SETMEMTYPE 0x02
9#define DRM_KGSL_GEM_GETMEMTYPE 0x03
10#define DRM_KGSL_GEM_MMAP 0x04
11#define DRM_KGSL_GEM_ALLOC 0x05
12#define DRM_KGSL_GEM_BIND_GPU 0x06
13#define DRM_KGSL_GEM_UNBIND_GPU 0x07
14
15#define DRM_KGSL_GEM_GET_BUFINFO 0x08
16#define DRM_KGSL_GEM_SET_BUFCOUNT 0x09
17#define DRM_KGSL_GEM_SET_ACTIVE 0x0A
18#define DRM_KGSL_GEM_LOCK_HANDLE 0x0B
19#define DRM_KGSL_GEM_UNLOCK_HANDLE 0x0C
20#define DRM_KGSL_GEM_UNLOCK_ON_TS 0x0D
21#define DRM_KGSL_GEM_CREATE_FD 0x0E
22
23#define DRM_IOCTL_KGSL_GEM_CREATE \
24DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE, struct drm_kgsl_gem_create)
25
26#define DRM_IOCTL_KGSL_GEM_PREP \
27DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_PREP, struct drm_kgsl_gem_prep)
28
29#define DRM_IOCTL_KGSL_GEM_SETMEMTYPE \
30DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SETMEMTYPE, \
31struct drm_kgsl_gem_memtype)
32
33#define DRM_IOCTL_KGSL_GEM_GETMEMTYPE \
34DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GETMEMTYPE, \
35struct drm_kgsl_gem_memtype)
36
37#define DRM_IOCTL_KGSL_GEM_MMAP \
38DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_MMAP, struct drm_kgsl_gem_mmap)
39
40#define DRM_IOCTL_KGSL_GEM_ALLOC \
41DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_ALLOC, struct drm_kgsl_gem_alloc)
42
43#define DRM_IOCTL_KGSL_GEM_BIND_GPU \
44DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_BIND_GPU, struct drm_kgsl_gem_bind_gpu)
45
46#define DRM_IOCTL_KGSL_GEM_UNBIND_GPU \
47DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNBIND_GPU, \
48struct drm_kgsl_gem_bind_gpu)
49
50#define DRM_IOCTL_KGSL_GEM_GET_BUFINFO \
51DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_BUFINFO, \
52	 struct drm_kgsl_gem_bufinfo)
53
54#define DRM_IOCTL_KGSL_GEM_SET_BUFCOUNT \
55DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_BUFCOUNT, \
56	 struct drm_kgsl_gem_bufcount)
57
58#define DRM_IOCTL_KGSL_GEM_SET_ACTIVE \
59DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_ACTIVE, \
60	 struct drm_kgsl_gem_active)
61
62#define DRM_IOCTL_KGSL_GEM_LOCK_HANDLE \
63DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_LOCK_HANDLE, \
64struct drm_kgsl_gem_lock_handles)
65
66#define DRM_IOCTL_KGSL_GEM_UNLOCK_HANDLE \
67DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_HANDLE, \
68struct drm_kgsl_gem_unlock_handles)
69
70#define DRM_IOCTL_KGSL_GEM_UNLOCK_ON_TS \
71DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_ON_TS, \
72struct drm_kgsl_gem_unlock_on_ts)
73
74#define DRM_IOCTL_KGSL_GEM_CREATE_FD \
75DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE_FD, \
76struct drm_kgsl_gem_create_fd)
77
78/* Maximum number of sub buffers per GEM object */
79#define DRM_KGSL_GEM_MAX_BUFFERS 2
80
81/* Memory types - these define the source and caching policies
82   of the GEM memory chunk */
83
84/* Legacy definitions left for compatibility */
85
86#define DRM_KGSL_GEM_TYPE_EBI          0
87#define DRM_KGSL_GEM_TYPE_SMI          1
88#define DRM_KGSL_GEM_TYPE_KMEM         2
89#define DRM_KGSL_GEM_TYPE_KMEM_NOCACHE 3
90#define DRM_KGSL_GEM_TYPE_MEM_MASK     0xF
91
92/* Contiguous memory (PMEM) */
93#define DRM_KGSL_GEM_TYPE_PMEM       0x000100
94
95/* PMEM memory types */
96#define DRM_KGSL_GEM_PMEM_EBI        0x001000
97#define DRM_KGSL_GEM_PMEM_SMI        0x002000
98
99/* Standard paged memory */
100#define DRM_KGSL_GEM_TYPE_MEM        0x010000
101
102/* Caching controls */
103#define DRM_KGSL_GEM_CACHE_NONE      0x000000
104#define DRM_KGSL_GEM_CACHE_WCOMBINE  0x100000
105#define DRM_KGSL_GEM_CACHE_WTHROUGH  0x200000
106#define DRM_KGSL_GEM_CACHE_WBACK     0x400000
107#define DRM_KGSL_GEM_CACHE_WBACKWA   0x800000
108#define DRM_KGSL_GEM_CACHE_MASK      0xF00000
109
110/* FD based objects */
111#define DRM_KGSL_GEM_TYPE_FD_FBMEM   0x1000000
112#define DRM_KGSL_GEM_TYPE_FD_MASK    0xF000000
113
114/* Timestamp types */
115#define DRM_KGSL_GEM_TS_3D         0x00000430
116#define DRM_KGSL_GEM_TS_2D         0x00000180
117
118
119struct drm_kgsl_gem_create {
120	uint32_t size;
121	uint32_t handle;
122};
123
124struct drm_kgsl_gem_prep {
125	uint32_t handle;
126	uint32_t phys;
127	uint64_t offset;
128};
129
130struct drm_kgsl_gem_memtype {
131	uint32_t handle;
132	uint32_t type;
133};
134
135struct drm_kgsl_gem_mmap {
136	uint32_t handle;
137	uint32_t size;
138	uint32_t hostptr;
139	uint64_t offset;
140};
141
142struct drm_kgsl_gem_alloc {
143	uint32_t handle;
144	uint64_t offset;
145};
146
147struct drm_kgsl_gem_bind_gpu {
148	uint32_t handle;
149	uint32_t gpuptr;
150};
151
152struct drm_kgsl_gem_bufinfo {
153	uint32_t handle;
154	uint32_t count;
155	uint32_t active;
156	uint32_t offset[DRM_KGSL_GEM_MAX_BUFFERS];
157	uint32_t gpuaddr[DRM_KGSL_GEM_MAX_BUFFERS];
158};
159
160struct drm_kgsl_gem_bufcount {
161	uint32_t handle;
162	uint32_t bufcount;
163};
164
165struct drm_kgsl_gem_active {
166	uint32_t handle;
167	uint32_t active;
168};
169
170struct drm_kgsl_gem_lock_handles {
171	uint32_t num_handles;
172	uint32_t *handle_list;
173	uint32_t pid;
174	uint32_t lock_id;	  /* Returned lock id used for unlocking */
175};
176
177struct drm_kgsl_gem_unlock_handles {
178	uint32_t lock_id;
179};
180
181struct drm_kgsl_gem_unlock_on_ts {
182	uint32_t lock_id;
183	uint32_t timestamp;	 /* This field is a hw generated ts */
184	uint32_t type;		 /* Which pipe to check for ts generation */
185};
186
187struct drm_kgsl_gem_create_fd {
188	uint32_t fd;
189	uint32_t handle;
190};
191
192#endif
193