1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#ifndef _shader_code_gfx11_h_ 25#define _shader_code_gfx11_h_ 26 27static const uint32_t bufferclear_cs_shader_gfx11[] = { 28 0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF, 29 0x7E020205, 0x7E040206, 0x7E060207, 0xBF870004, 30 0xD6460004, 0x04010C08, 0x7E000204, 0xE01C0000, 31 0x80800004, 0xBFB60003, 0xBFB00000, 0xBF9F0000, 32 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 33 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 34 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 35 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 36 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 37 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 38 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 39 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 40 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 41 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 42 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 43 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 44 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 45 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 46 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 47 0xBF9F0000, 0xBF9F0000, 0xBF9F0000 48}; 49 50static const struct reg_info bufferclear_cs_shader_registers_gfx11[] = { 51 {0x2e12, 0x600C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x600C0041 }, 52 {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 }, 53 {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 }, 54 {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 }, 55 {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 } 56}; 57 58static const uint32_t buffercopy_cs_shader_gfx11[] = { 59 0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF, 60 0xBF870001, 0xD6460001, 0x04010C08, 0xE00C0000, 61 0x80800201, 0xBF8903F7, 0xE01C0000, 0x80810201, 62 0xBFB60003, 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 63 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 64 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 65 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 66 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 67 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 68 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 69 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 70 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 71 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 72 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 73 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 74 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 75 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 76 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 77 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 78 0xBF9F0000, 0xBF9F0000 79}; 80 81static const uint32_t ps_const_shader_gfx11[] = { 82 0xB0802006, 0xBF840003, 0x7E000200, 0x7E020201, 83 0x7E040202, 0x7E060203, 0x5E000300, 0x5E020702, 84 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100, 85 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 86 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 87 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 88 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 89 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 90 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 91 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 92 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 93 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 94 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 95 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 96 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 97 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 98 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 99 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 100 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 101 0xBF9F0000 102}; 103 104#define ps_const_shader_patchinfo_code_size_gfx11 6 105 106static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = { 107 {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO 108 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 }, // SI_EXPORT_FMT_32_R 109 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_32_GR 110 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 }, // SI_EXPORT_FMT_32_AR 111 { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_FP16_ABGR 112 { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_UNORM16_ABGR 113 { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SNORM16_ABGR 114 { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_uint32_t16_ABGR 115 { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SINT16_ABGR 116 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 } // SI_EXPORT_FMT_32_ABGR 117 } 118}; 119 120static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = { 121 0x00000006 122}; 123 124#define ps_const_num_sh_registers_gfx11 2 125 126static const struct reg_info ps_const_sh_registers_gfx11[] = { 127 {0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 }, 128 {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } 129}; 130 131static const struct reg_info ps_const_context_registers_gfx11[] = { 132 {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, 133 {0xA1B6, 0x00000000 }, //{ mmSPI_PS_IN_CONTROL, 0x00000000 }, 134 {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK, 0x0000000F }, 135 {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL, 0x00000010 }, 136 {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, 137 {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, 138 {0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } 139}; 140 141#define ps_const_num_context_registers_gfx11 7 142 143static const uint32_t ps_tex_shader_gfx11[] = 144{ 145 0xB0802006, 0xBF840003, 0xBEFD000C, 0xBE8E017E, 146 0xBEFE1D7E, 0xCE000003, 0xCE000102, 0xCD000104, 147 0x040E0103, 0xCD000000, 0x040A0102, 0xBF870112, 148 0xCD010703, 0x04120303, 0xCD010700, 0x04020302, 149 0x8BFE0E7E, 0xF06C0F05, 0x08000003, 0x00000000, 150 0xBEFE010E, 0xBF8903F7, 0x5E000300, 0x5E020702, 151 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100, 152 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 153 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 154 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 155 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 156 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 157 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 158 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 159 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 160 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 161 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 162 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 163 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 164 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 165 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 166 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 167 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 168 0xBF9F0000 169}; 170 171static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] = 172{ 173 0x00000016 174}; 175 176// Denotes the Patch Info Code Length 177#define ps_tex_shader_patchinfo_code_size_gfx11 6 178 179static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] = 180{ 181 {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO 182 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 }, // SI_EXPORT_FMT_32_R 183 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_32_GR 184 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 }, // SI_EXPORT_FMT_32_AR 185 { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_FP16_ABGR 186 { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_UNORM16_ABGR 187 { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SNORM16_ABGR 188 { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_uint32_t16_ABGR 189 { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SINT16_ABGR 190 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 } // SI_EXPORT_FMT_32_ABGR 191 } 192}; 193// Holds Sh Register Information 194static const struct reg_info ps_tex_sh_registers_gfx11[] = 195{ 196 {0x2C0A, 0x020C0081 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0081 }, 197 {0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 } 198}; 199 200#define ps_tex_num_sh_registers_gfx11 2 201 202// Holds Context Register Information 203static const struct reg_info ps_tex_context_registers_gfx11[] = 204{ 205 {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, 206 {0xA1B6, 0x00000001 }, //{ mmSPI_PS_IN_CONTROL, 0x00000001 }, 207 {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK, 0x0000000F }, 208 {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL, 0x00000010 }, 209 {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, 210 {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, 211 {0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } 212}; 213 214#define ps_tex_num_context_registers_gfx11 7 215 216static const uint32_t vs_RectPosTexFast_shader_gfx11[] = 217{ 218 0xB0802006, 0xBEFE01C1, 0xBF840003, 0xF408050A, 219 0xF80000B0, 0xD71F0001, 0x000100C1, 0x9300FF03, 220 0x00040018, 0x9301FF02, 0x0009000C, 0xBF870091, 221 0xD7200001, 0x000202C1, 0xD60B0001, 0x04058000, 222 0xBF870001, 0xD4490000, 0x00000301, 0xBE862100, 223 0x7E040B05, 0xBFA5001C, 0x7E06020A, 0x7E08020E, 224 0x7E0A020F, 0xBF8701B4, 0x060404F3, 0x7E140211, 225 0x7E0E0210, 0x7C240480, 0x060404F3, 0xD5010003, 226 0x01AA0608, 0xD5010004, 0x01AA080C, 0xBF870003, 227 0xD4120012, 0x00010102, 0x7E04020B, 0xBEEA1F12, 228 0xBF870483, 0xD5010008, 0x01AA080C, 0xD5010006, 229 0x01AA0608, 0xBF870003, 0xD5010004, 0x004A0409, 230 0xD5010009, 0x004A0A0D, 0xBEFE0106, 0x9302FF02, 231 0x00090016, 0xBF870009, 0xD4C9007E, 0x00000501, 232 0xBFA50002, 0xF8000941, 0x00000000, 0xBF89FFF0, 233 0x8BFE0006, 0xD71F0000, 0x000100C1, 0xBFA50013, 234 0x7E1602F2, 0x9300FF03, 0x00040018, 0x8B01FF05, 235 0x00007FFF, 0xBF8704B2, 0xD7200000, 0x000200C1, 236 0x7E0202F2, 0x84018901, 0x80018001, 0xBF870002, 237 0xD60B0000, 0x04018000, 0xF80008CF, 0x01070406, 238 0xBF89FC07, 0xE0744000, 0x01850800, 0xBFB00000, 239 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 240 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 241 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 242 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 243 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 244 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 245 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 246 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 247 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 248 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 249 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 250 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 251 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 252 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 253 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 254 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000 255}; 256 257static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] = 258{ 259 {0x2C8A, 0x020C00C2}, //{ mmSPI_SHADER_PGM_RSRC1_GS, 0x020C00C2 }, 260 {0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C } 261}; 262 263#define vs_RectPosTexFast_num_sh_registers_gfx11 2 264 265// Holds Context Register Information 266static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] = 267{ 268 {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 }, 269 {0xA1C2, 0x00000001}, //{ mmSPI_SHADER_IDX_FORMAT, 0x00000001 }, 270 {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}, 271 {0xA2E4, 0x00000000}, //{ mmVGT_GS_INSTANCE_CNT, 0x00000000 }, 272 {0xA2AB, 0x00000004}, //{ mmVGT_ESGS_RING_ITEMSIZE, 0x00000004 }, 273 {0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 } 274}; 275 276#define vs_RectPosTexFast_num_context_registers_gfx11 6 277 278static const uint32_t preamblecache_gfx11[] = { 279 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, 280 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, 281 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, 0xc0016900, 0x208, 0x0, 282 0xc0016900, 0x2a1, 0x0, 0xc0016900, 0x2ad, 0x0, 0xc0016900, 0x2dc, 0x0, 283 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 284 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 285 0xc0046900, 0x310, 0x0, 0x3, 0x0, 0x100000, 0xc0016900, 0x349, 0x0, 286 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, 0xc0016900, 0x376, 0x0, 287 0xc0016900, 0x385, 0x0, 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 288 0xc0026900, 0x204, 0x90000, 0x4, 0xc0016900, 0x20c, 0x0, 0xc0026900, 0x20e, 0x0, 0x0, 289 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, 290 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0x0, 0xc0016900, 0x2a6, 0x0, 291 0xc0016900, 0x210, 0x0, 0xc0016900, 0x2db, 0x0, 0xc0016900, 0x2e4, 0x0, 292 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x0, 0xc0016900, 0x206, 0x300, 293 0xc0016900, 0x212, 0x200, 0xc0016900, 0xf4, 0x0, 0xc0016900, 0x18, 0x0, 294 0xc0016900, 0x1d4, 0xff, 0xc0016900, 0x2ce, 0x1, 0xc0016900, 0x2d3, 0x20001, 295 0xc0016900, 0x1ff, 0x80, 0xc0016900, 0x2d5, 0x6012010, 0xc0017a00, 0x20000243, 0x0, 296 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0, 0xc0017900, 0x24b, 0x0, 297 0xc0017900, 0x259, 0xffffffff, 0xc0017900, 0x25f, 0x0, 0xc0017900, 0x260, 0x0, 298 0xc0017900, 0x262, 0x0, 0xc0017900, 0x444, 0x0, 0xc0017900, 0x445, 0x0, 299 0xc0017600, 0x6, 0x0, 0xc0017600, 0x80, 0x0, 0xc0017600, 0xb0, 0x0, 300 0xc0047600, 0xb2, 0x0, 0x0, 0x0, 0x0, 0xc0017600, 0x30, 0x0, 301 0xc0047600, 0x32, 0x0, 0x0, 0x0, 0x0 302}; 303 304static const uint32_t cached_cmd_gfx11[] = { 305 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, 306 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, 307 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, 308 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x0, 309 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, 310 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, 311 0xc0026900, 0x292, 0x20, 0x6020000, 312 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0, 313 0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005, 314 0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4 315}; 316 317#define sh_reg_base_gfx11 0x2C00 318#define context_reg_base_gfx11 0xA000 319 320#endif 321