1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22*/
23
24#ifndef _shader_code_gfx9_h_
25#define _shader_code_gfx9_h_
26
27static const uint32_t bufferclear_cs_shader_gfx9[] = {
28	0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
29	0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206,
30	0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000,
31	0xbf810000
32};
33
34static const struct reg_info bufferclear_cs_shader_registers_gfx9[] = {
35	{0x2e12, 0x000C0041},	//{ mmCOMPUTE_PGM_RSRC1,	  0x000C0041 },
36	{0x2e13, 0x00000090},	//{ mmCOMPUTE_PGM_RSRC2,	  0x00000090 },
37	{0x2e07, 0x00000040},	//{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
38	{0x2e08, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
39	{0x2e09, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
40};
41
42static const uint32_t buffercopy_cs_shader_gfx9[] = {
43	0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
44	0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70,
45	0xe01c2000, 0x80010200, 0xbf810000
46};
47
48static const uint32_t ps_const_shader_gfx9[] = {
49	0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
50	0xD2960000, 0x00020300, 0xD2960001, 0x00020702,
51	0xC4001C0F, 0x00000100, 0xBF810000
52};
53
54#define ps_const_shader_patchinfo_code_size_gfx9 6
55
56static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
57    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
58     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 },
59     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 },
60     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 },
61     { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 },
62     { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 },
63     { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 },
64     { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 },
65     { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 },
66     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 }
67    }
68};
69
70static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
71	0x00000004
72};
73
74#define ps_const_num_sh_registers_gfx9 2
75
76static const struct reg_info ps_const_sh_registers_gfx9[] = {
77	{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
78	{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
79};
80
81#define ps_const_num_context_registers_gfx9 7
82
83static const struct reg_info ps_const_context_registers_gfx9[] = {
84    {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
85    {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL,       0x00000000 },
86    {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK,          0x0000000F },
87    {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL,       0x00000010 },
88    {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
89    {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
90    {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 }
91};
92
93static const uint32_t ps_tex_shader_gfx9[] = {
94    0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
95    0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
96    0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000,
97    0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F,
98    0x00000100, 0xBF810000
99};
100
101static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
102    0x0000000B
103};
104
105#define ps_tex_shader_patchinfo_code_size_gfx9 6
106
107static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
108    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
109     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 },
110     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 },
111     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 },
112     { 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 },
113     { 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 },
114     { 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 },
115     { 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 },
116     { 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 },
117     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 }
118    }
119};
120
121#define ps_tex_num_sh_registers_gfx9 2
122
123static const struct reg_info ps_tex_sh_registers_gfx9[] = {
124    {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
125    {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
126};
127
128#define ps_tex_num_context_registers_gfx9 7
129
130static const struct reg_info ps_tex_context_registers_gfx9[] = {
131    {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
132    {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL,       0x00000001 },
133    {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK,          0x0000000F },
134    {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL,       0x00000010 },
135    {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
136    {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
137    {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004  }
138};
139
140static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
141    0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
142    0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
143    0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080,
144    0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003,
145    0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101,
146    0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903,
147    0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100,
148    0xC400020F, 0x05060403, 0xBF810000
149};
150
151static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
152{
153    {0x2C4A, 0x000C0081}, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x000C0081 },
154    {0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
155};
156
157#define vs_RectPosTexFast_num_sh_registers_gfx9 2
158
159// Holds Context Register Information
160static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
161{
162    {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
163    {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
164};
165
166#define vs_RectPosTexFast_num_context_registers_gfx9 2
167
168static const uint32_t preamblecache_gfx9[] = {
169	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
170	0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
171	0xc0026900, 0xb4,  0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
172	0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
173	0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
174	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
175	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
176	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
177	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
178	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
179	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
180	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
181	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
182	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
183	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
184	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
185	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
186	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
187	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
188	0xc0017900, 0x24b, 0x0
189};
190
191static const uint32_t cached_cmd_gfx9[] = {
192	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
193	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
194	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
195	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
196	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
197	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
198	0xc0026900, 0x292, 0x20, 0x60201b8,
199	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
200};
201
202#define sh_reg_base_gfx9 0x2C00
203#define context_reg_base_gfx9 0xA000
204
205#endif
206