1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Alex Deucher <alexander.deucher@amd.com>
24 *
25 */
26#ifdef HAVE_CONFIG_H
27#include "config.h"
28#endif
29
30#include "xf86.h"
31
32#include <errno.h>
33
34#include "radeon.h"
35#include "radeon_reg.h"
36#include "cayman_reg.h"
37#include "evergreen_state.h"
38
39#include "radeon_vbo.h"
40#include "radeon_exa_shared.h"
41
42/*
43 * Setup of default state
44 */
45
46void
47cayman_set_default_state(ScrnInfoPtr pScrn)
48{
49    tex_resource_t tex_res;
50    shader_config_t fs_conf;
51    int i;
52    RADEONInfoPtr info = RADEONPTR(pScrn);
53    struct radeon_accel_state *accel_state = info->accel_state;
54
55    if (accel_state->XInited3D)
56	return;
57
58    memset(&tex_res, 0, sizeof(tex_resource_t));
59    memset(&fs_conf, 0, sizeof(shader_config_t));
60
61    accel_state->XInited3D = TRUE;
62
63    evergreen_start_3d(pScrn);
64
65    BEGIN_BATCH(21);
66    EREG(SQ_LDS_ALLOC_PS, 0);
67
68    PACK0(SQ_ESGS_RING_ITEMSIZE, 6);
69    E32(0);
70    E32(0);
71    E32(0);
72    E32(0);
73    E32(0);
74    E32(0);
75
76    PACK0(SQ_GS_VERT_ITEMSIZE, 4);
77    E32(0);
78    E32(0);
79    E32(0);
80    E32(0);
81
82    PACK0(SQ_VTX_BASE_VTX_LOC, 2);
83    E32(0);
84    E32(0);
85    END_BATCH();
86
87    /* DB */
88    BEGIN_BATCH(3 + 2);
89    EREG(DB_Z_INFO,                           0);
90    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
91    END_BATCH();
92
93    BEGIN_BATCH(3 + 2);
94    EREG(DB_STENCIL_INFO,                     0);
95    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
96    END_BATCH();
97
98    BEGIN_BATCH(3 + 2);
99    EREG(DB_HTILE_DATA_BASE,                    0);
100    RELOC_BATCH(accel_state->shaders_bo, RADEON_GEM_DOMAIN_VRAM, 0);
101    END_BATCH();
102
103    BEGIN_BATCH(52);
104    EREG(DB_DEPTH_INFO,                       0);
105    EREG(DB_DEPTH_CONTROL,                    0);
106
107    PACK0(PA_SC_VPORT_ZMIN_0, 2);
108    EFLOAT(0.0); // PA_SC_VPORT_ZMIN_0
109    EFLOAT(1.0); // PA_SC_VPORT_ZMAX_0
110
111    PACK0(DB_RENDER_CONTROL, 5);
112    E32(STENCIL_COMPRESS_DISABLE_bit | DEPTH_COMPRESS_DISABLE_bit); // DB_RENDER_CONTROL
113    E32(0); // DB_COUNT_CONTROL
114    E32(0); // DB_DEPTH_VIEW
115    E32(0x2a); // DB_RENDER_OVERRIDE
116    E32(0); // DB_RENDER_OVERRIDE2
117
118    PACK0(DB_STENCIL_CLEAR, 2);
119    E32(0); // DB_STENCIL_CLEAR
120    E32(0); // DB_DEPTH_CLEAR
121
122    EREG(DB_ALPHA_TO_MASK,                    ((2 << ALPHA_TO_MASK_OFFSET0_shift)	|
123					       (2 << ALPHA_TO_MASK_OFFSET1_shift)	|
124					       (2 << ALPHA_TO_MASK_OFFSET2_shift)	|
125					       (2 << ALPHA_TO_MASK_OFFSET3_shift)));
126
127    EREG(DB_SHADER_CONTROL, ((EARLY_Z_THEN_LATE_Z << Z_ORDER_shift) |
128			     DUAL_EXPORT_ENABLE_bit)); /* Only useful if no depth export */
129
130    // SX
131    EREG(SX_MISC,               0);
132
133    // CB
134    PACK0(SX_ALPHA_TEST_CONTROL, 5);
135    E32(0); // SX_ALPHA_TEST_CONTROL
136    E32(0x00000000); //CB_BLEND_RED
137    E32(0x00000000); //CB_BLEND_GREEN
138    E32(0x00000000); //CB_BLEND_BLUE
139    E32(0x00000000); //CB_BLEND_ALPHA
140
141    EREG(CB_SHADER_MASK,                      OUTPUT0_ENABLE_mask);
142
143    // SC
144    EREG(PA_SC_WINDOW_OFFSET,                 ((0 << WINDOW_X_OFFSET_shift) |
145					       (0 << WINDOW_Y_OFFSET_shift)));
146    EREG(PA_SC_CLIPRECT_RULE,                 CLIP_RULE_mask);
147    EREG(PA_SC_EDGERULE,             0xAAAAAAAA);
148    EREG(PA_SU_HARDWARE_SCREEN_OFFSET, 0);
149    END_BATCH();
150
151    /* clip boolean is set to always visible -> doesn't matter */
152    for (i = 0; i < PA_SC_CLIPRECT_0_TL_num; i++)
153	evergreen_set_clip_rect (pScrn, i, 0, 0, 8192, 8192);
154
155    for (i = 0; i < PA_SC_VPORT_SCISSOR_0_TL_num; i++)
156	evergreen_set_vport_scissor (pScrn, i, 0, 0, 8192, 8192);
157
158    BEGIN_BATCH(73);
159    PACK0(PA_SC_MODE_CNTL_0, 2);
160    E32(0); // PA_SC_MODE_CNTL_0
161    E32(0); // PA_SC_MODE_CNTL_1
162
163    PACK0(PA_SC_CENTROID_PRIORITY_0, 27);
164    E32((0 << DISTANCE_0_shift) |
165	(1 << DISTANCE_1_shift) |
166	(2 << DISTANCE_2_shift) |
167	(3 << DISTANCE_3_shift) |
168	(4 << DISTANCE_4_shift) |
169	(5 << DISTANCE_5_shift) |
170	(6 << DISTANCE_6_shift) |
171	(7 << DISTANCE_7_shift)); // PA_SC_CENTROID_PRIORITY_0
172    E32((8 << DISTANCE_8_shift) |
173	(9 << DISTANCE_9_shift) |
174	(10 << DISTANCE_10_shift) |
175	(11 << DISTANCE_11_shift) |
176	(12 << DISTANCE_12_shift) |
177	(13 << DISTANCE_13_shift) |
178	(14 << DISTANCE_14_shift) |
179	(15 << DISTANCE_15_shift)); // PA_SC_CENTROID_PRIORITY_1
180    E32(0); // PA_SC_LINE_CNTL
181    E32(0); // PA_SC_AA_CONFIG
182    E32(((X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
183	 PIX_CENTER_bit)); // PA_SU_VTX_CNTL
184    EFLOAT(1.0);						// PA_CL_GB_VERT_CLIP_ADJ
185    EFLOAT(1.0);						// PA_CL_GB_VERT_DISC_ADJ
186    EFLOAT(1.0);						// PA_CL_GB_HORZ_CLIP_ADJ
187    EFLOAT(1.0);						// PA_CL_GB_HORZ_DISC_ADJ
188    E32(0); // PA_SC_AA_SAMPLE_LOCS_PIXEL_*
189    E32(0);
190    E32(0);
191    E32(0);
192    E32(0);
193    E32(0);
194    E32(0);
195    E32(0);
196    E32(0);
197    E32(0);
198    E32(0);
199    E32(0);
200    E32(0);
201    E32(0);
202    E32(0);
203    E32(0); // PA_SC_AA_SAMPLE_LOCS__PIXEL_*
204    E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
205    E32(0xFFFFFFFF); // PA_SC_AA_MASK_*
206
207    // CL
208    PACK0(PA_CL_CLIP_CNTL, 8);
209    E32(CLIP_DISABLE_bit); // PA_CL_CLIP_CNTL
210    E32(FACE_bit); // PA_SU_SC_MODE_CNTL
211    E32(VTX_XY_FMT_bit); // PA_CL_VTE_CNTL
212    E32(0); // PA_CL_VS_OUT_CNTL
213    E32(0); // PA_CL_NANINF_CNTL
214    E32(0); // PA_SU_LINE_STIPPLE_CNTL
215    E32(0); // PA_SU_LINE_STIPPLE_SCALE
216    E32(0); // PA_SU_PRIM_FILTER_CNTL
217
218    // SU
219    PACK0(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
220    E32(0);
221    E32(0);
222    E32(0);
223    E32(0);
224    E32(0);
225    E32(0);
226
227    /* src = semantic id 0; mask = semantic id 1 */
228    EREG(SPI_VS_OUT_ID_0, ((0 << SEMANTIC_0_shift) |
229			   (1 << SEMANTIC_1_shift)));
230    PACK0(SPI_PS_INPUT_CNTL_0 + (0 << 2), 2);
231    /* SPI_PS_INPUT_CNTL_0 maps to GPR[0] - load with semantic id 0 */
232    E32(((0    << SEMANTIC_shift)	|
233	 (0x01 << DEFAULT_VAL_shift)));
234    /* SPI_PS_INPUT_CNTL_1 maps to GPR[1] - load with semantic id 1 */
235    E32(((1    << SEMANTIC_shift)	|
236	 (0x01 << DEFAULT_VAL_shift)));
237
238    PACK0(SPI_INPUT_Z, 13);
239    E32(0); // SPI_INPUT_Z
240    E32(0); // SPI_FOG_CNTL
241    E32(LINEAR_CENTROID_ENA__X_ON_AT_CENTROID << LINEAR_CENTROID_ENA_shift); // SPI_BARYC_CNTL
242    E32(0); // SPI_PS_IN_CONTROL_2
243    E32(0);
244    E32(0);
245    E32(0);
246    E32(0);
247    E32(0); // SPI_GPR_MGMT
248    E32(0); // SPI_LDS_MGMT
249    E32(0); // SPI_STACK_MGMT
250    E32(0); // SPI_WAVE_MGMT_1
251    E32(0); // SPI_WAVE_MGMT_2
252    END_BATCH();
253
254    // clear FS
255    fs_conf.bo = accel_state->shaders_bo;
256    evergreen_fs_setup(pScrn, &fs_conf, RADEON_GEM_DOMAIN_VRAM);
257
258    // VGT
259    BEGIN_BATCH(46);
260
261    PACK0(VGT_MAX_VTX_INDX, 4);
262    E32(0xffffff);
263    E32(0);
264    E32(0);
265    E32(0);
266
267    PACK0(VGT_INSTANCE_STEP_RATE_0, 2);
268    E32(0);
269    E32(0);
270
271    PACK0(VGT_REUSE_OFF, 2);
272    E32(0);
273    E32(0);
274
275    PACK0(PA_SU_POINT_SIZE, 17);
276    E32(0); // PA_SU_POINT_SIZE
277    E32(0); // PA_SU_POINT_MINMAX
278    E32((8 << PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */ // PA_SU_LINE_CNTL
279    E32(0); // PA_SC_LINE_STIPPLE
280    E32(0); // VGT_OUTPUT_PATH_CNTL
281    E32(0); // VGT_HOS_CNTL
282    E32(0);
283    E32(0);
284    E32(0);
285    E32(0);
286    E32(0);
287    E32(0);
288    E32(0);
289    E32(0);
290    E32(0);
291    E32(0);
292    E32(0); // VGT_GS_MODE
293
294    EREG(VGT_PRIMITIVEID_EN,                  0);
295    EREG(VGT_MULTI_PRIM_IB_RESET_EN,          0);
296    EREG(VGT_SHADER_STAGES_EN,          0);
297
298    PACK0(VGT_STRMOUT_CONFIG, 2);
299    E32(0);
300    E32(0);
301    END_BATCH();
302}
303
304