1/* 2 * Cayman Register documentation 3 * 4 * Copyright (C) 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef _CAYMAN_REG_AUTO 25#define _CAYMAN_REG_AUTO 26 27enum { 28 29 VGT_VTX_VECT_EJECT_REG = 0x000088b0, 30 PRIM_COUNT_mask = 0x3ff << 0, 31 PRIM_COUNT_shift = 0, 32 VGT_LAST_COPY_STATE = 0x000088c0, 33 SRC_STATE_ID_mask = 0x07 << 0, 34 SRC_STATE_ID_shift = 0, 35 DST_STATE_ID_mask = 0x07 << 16, 36 DST_STATE_ID_shift = 16, 37 VGT_CACHE_INVALIDATION = 0x000088c4, 38 CACHE_INVALIDATION_mask = 0x03 << 0, 39 CACHE_INVALIDATION_shift = 0, 40 VC_ONLY = 0x00, 41 TC_ONLY = 0x01, 42 VC_AND_TC = 0x02, 43 VS_NO_EXTRA_BUFFER_bit = 1 << 5, 44 AUTO_INVLD_EN_mask = 0x03 << 6, 45 AUTO_INVLD_EN_shift = 6, 46 VGT_GS_VERTEX_REUSE = 0x000088d4, 47 VERT_REUSE_mask = 0x1f << 0, 48 VERT_REUSE_shift = 0, 49 VGT_CNTL_STATUS = 0x000088f0, 50 VGT_OUT_INDX_BUSY_bit = 1 << 0, 51 VGT_OUT_BUSY_bit = 1 << 1, 52 VGT_PT_BUSY_bit = 1 << 2, 53 VGT_TE_BUSY_bit = 1 << 3, 54 VGT_VR_BUSY_bit = 1 << 4, 55 VGT_PI_BUSY_bit = 1 << 5, 56 VGT_INVLD_BUSY_bit = 1 << 6, 57 VGT_GS_BUSY_bit = 1 << 7, 58 VGT_HS_BUSY_bit = 1 << 8, 59 VGT_TE11_BUSY_bit = 1 << 9, 60 VGT_BUSY_bit = 1 << 10, 61 VGT_PRIMITIVE_TYPE = 0x00008958, 62 VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask = 0x3f << 0, 63 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift = 0, 64 DI_PT_NONE = 0x00, 65 DI_PT_POINTLIST = 0x01, 66 DI_PT_LINELIST = 0x02, 67 DI_PT_LINESTRIP = 0x03, 68 DI_PT_TRILIST = 0x04, 69 DI_PT_TRIFAN = 0x05, 70 DI_PT_TRISTRIP = 0x06, 71 DI_PT_UNUSED_0 = 0x07, 72 DI_PT_UNUSED_1 = 0x08, 73 DI_PT_PATCH = 0x09, 74 DI_PT_LINELIST_ADJ = 0x0a, 75 DI_PT_LINESTRIP_ADJ = 0x0b, 76 DI_PT_TRILIST_ADJ = 0x0c, 77 DI_PT_TRISTRIP_ADJ = 0x0d, 78 DI_PT_UNUSED_3 = 0x0e, 79 DI_PT_UNUSED_4 = 0x0f, 80 DI_PT_TRI_WITH_WFLAGS = 0x10, 81 DI_PT_RECTLIST = 0x11, 82 DI_PT_LINELOOP = 0x12, 83 DI_PT_QUADLIST = 0x13, 84 DI_PT_QUADSTRIP = 0x14, 85 DI_PT_POLYGON = 0x15, 86 DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, 87 DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, 88 DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, 89 DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, 90 DI_PT_2D_FILL_RECT_LIST = 0x1a, 91 DI_PT_2D_LINE_STRIP = 0x1b, 92 DI_PT_2D_TRI_STRIP = 0x1c, 93 VGT_INDEX_TYPE = 0x0000895c, 94 INDEX_TYPE_mask = 0x03 << 0, 95 INDEX_TYPE_shift = 0, 96 DI_INDEX_SIZE_16_BIT = 0x00, 97 DI_INDEX_SIZE_32_BIT = 0x01, 98 VGT_STRMOUT_BUFFER_FILLED_SIZE_0 = 0x00008960, 99 VGT_STRMOUT_BUFFER_FILLED_SIZE_1 = 0x00008964, 100 VGT_STRMOUT_BUFFER_FILLED_SIZE_2 = 0x00008968, 101 VGT_STRMOUT_BUFFER_FILLED_SIZE_3 = 0x0000896c, 102 VGT_NUM_INDICES = 0x00008970, 103 VGT_NUM_INSTANCES = 0x00008974, 104 VGT_SYS_CONFIG = 0x0000898c, 105 DUAL_CORE_EN_bit = 1 << 0, 106 MAX_LS_HS_THDGRP_mask = 0x3f << 1, 107 MAX_LS_HS_THDGRP_shift = 1, 108 PA_CL_CNTL_STATUS = 0x00008a10, 109 CL_BUSY_bit = 1 << 31, 110 PA_CL_ENHANCE = 0x00008a14, 111 CLIP_VTX_REORDER_ENA_bit = 1 << 0, 112 NUM_CLIP_SEQ_mask = 0x03 << 1, 113 NUM_CLIP_SEQ_shift = 1, 114 CLIPPED_PRIM_SEQ_STALL_bit = 1 << 3, 115 VE_NAN_PROC_DISABLE_bit = 1 << 4, 116 PA_SU_CNTL_STATUS = 0x00008a50, 117 SU_BUSY_bit = 1 << 31, 118 PA_SU_LINE_STIPPLE_VALUE = 0x00008a60, 119 LINE_STIPPLE_VALUE_mask = 0xffffff << 0, 120 LINE_STIPPLE_VALUE_shift = 0, 121 PA_SC_LINE_STIPPLE_STATE = 0x00008b10, 122 CURRENT_PTR_mask = 0x0f << 0, 123 CURRENT_PTR_shift = 0, 124 CURRENT_COUNT_mask = 0xff << 8, 125 CURRENT_COUNT_shift = 8, 126 SQ_CONFIG = 0x00008c00, 127 VC_ENABLE_bit = 1 << 0, 128 EXPORT_SRC_C_bit = 1 << 1, 129 GFX_PRIO_mask = 0x03 << 2, 130 GFX_PRIO_shift = 2, 131 CS1_PRIO_mask = 0x03 << 4, 132 CS1_PRIO_shift = 4, 133 CS2_PRIO_mask = 0x03 << 6, 134 CS2_PRIO_shift = 6, 135 SQ_GPR_RESOURCE_MGMT_1 = 0x00008c04, 136 SQ_GPR_RESOURCE_MGMT_1__NUM_PS_GPRS_mask = 0xff << 0, 137 SQ_GPR_RESOURCE_MGMT_1__NUM_PS_GPRS_shift = 0, 138 SQ_GPR_RESOURCE_MGMT_1__NUM_VS_GPRS_mask = 0xff << 16, 139 SQ_GPR_RESOURCE_MGMT_1__NUM_VS_GPRS_shift = 16, 140 NUM_CLAUSE_TEMP_GPRS_mask = 0x0f << 28, 141 NUM_CLAUSE_TEMP_GPRS_shift = 28, 142 SQ_GLOBAL_GPR_RESOURCE_MGMT_1 = 0x00008c10, 143 PS_GGPR_BASE_mask = 0xff << 0, 144 PS_GGPR_BASE_shift = 0, 145 VS_GGPR_BASE_mask = 0xff << 8, 146 VS_GGPR_BASE_shift = 8, 147 GS_GGPR_BASE_mask = 0xff << 16, 148 GS_GGPR_BASE_shift = 16, 149 ES_GGPR_BASE_mask = 0xff << 24, 150 ES_GGPR_BASE_shift = 24, 151 SQ_GLOBAL_GPR_RESOURCE_MGMT_2 = 0x00008c14, 152 HS_GGPR_BASE_mask = 0xff << 0, 153 HS_GGPR_BASE_shift = 0, 154 LS_GGPR_BASE_mask = 0xff << 8, 155 LS_GGPR_BASE_shift = 8, 156 CS_GGPR_BASE_mask = 0xff << 16, 157 CS_GGPR_BASE_shift = 16, 158 SQ_ESGS_RING_BASE = 0x00008c40, 159 SQ_ESGS_RING_SIZE = 0x00008c44, 160 SQ_GSVS_RING_BASE = 0x00008c48, 161 SQ_GSVS_RING_SIZE = 0x00008c4c, 162 SQ_ESTMP_RING_BASE = 0x00008c50, 163 SQ_ESTMP_RING_SIZE = 0x00008c54, 164 SQ_GSTMP_RING_BASE = 0x00008c58, 165 SQ_GSTMP_RING_SIZE = 0x00008c5c, 166 SQ_VSTMP_RING_BASE = 0x00008c60, 167 SQ_VSTMP_RING_SIZE = 0x00008c64, 168 SQ_PSTMP_RING_BASE = 0x00008c68, 169 SQ_PSTMP_RING_SIZE = 0x00008c6c, 170 SQ_ALU_WORD1_OP3 = 0x00008dfc, 171 SRC2_SEL_mask = 0x1ff << 0, 172 SRC2_SEL_shift = 0, 173 SQ_ALU_SRC_LDS_OQ_A = 0xdb, 174 SQ_ALU_SRC_LDS_OQ_B = 0xdc, 175 SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, 176 SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, 177 SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, 178 SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, 179 SQ_ALU_SRC_TIME_HI = 0xe3, 180 SQ_ALU_SRC_TIME_LO = 0xe4, 181 SQ_ALU_SRC_MASK_HI = 0xe5, 182 SQ_ALU_SRC_MASK_LO = 0xe6, 183 SQ_ALU_SRC_HW_WAVE_ID = 0xe7, 184 SQ_ALU_SRC_SIMD_ID = 0xe8, 185 SQ_ALU_SRC_SE_ID = 0xe9, 186 SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, 187 SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, 188 SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, 189 SQ_ALU_SRC_HW_ALU_ODD = 0xed, 190 SQ_ALU_SRC_LOOP_IDX = 0xee, 191 SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, 192 SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, 193 SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, 194 SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, 195 SQ_ALU_SRC_1_DBL_L = 0xf4, 196 SQ_ALU_SRC_1_DBL_M = 0xf5, 197 SQ_ALU_SRC_0_5_DBL_L = 0xf6, 198 SQ_ALU_SRC_0_5_DBL_M = 0xf7, 199 SQ_ALU_SRC_0 = 0xf8, 200 SQ_ALU_SRC_1 = 0xf9, 201 SQ_ALU_SRC_1_INT = 0xfa, 202 SQ_ALU_SRC_M_1_INT = 0xfb, 203 SQ_ALU_SRC_0_5 = 0xfc, 204 SQ_ALU_SRC_LITERAL = 0xfd, 205 SQ_ALU_SRC_PV = 0xfe, 206 SQ_ALU_SRC_PS = 0xff, 207 SRC2_REL_bit = 1 << 9, 208 SRC2_CHAN_mask = 0x03 << 10, 209 SRC2_CHAN_shift = 10, 210 SQ_CHAN_X = 0x00, 211 SQ_CHAN_Y = 0x01, 212 SQ_CHAN_Z = 0x02, 213 SQ_CHAN_W = 0x03, 214 SRC2_NEG_bit = 1 << 12, 215 SQ_ALU_WORD1_OP3__ALU_INST_mask = 0x1f << 13, 216 SQ_ALU_WORD1_OP3__ALU_INST_shift = 13, 217 SQ_OP3_INST_BFE_UINT = 0x04, 218 SQ_OP3_INST_BFE_INT = 0x05, 219 SQ_OP3_INST_BFI_INT = 0x06, 220 SQ_OP3_INST_FMA = 0x07, 221 SQ_OP3_INST_CNDNE_64 = 0x09, 222 SQ_OP3_INST_FMA_64 = 0x0a, 223 SQ_OP3_INST_LERP_UINT = 0x0b, 224 SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, 225 SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, 226 SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, 227 SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, 228 SQ_OP3_INST_MULADD_UINT24 = 0x10, 229 SQ_OP3_INST_LDS_IDX_OP = 0x11, 230 SQ_OP3_INST_MULADD = 0x14, 231 SQ_OP3_INST_MULADD_M2 = 0x15, 232 SQ_OP3_INST_MULADD_M4 = 0x16, 233 SQ_OP3_INST_MULADD_D2 = 0x17, 234 SQ_OP3_INST_MULADD_IEEE = 0x18, 235 SQ_OP3_INST_CNDE = 0x19, 236 SQ_OP3_INST_CNDGT = 0x1a, 237 SQ_OP3_INST_CNDGE = 0x1b, 238 SQ_OP3_INST_CNDE_INT = 0x1c, 239 SQ_OP3_INST_CNDGT_INT = 0x1d, 240 SQ_OP3_INST_CNDGE_INT = 0x1e, 241 SQ_OP3_INST_MUL_LIT = 0x1f, 242 SQ_ALU_WORD1_LDS_DIRECT_LITERAL_LO = 0x00008dfc, 243 OFFSET_A_mask = 0x1fff << 0, 244 OFFSET_A_shift = 0, 245 STRIDE_A_mask = 0x7f << 13, 246 STRIDE_A_shift = 13, 247 THREAD_REL_A_bit = 1 << 22, 248 SQ_TEX_WORD2 = 0x00008dfc, 249 OFFSET_X_mask = 0x1f << 0, 250 OFFSET_X_shift = 0, 251 OFFSET_Y_mask = 0x1f << 5, 252 OFFSET_Y_shift = 5, 253 OFFSET_Z_mask = 0x1f << 10, 254 OFFSET_Z_shift = 10, 255 SAMPLER_ID_mask = 0x1f << 15, 256 SAMPLER_ID_shift = 15, 257 SQ_TEX_WORD2__SRC_SEL_X_mask = 0x07 << 20, 258 SQ_TEX_WORD2__SRC_SEL_X_shift = 20, 259 SQ_SEL_X = 0x00, 260 SQ_SEL_Y = 0x01, 261 SQ_SEL_Z = 0x02, 262 SQ_SEL_W = 0x03, 263 SQ_SEL_0 = 0x04, 264 SQ_SEL_1 = 0x05, 265 SQ_TEX_WORD2__SRC_SEL_Y_mask = 0x07 << 23, 266 SQ_TEX_WORD2__SRC_SEL_Y_shift = 23, 267/* SQ_SEL_X = 0x00, */ 268/* SQ_SEL_Y = 0x01, */ 269/* SQ_SEL_Z = 0x02, */ 270/* SQ_SEL_W = 0x03, */ 271/* SQ_SEL_0 = 0x04, */ 272/* SQ_SEL_1 = 0x05, */ 273 SRC_SEL_Z_mask = 0x07 << 26, 274 SRC_SEL_Z_shift = 26, 275/* SQ_SEL_X = 0x00, */ 276/* SQ_SEL_Y = 0x01, */ 277/* SQ_SEL_Z = 0x02, */ 278/* SQ_SEL_W = 0x03, */ 279/* SQ_SEL_0 = 0x04, */ 280/* SQ_SEL_1 = 0x05, */ 281 SRC_SEL_W_mask = 0x07 << 29, 282 SRC_SEL_W_shift = 29, 283/* SQ_SEL_X = 0x00, */ 284/* SQ_SEL_Y = 0x01, */ 285/* SQ_SEL_Z = 0x02, */ 286/* SQ_SEL_W = 0x03, */ 287/* SQ_SEL_0 = 0x04, */ 288/* SQ_SEL_1 = 0x05, */ 289 SQ_CF_ALLOC_EXPORT_WORD1 = 0x00008dfc, 290 BURST_COUNT_mask = 0x0f << 16, 291 BURST_COUNT_shift = 16, 292 VALID_PIXEL_MODE_bit = 1 << 20, 293 SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xff << 22, 294 SQ_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, 295 SQ_CF_INST_MEM_STREAM0_BUF0 = 0x40, 296 SQ_CF_INST_MEM_STREAM0_BUF1 = 0x41, 297 SQ_CF_INST_MEM_STREAM0_BUF2 = 0x42, 298 SQ_CF_INST_MEM_STREAM0_BUF3 = 0x43, 299 SQ_CF_INST_MEM_STREAM1_BUF0 = 0x44, 300 SQ_CF_INST_MEM_STREAM1_BUF1 = 0x45, 301 SQ_CF_INST_MEM_STREAM1_BUF2 = 0x46, 302 SQ_CF_INST_MEM_STREAM1_BUF3 = 0x47, 303 SQ_CF_INST_MEM_STREAM2_BUF0 = 0x48, 304 SQ_CF_INST_MEM_STREAM2_BUF1 = 0x49, 305 SQ_CF_INST_MEM_STREAM2_BUF2 = 0x4a, 306 SQ_CF_INST_MEM_STREAM2_BUF3 = 0x4b, 307 SQ_CF_INST_MEM_STREAM3_BUF0 = 0x4c, 308 SQ_CF_INST_MEM_STREAM3_BUF1 = 0x4d, 309 SQ_CF_INST_MEM_STREAM3_BUF2 = 0x4e, 310 SQ_CF_INST_MEM_STREAM3_BUF3 = 0x4f, 311 SQ_CF_INST_MEM_SCRATCH = 0x50, 312 SQ_CF_INST_MEM_RING = 0x52, 313 SQ_CF_INST_EXPORT = 0x53, 314 SQ_CF_INST_EXPORT_DONE = 0x54, 315 SQ_CF_INST_MEM_EXPORT = 0x55, 316 SQ_CF_INST_MEM_RAT = 0x56, 317 SQ_CF_INST_MEM_RAT_CACHELESS = 0x57, 318 SQ_CF_INST_MEM_RING1 = 0x58, 319 SQ_CF_INST_MEM_RING2 = 0x59, 320 SQ_CF_INST_MEM_RING3 = 0x5a, 321 SQ_CF_INST_MEM_EXPORT_COMBINED = 0x5b, 322 SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS = 0x5c, 323 SQ_CF_INST_MEM_RAT_COMBINED = 0x5d, 324 SQ_CF_INST_EXPORT_DONE_END_IS_NEXT = 0x5e, 325 MARK_bit = 1 << 30, 326 BARRIER_bit = 1 << 31, 327 SQ_CF_ALU_WORD1 = 0x00008dfc, 328 KCACHE_MODE1_mask = 0x03 << 0, 329 KCACHE_MODE1_shift = 0, 330 SQ_CF_KCACHE_NOP = 0x00, 331 SQ_CF_KCACHE_LOCK_1 = 0x01, 332 SQ_CF_KCACHE_LOCK_2 = 0x02, 333 SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, 334 KCACHE_ADDR0_mask = 0xff << 2, 335 KCACHE_ADDR0_shift = 2, 336 KCACHE_ADDR1_mask = 0xff << 10, 337 KCACHE_ADDR1_shift = 10, 338 SQ_CF_ALU_WORD1__COUNT_mask = 0x7f << 18, 339 SQ_CF_ALU_WORD1__COUNT_shift = 18, 340 SQ_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25, 341 SQ_CF_ALU_WORD1__CF_INST_mask = 0x0f << 26, 342 SQ_CF_ALU_WORD1__CF_INST_shift = 26, 343 SQ_CF_INST_ALU = 0x08, 344 SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, 345 SQ_CF_INST_ALU_POP_AFTER = 0x0a, 346 SQ_CF_INST_ALU_POP2_AFTER = 0x0b, 347 SQ_CF_INST_ALU_EXTENDED = 0x0c, 348 SQ_CF_INST_ALU_CONTINUE = 0x0d, 349 SQ_CF_INST_ALU_BREAK = 0x0e, 350 SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, 351 WHOLE_QUAD_MODE_bit = 1 << 30, 352/* BARRIER_bit = 1 << 31, */ 353 SQ_TEX_WORD1 = 0x00008dfc, 354 SQ_TEX_WORD1__DST_GPR_mask = 0x7f << 0, 355 SQ_TEX_WORD1__DST_GPR_shift = 0, 356 SQ_TEX_WORD1__DST_REL_bit = 1 << 7, 357 SQ_TEX_WORD1__DST_SEL_X_mask = 0x07 << 9, 358 SQ_TEX_WORD1__DST_SEL_X_shift = 9, 359/* SQ_SEL_X = 0x00, */ 360/* SQ_SEL_Y = 0x01, */ 361/* SQ_SEL_Z = 0x02, */ 362/* SQ_SEL_W = 0x03, */ 363/* SQ_SEL_0 = 0x04, */ 364/* SQ_SEL_1 = 0x05, */ 365 SQ_SEL_MASK = 0x07, 366 SQ_TEX_WORD1__DST_SEL_Y_mask = 0x07 << 12, 367 SQ_TEX_WORD1__DST_SEL_Y_shift = 12, 368/* SQ_SEL_X = 0x00, */ 369/* SQ_SEL_Y = 0x01, */ 370/* SQ_SEL_Z = 0x02, */ 371/* SQ_SEL_W = 0x03, */ 372/* SQ_SEL_0 = 0x04, */ 373/* SQ_SEL_1 = 0x05, */ 374/* SQ_SEL_MASK = 0x07, */ 375 SQ_TEX_WORD1__DST_SEL_Z_mask = 0x07 << 15, 376 SQ_TEX_WORD1__DST_SEL_Z_shift = 15, 377/* SQ_SEL_X = 0x00, */ 378/* SQ_SEL_Y = 0x01, */ 379/* SQ_SEL_Z = 0x02, */ 380/* SQ_SEL_W = 0x03, */ 381/* SQ_SEL_0 = 0x04, */ 382/* SQ_SEL_1 = 0x05, */ 383/* SQ_SEL_MASK = 0x07, */ 384 SQ_TEX_WORD1__DST_SEL_W_mask = 0x07 << 18, 385 SQ_TEX_WORD1__DST_SEL_W_shift = 18, 386/* SQ_SEL_X = 0x00, */ 387/* SQ_SEL_Y = 0x01, */ 388/* SQ_SEL_Z = 0x02, */ 389/* SQ_SEL_W = 0x03, */ 390/* SQ_SEL_0 = 0x04, */ 391/* SQ_SEL_1 = 0x05, */ 392/* SQ_SEL_MASK = 0x07, */ 393 SQ_TEX_WORD1__LOD_BIAS_mask = 0x7f << 21, 394 SQ_TEX_WORD1__LOD_BIAS_shift = 21, 395 COORD_TYPE_X_bit = 1 << 28, 396 COORD_TYPE_Y_bit = 1 << 29, 397 COORD_TYPE_Z_bit = 1 << 30, 398 COORD_TYPE_W_bit = 1 << 31, 399 SQ_ALU_WORD1_OP2_MOVA = 0x00008dfc, 400 MOVA_DST_mask = 0x7f << 21, 401 MOVA_DST_shift = 21, 402 SQ_ALU_MOVA_DST_AR_X = 0x00, 403 SQ_ALU_MOVA_DST_CF_PC = 0x01, 404 SQ_ALU_MOVA_DST_CF_IDX0 = 0x02, 405 SQ_ALU_MOVA_DST_CF_IDX1 = 0x03, 406 SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B0 = 0x04, 407 SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B1 = 0x05, 408 SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B2 = 0x06, 409 SQ_ALU_MOVA_DST_CLAUSE_GLOBAL_B3 = 0x07, 410 SQ_VTX_WORD0 = 0x00008dfc, 411 VTX_INST_mask = 0x1f << 0, 412 VTX_INST_shift = 0, 413 SQ_VTX_INST_FETCH = 0x00, 414 SQ_VTX_INST_SEMANTIC = 0x01, 415 SQ_VTX_INST_GET_BUFFER_RESINFO = 0x0e, 416 FETCH_TYPE_mask = 0x03 << 5, 417 FETCH_TYPE_shift = 5, 418 SQ_VTX_FETCH_VERTEX_DATA = 0x00, 419 SQ_VTX_FETCH_INSTANCE_DATA = 0x01, 420 SQ_VTX_FETCH_NO_INDEX_OFFSET = 0x02, 421 FETCH_WHOLE_QUAD_bit = 1 << 7, 422 BUFFER_ID_mask = 0xff << 8, 423 BUFFER_ID_shift = 8, 424 SQ_VTX_WORD0__SRC_GPR_mask = 0x7f << 16, 425 SQ_VTX_WORD0__SRC_GPR_shift = 16, 426 SRC_REL_bit = 1 << 23, 427 SQ_VTX_WORD0__SRC_SEL_X_mask = 0x03 << 24, 428 SQ_VTX_WORD0__SRC_SEL_X_shift = 24, 429/* SQ_SEL_X = 0x00, */ 430/* SQ_SEL_Y = 0x01, */ 431/* SQ_SEL_Z = 0x02, */ 432/* SQ_SEL_W = 0x03, */ 433 SQ_VTX_WORD0__SRC_SEL_Y_mask = 0x03 << 26, 434 SQ_VTX_WORD0__SRC_SEL_Y_shift = 26, 435/* SQ_SEL_X = 0x00, */ 436/* SQ_SEL_Y = 0x01, */ 437/* SQ_SEL_Z = 0x02, */ 438/* SQ_SEL_W = 0x03, */ 439 STRUCTURED_READ_mask = 0x03 << 28, 440 STRUCTURED_READ_shift = 28, 441 SQ_VTX_STRU_READ_OFF = 0x00, 442 SQ_VTX_STRU_READ_GPR_OFFSET = 0x01, 443 SQ_VTX_STRU_READ_INST_OFFSET = 0x02, 444 LDS_REQ_bit = 1 << 30, 445 COALESCED_READ_bit = 1 << 31, 446 SQ_CF_ALLOC_EXPORT_WORD1_SWIZ = 0x00008dfc, 447 SEL_X_mask = 0x07 << 0, 448 SEL_X_shift = 0, 449/* SQ_SEL_X = 0x00, */ 450/* SQ_SEL_Y = 0x01, */ 451/* SQ_SEL_Z = 0x02, */ 452/* SQ_SEL_W = 0x03, */ 453/* SQ_SEL_0 = 0x04, */ 454/* SQ_SEL_1 = 0x05, */ 455/* SQ_SEL_MASK = 0x07, */ 456 SEL_Y_mask = 0x07 << 3, 457 SEL_Y_shift = 3, 458/* SQ_SEL_X = 0x00, */ 459/* SQ_SEL_Y = 0x01, */ 460/* SQ_SEL_Z = 0x02, */ 461/* SQ_SEL_W = 0x03, */ 462/* SQ_SEL_0 = 0x04, */ 463/* SQ_SEL_1 = 0x05, */ 464/* SQ_SEL_MASK = 0x07, */ 465 SEL_Z_mask = 0x07 << 6, 466 SEL_Z_shift = 6, 467/* SQ_SEL_X = 0x00, */ 468/* SQ_SEL_Y = 0x01, */ 469/* SQ_SEL_Z = 0x02, */ 470/* SQ_SEL_W = 0x03, */ 471/* SQ_SEL_0 = 0x04, */ 472/* SQ_SEL_1 = 0x05, */ 473/* SQ_SEL_MASK = 0x07, */ 474 SEL_W_mask = 0x07 << 9, 475 SEL_W_shift = 9, 476/* SQ_SEL_X = 0x00, */ 477/* SQ_SEL_Y = 0x01, */ 478/* SQ_SEL_Z = 0x02, */ 479/* SQ_SEL_W = 0x03, */ 480/* SQ_SEL_0 = 0x04, */ 481/* SQ_SEL_1 = 0x05, */ 482/* SQ_SEL_MASK = 0x07, */ 483 SQ_MEM_RD_WORD0 = 0x00008dfc, 484 MEM_INST_mask = 0x1f << 0, 485 MEM_INST_shift = 0, 486 SQ_MEM_INST_MEM = 0x02, 487 SQ_MEM_RD_WORD0__ELEM_SIZE_mask = 0x03 << 5, 488 SQ_MEM_RD_WORD0__ELEM_SIZE_shift = 5, 489/* FETCH_WHOLE_QUAD_bit = 1 << 7, */ 490 MEM_OP_mask = 0x07 << 8, 491 MEM_OP_shift = 8, 492 SQ_MEM_OP_RD_SCRATCH = 0x00, 493 SQ_MEM_OP_RD_SCATTER = 0x02, 494 SQ_MEM_OP_GDS = 0x04, 495 SQ_MEM_OP_TF_WRITE = 0x05, 496 SQ_MEM_RD_WORD0__UNCACHED_bit = 1 << 11, 497 INDEXED_bit = 1 << 12, 498 SQ_MEM_RD_WORD0__SRC_SEL_Y_mask = 0x03 << 13, 499 SQ_MEM_RD_WORD0__SRC_SEL_Y_shift = 13, 500/* SQ_SEL_X = 0x00, */ 501/* SQ_SEL_Y = 0x01, */ 502/* SQ_SEL_Z = 0x02, */ 503/* SQ_SEL_W = 0x03, */ 504 SQ_MEM_RD_WORD0__SRC_GPR_mask = 0x7f << 16, 505 SQ_MEM_RD_WORD0__SRC_GPR_shift = 16, 506/* SRC_REL_bit = 1 << 23, */ 507 SQ_MEM_RD_WORD0__SRC_SEL_X_mask = 0x03 << 24, 508 SQ_MEM_RD_WORD0__SRC_SEL_X_shift = 24, 509/* SQ_SEL_X = 0x00, */ 510/* SQ_SEL_Y = 0x01, */ 511/* SQ_SEL_Z = 0x02, */ 512/* SQ_SEL_W = 0x03, */ 513 BURST_CNT_mask = 0x0f << 26, 514 BURST_CNT_shift = 26, 515/* LDS_REQ_bit = 1 << 30, */ 516/* COALESCED_READ_bit = 1 << 31, */ 517 SQ_ALU_WORD1 = 0x00008dfc, 518 SQ_ALU_WORD1__ENCODING_mask = 0x07 << 15, 519 SQ_ALU_WORD1__ENCODING_shift = 15, 520 BANK_SWIZZLE_mask = 0x07 << 18, 521 BANK_SWIZZLE_shift = 18, 522 SQ_ALU_VEC_012 = 0x00, 523 SQ_ALU_VEC_021 = 0x01, 524 SQ_ALU_VEC_120 = 0x02, 525 SQ_ALU_VEC_102 = 0x03, 526 SQ_ALU_VEC_201 = 0x04, 527 SQ_ALU_VEC_210 = 0x05, 528 SQ_ALU_WORD1__DST_GPR_mask = 0x7f << 21, 529 SQ_ALU_WORD1__DST_GPR_shift = 21, 530 SQ_ALU_WORD1__DST_REL_bit = 1 << 28, 531 DST_CHAN_mask = 0x03 << 29, 532 DST_CHAN_shift = 29, 533 CHAN_X = 0x00, 534 CHAN_Y = 0x01, 535 CHAN_Z = 0x02, 536 CHAN_W = 0x03, 537 SQ_ALU_WORD1__CLAMP_bit = 1 << 31, 538 SQ_CF_ALU_WORD0_EXT = 0x00008dfc, 539 KCACHE_BANK_INDEX_MODE0_mask = 0x03 << 4, 540 KCACHE_BANK_INDEX_MODE0_shift = 4, 541 SQ_CF_INDEX_NONE = 0x00, 542 SQ_CF_INDEX_0 = 0x01, 543 SQ_CF_INDEX_1 = 0x02, 544 SQ_CF_INVALID = 0x03, 545 KCACHE_BANK_INDEX_MODE1_mask = 0x03 << 6, 546 KCACHE_BANK_INDEX_MODE1_shift = 6, 547/* SQ_CF_INDEX_NONE = 0x00, */ 548/* SQ_CF_INDEX_0 = 0x01, */ 549/* SQ_CF_INDEX_1 = 0x02, */ 550/* SQ_CF_INVALID = 0x03, */ 551 KCACHE_BANK_INDEX_MODE2_mask = 0x03 << 8, 552 KCACHE_BANK_INDEX_MODE2_shift = 8, 553/* SQ_CF_INDEX_NONE = 0x00, */ 554/* SQ_CF_INDEX_0 = 0x01, */ 555/* SQ_CF_INDEX_1 = 0x02, */ 556/* SQ_CF_INVALID = 0x03, */ 557 KCACHE_BANK_INDEX_MODE3_mask = 0x03 << 10, 558 KCACHE_BANK_INDEX_MODE3_shift = 10, 559/* SQ_CF_INDEX_NONE = 0x00, */ 560/* SQ_CF_INDEX_0 = 0x01, */ 561/* SQ_CF_INDEX_1 = 0x02, */ 562/* SQ_CF_INVALID = 0x03, */ 563 KCACHE_BANK2_mask = 0x0f << 22, 564 KCACHE_BANK2_shift = 22, 565 KCACHE_BANK3_mask = 0x0f << 26, 566 KCACHE_BANK3_shift = 26, 567 KCACHE_MODE2_mask = 0x03 << 30, 568 KCACHE_MODE2_shift = 30, 569/* SQ_CF_KCACHE_NOP = 0x00, */ 570/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ 571/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ 572/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ 573 SQ_ALU_WORD0_LDS_IDX_OP = 0x00008dfc, 574 SRC0_SEL_mask = 0x1ff << 0, 575 SRC0_SEL_shift = 0, 576/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 577/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 578/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 579/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 580/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 581/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 582/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 583/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 584/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 585/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 586/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 587/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 588/* SQ_ALU_SRC_SE_ID = 0xe9, */ 589/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 590/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 591/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 592/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 593/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 594/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 595/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 596/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 597/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 598/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 599/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 600/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 601/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 602/* SQ_ALU_SRC_0 = 0xf8, */ 603/* SQ_ALU_SRC_1 = 0xf9, */ 604/* SQ_ALU_SRC_1_INT = 0xfa, */ 605/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 606/* SQ_ALU_SRC_0_5 = 0xfc, */ 607/* SQ_ALU_SRC_LITERAL = 0xfd, */ 608/* SQ_ALU_SRC_PV = 0xfe, */ 609/* SQ_ALU_SRC_PS = 0xff, */ 610 SRC0_REL_bit = 1 << 9, 611 SRC0_CHAN_mask = 0x03 << 10, 612 SRC0_CHAN_shift = 10, 613/* SQ_CHAN_X = 0x00, */ 614/* SQ_CHAN_Y = 0x01, */ 615/* SQ_CHAN_Z = 0x02, */ 616/* SQ_CHAN_W = 0x03, */ 617 IDX_OFFSET_4_bit = 1 << 12, 618 SRC1_SEL_mask = 0x1ff << 13, 619 SRC1_SEL_shift = 13, 620/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 621/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 622/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 623/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 624/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 625/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 626/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 627/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 628/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 629/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 630/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 631/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 632/* SQ_ALU_SRC_SE_ID = 0xe9, */ 633/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 634/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 635/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 636/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 637/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 638/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 639/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 640/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 641/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 642/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 643/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 644/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 645/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 646/* SQ_ALU_SRC_0 = 0xf8, */ 647/* SQ_ALU_SRC_1 = 0xf9, */ 648/* SQ_ALU_SRC_1_INT = 0xfa, */ 649/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 650/* SQ_ALU_SRC_0_5 = 0xfc, */ 651/* SQ_ALU_SRC_LITERAL = 0xfd, */ 652/* SQ_ALU_SRC_PV = 0xfe, */ 653/* SQ_ALU_SRC_PS = 0xff, */ 654 SRC1_REL_bit = 1 << 22, 655 SRC1_CHAN_mask = 0x03 << 23, 656 SRC1_CHAN_shift = 23, 657/* SQ_CHAN_X = 0x00, */ 658/* SQ_CHAN_Y = 0x01, */ 659/* SQ_CHAN_Z = 0x02, */ 660/* SQ_CHAN_W = 0x03, */ 661 IDX_OFFSET_5_bit = 1 << 25, 662 INDEX_MODE_mask = 0x07 << 26, 663 INDEX_MODE_shift = 26, 664 SQ_INDEX_AR_X = 0x00, 665 SQ_INDEX_LOOP = 0x04, 666 SQ_INDEX_GLOBAL = 0x05, 667 SQ_INDEX_GLOBAL_AR_X = 0x06, 668 PRED_SEL_mask = 0x03 << 29, 669 PRED_SEL_shift = 29, 670 SQ_PRED_SEL_OFF = 0x00, 671 SQ_PRED_SEL_ZERO = 0x02, 672 SQ_PRED_SEL_ONE = 0x03, 673 LAST_bit = 1 << 31, 674 SQ_MEM_GDS_WORD2 = 0x00008dfc, 675 SQ_MEM_GDS_WORD2__DST_SEL_X_mask = 0x07 << 0, 676 SQ_MEM_GDS_WORD2__DST_SEL_X_shift = 0, 677/* SQ_SEL_X = 0x00, */ 678/* SQ_SEL_Y = 0x01, */ 679/* SQ_SEL_Z = 0x02, */ 680/* SQ_SEL_W = 0x03, */ 681/* SQ_SEL_0 = 0x04, */ 682/* SQ_SEL_1 = 0x05, */ 683/* SQ_SEL_MASK = 0x07, */ 684 SQ_MEM_GDS_WORD2__DST_SEL_Y_mask = 0x07 << 3, 685 SQ_MEM_GDS_WORD2__DST_SEL_Y_shift = 3, 686/* SQ_SEL_X = 0x00, */ 687/* SQ_SEL_Y = 0x01, */ 688/* SQ_SEL_Z = 0x02, */ 689/* SQ_SEL_W = 0x03, */ 690/* SQ_SEL_0 = 0x04, */ 691/* SQ_SEL_1 = 0x05, */ 692/* SQ_SEL_MASK = 0x07, */ 693 SQ_MEM_GDS_WORD2__DST_SEL_Z_mask = 0x07 << 6, 694 SQ_MEM_GDS_WORD2__DST_SEL_Z_shift = 6, 695/* SQ_SEL_X = 0x00, */ 696/* SQ_SEL_Y = 0x01, */ 697/* SQ_SEL_Z = 0x02, */ 698/* SQ_SEL_W = 0x03, */ 699/* SQ_SEL_0 = 0x04, */ 700/* SQ_SEL_1 = 0x05, */ 701/* SQ_SEL_MASK = 0x07, */ 702 SQ_MEM_GDS_WORD2__DST_SEL_W_mask = 0x07 << 9, 703 SQ_MEM_GDS_WORD2__DST_SEL_W_shift = 9, 704/* SQ_SEL_X = 0x00, */ 705/* SQ_SEL_Y = 0x01, */ 706/* SQ_SEL_Z = 0x02, */ 707/* SQ_SEL_W = 0x03, */ 708/* SQ_SEL_0 = 0x04, */ 709/* SQ_SEL_1 = 0x05, */ 710/* SQ_SEL_MASK = 0x07, */ 711 SQ_CF_ALLOC_EXPORT_WORD0_RAT = 0x00008dfc, 712 RAT_ID_mask = 0x0f << 0, 713 RAT_ID_shift = 0, 714 RAT_INST_mask = 0x3f << 4, 715 RAT_INST_shift = 4, 716 SQ_EXPORT_RAT_INST_NOP = 0x00, 717 SQ_EXPORT_RAT_INST_STORE_TYPED = 0x01, 718 SQ_EXPORT_RAT_INST_STORE_RAW = 0x02, 719 SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x03, 720 SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x04, 721 SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x05, 722 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x06, 723 SQ_EXPORT_RAT_INST_ADD = 0x07, 724 SQ_EXPORT_RAT_INST_SUB = 0x08, 725 SQ_EXPORT_RAT_INST_RSUB = 0x09, 726 SQ_EXPORT_RAT_INST_MIN_INT = 0x0a, 727 SQ_EXPORT_RAT_INST_MIN_UINT = 0x0b, 728 SQ_EXPORT_RAT_INST_MAX_INT = 0x0c, 729 SQ_EXPORT_RAT_INST_MAX_UINT = 0x0d, 730 SQ_EXPORT_RAT_INST_AND = 0x0e, 731 SQ_EXPORT_RAT_INST_OR = 0x0f, 732 SQ_EXPORT_RAT_INST_XOR = 0x10, 733 SQ_EXPORT_RAT_INST_MSKOR = 0x11, 734 SQ_EXPORT_RAT_INST_INC_UINT = 0x12, 735 SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, 736 SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, 737 SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, 738 SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, 739 SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, 740 SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, 741 SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, 742 SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, 743 SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, 744 SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, 745 SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, 746 SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, 747 SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, 748 SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, 749 SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, 750 SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, 751 SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, 752 SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, 753 SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, 754 SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, 755 RAT_INDEX_MODE_mask = 0x03 << 11, 756 RAT_INDEX_MODE_shift = 11, 757/* SQ_CF_INDEX_NONE = 0x00, */ 758/* SQ_CF_INDEX_0 = 0x01, */ 759/* SQ_CF_INDEX_1 = 0x02, */ 760/* SQ_CF_INVALID = 0x03, */ 761 SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_mask = 0x03 << 13, 762 SQ_CF_ALLOC_EXPORT_WORD0_RAT__TYPE_shift = 13, 763 SQ_EXPORT_PIXEL = 0x00, 764 SQ_EXPORT_POS = 0x01, 765 SQ_EXPORT_PARAM = 0x02, 766 X_UNUSED_FOR_SX_EXPORTS = 0x03, 767 RW_GPR_mask = 0x7f << 15, 768 RW_GPR_shift = 15, 769 RW_REL_bit = 1 << 22, 770 INDEX_GPR_mask = 0x7f << 23, 771 INDEX_GPR_shift = 23, 772 SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_mask = 0x03 << 30, 773 SQ_CF_ALLOC_EXPORT_WORD0_RAT__ELEM_SIZE_shift = 30, 774 SQ_CF_ALU_WORD0 = 0x00008dfc, 775 SQ_CF_ALU_WORD0__ADDR_mask = 0x3fffff << 0, 776 SQ_CF_ALU_WORD0__ADDR_shift = 0, 777 KCACHE_BANK0_mask = 0x0f << 22, 778 KCACHE_BANK0_shift = 22, 779 KCACHE_BANK1_mask = 0x0f << 26, 780 KCACHE_BANK1_shift = 26, 781 KCACHE_MODE0_mask = 0x03 << 30, 782 KCACHE_MODE0_shift = 30, 783/* SQ_CF_KCACHE_NOP = 0x00, */ 784/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ 785/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ 786/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ 787 SQ_MEM_GDS_WORD1 = 0x00008dfc, 788 SQ_MEM_GDS_WORD1__DST_GPR_mask = 0x7f << 0, 789 SQ_MEM_GDS_WORD1__DST_GPR_shift = 0, 790 DST_REL_MODE_mask = 0x03 << 7, 791 DST_REL_MODE_shift = 7, 792 SQ_REL_NONE = 0x00, 793 SQ_REL_LOOP = 0x01, 794 SQ_REL_GLOBAL = 0x02, 795 GDS_OP_mask = 0x3f << 9, 796 GDS_OP_shift = 9, 797 SQ_DS_INST_ADD = 0x00, 798 SQ_DS_INST_SUB = 0x01, 799 SQ_DS_INST_RSUB = 0x02, 800 SQ_DS_INST_INC = 0x03, 801 SQ_DS_INST_DEC = 0x04, 802 SQ_DS_INST_MIN_INT = 0x05, 803 SQ_DS_INST_MAX_INT = 0x06, 804 SQ_DS_INST_MIN_UINT = 0x07, 805 SQ_DS_INST_MAX_UINT = 0x08, 806 SQ_DS_INST_AND = 0x09, 807 SQ_DS_INST_OR = 0x0a, 808 SQ_DS_INST_XOR = 0x0b, 809 SQ_DS_INST_MSKOR = 0x0c, 810 SQ_DS_INST_WRITE = 0x0d, 811 SQ_DS_INST_WRITE_REL = 0x0e, 812 SQ_DS_INST_WRITE2 = 0x0f, 813 SQ_DS_INST_CMP_STORE = 0x10, 814 SQ_DS_INST_CMP_STORE_SPF = 0x11, 815 SQ_DS_INST_BYTE_WRITE = 0x12, 816 SQ_DS_INST_SHORT_WRITE = 0x13, 817 SQ_DS_INST_ADD_RET = 0x20, 818 SQ_DS_INST_SUB_RET = 0x21, 819 SQ_DS_INST_RSUB_RET = 0x22, 820 SQ_DS_INST_INC_RET = 0x23, 821 SQ_DS_INST_DEC_RET = 0x24, 822 SQ_DS_INST_MIN_INT_RET = 0x25, 823 SQ_DS_INST_MAX_INT_RET = 0x26, 824 SQ_DS_INST_MIN_UINT_RET = 0x27, 825 SQ_DS_INST_MAX_UINT_RET = 0x28, 826 SQ_DS_INST_AND_RET = 0x29, 827 SQ_DS_INST_OR_RET = 0x2a, 828 SQ_DS_INST_XOR_RET = 0x2b, 829 SQ_DS_INST_MSKOR_RET = 0x2c, 830 SQ_DS_INST_XCHG_RET = 0x2d, 831 SQ_DS_INST_XCHG_REL_RET = 0x2e, 832 SQ_DS_INST_XCHG2_RET = 0x2f, 833 SQ_DS_INST_CMP_XCHG_RET = 0x30, 834 SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, 835 SQ_DS_INST_READ_RET = 0x32, 836 SQ_DS_INST_READ_REL_RET = 0x33, 837 SQ_DS_INST_READ2_RET = 0x34, 838 SQ_DS_INST_READWRITE_RET = 0x35, 839 SQ_DS_INST_BYTE_READ_RET = 0x36, 840 SQ_DS_INST_UBYTE_READ_RET = 0x37, 841 SQ_DS_INST_SHORT_READ_RET = 0x38, 842 SQ_DS_INST_USHORT_READ_RET = 0x39, 843 SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, 844 DS_OFFSET_mask = 0x7f << 16, 845 DS_OFFSET_shift = 16, 846 UAV_INDEX_MODE_mask = 0x03 << 24, 847 UAV_INDEX_MODE_shift = 24, 848/* SQ_CF_INDEX_NONE = 0x00, */ 849/* SQ_CF_INDEX_0 = 0x01, */ 850/* SQ_CF_INDEX_1 = 0x02, */ 851/* SQ_CF_INVALID = 0x03, */ 852 UAV_ID_mask = 0x0f << 26, 853 UAV_ID_shift = 26, 854 ALLOC_CONSUME_bit = 1 << 30, 855 BCAST_FIRST_REQ_bit = 1 << 31, 856 SQ_MEM_RD_WORD2 = 0x00008dfc, 857 ARRAY_BASE_mask = 0x1fff << 0, 858 ARRAY_BASE_shift = 0, 859 SQ_MEM_RD_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, 860 SQ_MEM_RD_WORD2__ENDIAN_SWAP_shift = 16, 861 SQ_ENDIAN_NONE = 0x00, 862 SQ_ENDIAN_8IN16 = 0x01, 863 SQ_ENDIAN_8IN32 = 0x02, 864 SQ_MEM_RD_WORD2__ARRAY_SIZE_mask = 0xfff << 20, 865 SQ_MEM_RD_WORD2__ARRAY_SIZE_shift = 20, 866 SQ_CF_ALU_WORD1_EXT = 0x00008dfc, 867 KCACHE_MODE3_mask = 0x03 << 0, 868 KCACHE_MODE3_shift = 0, 869/* SQ_CF_KCACHE_NOP = 0x00, */ 870/* SQ_CF_KCACHE_LOCK_1 = 0x01, */ 871/* SQ_CF_KCACHE_LOCK_2 = 0x02, */ 872/* SQ_CF_KCACHE_LOCK_LOOP_INDEX = 0x03, */ 873 KCACHE_ADDR2_mask = 0xff << 2, 874 KCACHE_ADDR2_shift = 2, 875 KCACHE_ADDR3_mask = 0xff << 10, 876 KCACHE_ADDR3_shift = 10, 877 SQ_CF_ALU_WORD1_EXT__CF_INST_mask = 0x0f << 26, 878 SQ_CF_ALU_WORD1_EXT__CF_INST_shift = 26, 879/* SQ_CF_INST_ALU = 0x08, */ 880/* SQ_CF_INST_ALU_PUSH_BEFORE = 0x09, */ 881/* SQ_CF_INST_ALU_POP_AFTER = 0x0a, */ 882/* SQ_CF_INST_ALU_POP2_AFTER = 0x0b, */ 883/* SQ_CF_INST_ALU_EXTENDED = 0x0c, */ 884/* SQ_CF_INST_ALU_CONTINUE = 0x0d, */ 885/* SQ_CF_INST_ALU_BREAK = 0x0e, */ 886/* SQ_CF_INST_ALU_ELSE_AFTER = 0x0f, */ 887/* BARRIER_bit = 1 << 31, */ 888 SQ_CF_GWS_WORD0 = 0x00008dfc, 889 VALUE_mask = 0x3ff << 0, 890 VALUE_shift = 0, 891 RESOURCE_mask = 0x1f << 16, 892 RESOURCE_shift = 16, 893 SIGN_bit = 1 << 25, 894 VAL_INDEX_MODE_mask = 0x03 << 26, 895 VAL_INDEX_MODE_shift = 26, 896 SQ_GWS_INDEX_NONE = 0x00, 897 SQ_GWS_INDEX_0 = 0x01, 898 SQ_GWS_INDEX_1 = 0x02, 899 SQ_GWS_INDEX_MIX = 0x03, 900 RSRC_INDEX_MODE_mask = 0x03 << 28, 901 RSRC_INDEX_MODE_shift = 28, 902/* SQ_CF_INDEX_NONE = 0x00, */ 903/* SQ_CF_INDEX_0 = 0x01, */ 904/* SQ_CF_INDEX_1 = 0x02, */ 905/* SQ_CF_INVALID = 0x03, */ 906 GWS_OPCODE_mask = 0x03 << 30, 907 GWS_OPCODE_shift = 30, 908 SQ_GWS_SEMA_V = 0x00, 909 SQ_GWS_SEMA_P = 0x01, 910 SQ_GWS_BARRIER = 0x02, 911 SQ_GWS_INIT = 0x03, 912 SQ_VTX_WORD2 = 0x00008dfc, 913 SQ_VTX_WORD2__OFFSET_mask = 0xffff << 0, 914 SQ_VTX_WORD2__OFFSET_shift = 0, 915 SQ_VTX_WORD2__ENDIAN_SWAP_mask = 0x03 << 16, 916 SQ_VTX_WORD2__ENDIAN_SWAP_shift = 16, 917/* SQ_ENDIAN_NONE = 0x00, */ 918/* SQ_ENDIAN_8IN16 = 0x01, */ 919/* SQ_ENDIAN_8IN32 = 0x02, */ 920 CONST_BUF_NO_STRIDE_bit = 1 << 18, 921 SQ_VTX_WORD2__ALT_CONST_bit = 1 << 20, 922 BUFFER_INDEX_MODE_mask = 0x03 << 21, 923 BUFFER_INDEX_MODE_shift = 21, 924/* SQ_CF_INDEX_NONE = 0x00, */ 925/* SQ_CF_INDEX_0 = 0x01, */ 926/* SQ_CF_INDEX_1 = 0x02, */ 927/* SQ_CF_INVALID = 0x03, */ 928 SQ_ALU_WORD1_OP2_EXECUTE_MASK = 0x00008dfc, 929 EXECUTE_MASK_OP_mask = 0x03 << 5, 930 EXECUTE_MASK_OP_shift = 5, 931 SQ_ALU_EXECUTE_MASK_OP_DEACTIVATE = 0x00, 932 SQ_ALU_EXECUTE_MASK_OP_BREAK = 0x01, 933 SQ_ALU_EXECUTE_MASK_OP_CONTINUE = 0x02, 934 SQ_ALU_EXECUTE_MASK_OP_KILL = 0x03, 935 SQ_CF_ALLOC_EXPORT_WORD1_BUF = 0x00008dfc, 936 SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xfff << 0, 937 SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, 938 COMP_MASK_mask = 0x0f << 12, 939 COMP_MASK_shift = 12, 940 SQ_CF_WORD0 = 0x00008dfc, 941 SQ_CF_WORD0__ADDR_mask = 0xffffff << 0, 942 SQ_CF_WORD0__ADDR_shift = 0, 943 JUMPTABLE_SEL_mask = 0x07 << 24, 944 JUMPTABLE_SEL_shift = 24, 945 SQ_CF_JUMPTABLE_SEL_CONST_A = 0x00, 946 SQ_CF_JUMPTABLE_SEL_CONST_B = 0x01, 947 SQ_CF_JUMPTABLE_SEL_CONST_C = 0x02, 948 SQ_CF_JUMPTABLE_SEL_CONST_D = 0x03, 949 SQ_CF_JUMPTABLE_SEL_INDEX_0 = 0x04, 950 SQ_CF_JUMPTABLE_SEL_INDEX_1 = 0x05, 951 SQ_CF_ALLOC_EXPORT_WORD0 = 0x00008dfc, 952/* ARRAY_BASE_mask = 0x1fff << 0, */ 953/* ARRAY_BASE_shift = 0, */ 954 SQ_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x03 << 13, 955 SQ_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13, 956/* SQ_EXPORT_PIXEL = 0x00, */ 957/* SQ_EXPORT_POS = 0x01, */ 958/* SQ_EXPORT_PARAM = 0x02, */ 959/* X_UNUSED_FOR_SX_EXPORTS = 0x03, */ 960/* RW_GPR_mask = 0x7f << 15, */ 961/* RW_GPR_shift = 15, */ 962/* RW_REL_bit = 1 << 22, */ 963/* INDEX_GPR_mask = 0x7f << 23, */ 964/* INDEX_GPR_shift = 23, */ 965 SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x03 << 30, 966 SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30, 967 SQ_MEM_GDS_WORD0 = 0x00008dfc, 968/* MEM_INST_mask = 0x1f << 0, */ 969/* MEM_INST_shift = 0, */ 970/* SQ_MEM_INST_MEM = 0x02, */ 971/* MEM_OP_mask = 0x07 << 8, */ 972/* MEM_OP_shift = 8, */ 973/* SQ_MEM_OP_RD_SCRATCH = 0x00, */ 974/* SQ_MEM_OP_RD_SCATTER = 0x02, */ 975/* SQ_MEM_OP_GDS = 0x04, */ 976/* SQ_MEM_OP_TF_WRITE = 0x05, */ 977 SQ_MEM_GDS_WORD0__SRC_GPR_mask = 0x7f << 11, 978 SQ_MEM_GDS_WORD0__SRC_GPR_shift = 11, 979 SRC_REL_MODE_mask = 0x03 << 18, 980 SRC_REL_MODE_shift = 18, 981/* SQ_REL_NONE = 0x00, */ 982/* SQ_REL_LOOP = 0x01, */ 983/* SQ_REL_GLOBAL = 0x02, */ 984 SQ_MEM_GDS_WORD0__SRC_SEL_X_mask = 0x07 << 20, 985 SQ_MEM_GDS_WORD0__SRC_SEL_X_shift = 20, 986/* SQ_SEL_X = 0x00, */ 987/* SQ_SEL_Y = 0x01, */ 988/* SQ_SEL_Z = 0x02, */ 989/* SQ_SEL_W = 0x03, */ 990/* SQ_SEL_0 = 0x04, */ 991/* SQ_SEL_1 = 0x05, */ 992 SQ_MEM_GDS_WORD0__SRC_SEL_Y_mask = 0x07 << 23, 993 SQ_MEM_GDS_WORD0__SRC_SEL_Y_shift = 23, 994/* SQ_SEL_X = 0x00, */ 995/* SQ_SEL_Y = 0x01, */ 996/* SQ_SEL_Z = 0x02, */ 997/* SQ_SEL_W = 0x03, */ 998/* SQ_SEL_0 = 0x04, */ 999/* SQ_SEL_1 = 0x05, */ 1000/* SRC_SEL_Z_mask = 0x07 << 26, */ 1001/* SRC_SEL_Z_shift = 26, */ 1002/* SQ_SEL_X = 0x00, */ 1003/* SQ_SEL_Y = 0x01, */ 1004/* SQ_SEL_Z = 0x02, */ 1005/* SQ_SEL_W = 0x03, */ 1006/* SQ_SEL_0 = 0x04, */ 1007/* SQ_SEL_1 = 0x05, */ 1008 SQ_ALU_WORD1_LDS_DIRECT_LITERAL_HI = 0x00008dfc, 1009 OFFSET_B_mask = 0x1fff << 0, 1010 OFFSET_B_shift = 0, 1011 STRIDE_B_mask = 0x7f << 13, 1012 STRIDE_B_shift = 13, 1013 THREAD_REL_B_bit = 1 << 22, 1014 DIRECT_READ_32_bit = 1 << 31, 1015 SQ_VTX_WORD1 = 0x00008dfc, 1016 SQ_VTX_WORD1__DST_SEL_X_mask = 0x07 << 9, 1017 SQ_VTX_WORD1__DST_SEL_X_shift = 9, 1018/* SQ_SEL_X = 0x00, */ 1019/* SQ_SEL_Y = 0x01, */ 1020/* SQ_SEL_Z = 0x02, */ 1021/* SQ_SEL_W = 0x03, */ 1022/* SQ_SEL_0 = 0x04, */ 1023/* SQ_SEL_1 = 0x05, */ 1024/* SQ_SEL_MASK = 0x07, */ 1025 SQ_VTX_WORD1__DST_SEL_Y_mask = 0x07 << 12, 1026 SQ_VTX_WORD1__DST_SEL_Y_shift = 12, 1027/* SQ_SEL_X = 0x00, */ 1028/* SQ_SEL_Y = 0x01, */ 1029/* SQ_SEL_Z = 0x02, */ 1030/* SQ_SEL_W = 0x03, */ 1031/* SQ_SEL_0 = 0x04, */ 1032/* SQ_SEL_1 = 0x05, */ 1033/* SQ_SEL_MASK = 0x07, */ 1034 SQ_VTX_WORD1__DST_SEL_Z_mask = 0x07 << 15, 1035 SQ_VTX_WORD1__DST_SEL_Z_shift = 15, 1036/* SQ_SEL_X = 0x00, */ 1037/* SQ_SEL_Y = 0x01, */ 1038/* SQ_SEL_Z = 0x02, */ 1039/* SQ_SEL_W = 0x03, */ 1040/* SQ_SEL_0 = 0x04, */ 1041/* SQ_SEL_1 = 0x05, */ 1042/* SQ_SEL_MASK = 0x07, */ 1043 SQ_VTX_WORD1__DST_SEL_W_mask = 0x07 << 18, 1044 SQ_VTX_WORD1__DST_SEL_W_shift = 18, 1045/* SQ_SEL_X = 0x00, */ 1046/* SQ_SEL_Y = 0x01, */ 1047/* SQ_SEL_Z = 0x02, */ 1048/* SQ_SEL_W = 0x03, */ 1049/* SQ_SEL_0 = 0x04, */ 1050/* SQ_SEL_1 = 0x05, */ 1051/* SQ_SEL_MASK = 0x07, */ 1052 USE_CONST_FIELDS_bit = 1 << 21, 1053 SQ_VTX_WORD1__DATA_FORMAT_mask = 0x3f << 22, 1054 SQ_VTX_WORD1__DATA_FORMAT_shift = 22, 1055 SQ_VTX_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, 1056 SQ_VTX_WORD1__NUM_FORMAT_ALL_shift = 28, 1057 SQ_NUM_FORMAT_NORM = 0x00, 1058 SQ_NUM_FORMAT_INT = 0x01, 1059 SQ_NUM_FORMAT_SCALED = 0x02, 1060 SQ_VTX_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, 1061 SQ_VTX_WORD1__SRF_MODE_ALL_bit = 1 << 31, 1062 SQ_ALU_WORD1_OP2 = 0x00008dfc, 1063 SRC0_ABS_bit = 1 << 0, 1064 SRC1_ABS_bit = 1 << 1, 1065 UPDATE_EXECUTE_MASK_bit = 1 << 2, 1066 UPDATE_PRED_bit = 1 << 3, 1067 WRITE_MASK_bit = 1 << 4, 1068 OMOD_mask = 0x03 << 5, 1069 OMOD_shift = 5, 1070 SQ_ALU_OMOD_OFF = 0x00, 1071 SQ_ALU_OMOD_M2 = 0x01, 1072 SQ_ALU_OMOD_M4 = 0x02, 1073 SQ_ALU_OMOD_D2 = 0x03, 1074 SQ_ALU_WORD1_OP2__ALU_INST_mask = 0x7ff << 7, 1075 SQ_ALU_WORD1_OP2__ALU_INST_shift = 7, 1076 SQ_OP2_INST_ADD = 0x00, 1077 SQ_OP2_INST_MUL = 0x01, 1078 SQ_OP2_INST_MUL_IEEE = 0x02, 1079 SQ_OP2_INST_MAX = 0x03, 1080 SQ_OP2_INST_MIN = 0x04, 1081 SQ_OP2_INST_MAX_DX10 = 0x05, 1082 SQ_OP2_INST_MIN_DX10 = 0x06, 1083 SQ_OP2_INST_SETE = 0x08, 1084 SQ_OP2_INST_SETGT = 0x09, 1085 SQ_OP2_INST_SETGE = 0x0a, 1086 SQ_OP2_INST_SETNE = 0x0b, 1087 SQ_OP2_INST_SETE_DX10 = 0x0c, 1088 SQ_OP2_INST_SETGT_DX10 = 0x0d, 1089 SQ_OP2_INST_SETGE_DX10 = 0x0e, 1090 SQ_OP2_INST_SETNE_DX10 = 0x0f, 1091 SQ_OP2_INST_FRACT = 0x10, 1092 SQ_OP2_INST_TRUNC = 0x11, 1093 SQ_OP2_INST_CEIL = 0x12, 1094 SQ_OP2_INST_RNDNE = 0x13, 1095 SQ_OP2_INST_FLOOR = 0x14, 1096 SQ_OP2_INST_ASHR_INT = 0x15, 1097 SQ_OP2_INST_LSHR_INT = 0x16, 1098 SQ_OP2_INST_LSHL_INT = 0x17, 1099 SQ_OP2_INST_MOV = 0x19, 1100 SQ_OP2_INST_NOP = 0x1a, 1101 SQ_OP2_INST_PRED_SETGT_UINT = 0x1e, 1102 SQ_OP2_INST_PRED_SETGE_UINT = 0x1f, 1103 SQ_OP2_INST_PRED_SETE = 0x20, 1104 SQ_OP2_INST_PRED_SETGT = 0x21, 1105 SQ_OP2_INST_PRED_SETGE = 0x22, 1106 SQ_OP2_INST_PRED_SETNE = 0x23, 1107 SQ_OP2_INST_PRED_SET_INV = 0x24, 1108 SQ_OP2_INST_PRED_SET_POP = 0x25, 1109 SQ_OP2_INST_PRED_SET_CLR = 0x26, 1110 SQ_OP2_INST_PRED_SET_RESTORE = 0x27, 1111 SQ_OP2_INST_PRED_SETE_PUSH = 0x28, 1112 SQ_OP2_INST_PRED_SETGT_PUSH = 0x29, 1113 SQ_OP2_INST_PRED_SETGE_PUSH = 0x2a, 1114 SQ_OP2_INST_PRED_SETNE_PUSH = 0x2b, 1115 SQ_OP2_INST_KILLE = 0x2c, 1116 SQ_OP2_INST_KILLGT = 0x2d, 1117 SQ_OP2_INST_KILLGE = 0x2e, 1118 SQ_OP2_INST_KILLNE = 0x2f, 1119 SQ_OP2_INST_AND_INT = 0x30, 1120 SQ_OP2_INST_OR_INT = 0x31, 1121 SQ_OP2_INST_XOR_INT = 0x32, 1122 SQ_OP2_INST_NOT_INT = 0x33, 1123 SQ_OP2_INST_ADD_INT = 0x34, 1124 SQ_OP2_INST_SUB_INT = 0x35, 1125 SQ_OP2_INST_MAX_INT = 0x36, 1126 SQ_OP2_INST_MIN_INT = 0x37, 1127 SQ_OP2_INST_MAX_UINT = 0x38, 1128 SQ_OP2_INST_MIN_UINT = 0x39, 1129 SQ_OP2_INST_SETE_INT = 0x3a, 1130 SQ_OP2_INST_SETGT_INT = 0x3b, 1131 SQ_OP2_INST_SETGE_INT = 0x3c, 1132 SQ_OP2_INST_SETNE_INT = 0x3d, 1133 SQ_OP2_INST_SETGT_UINT = 0x3e, 1134 SQ_OP2_INST_SETGE_UINT = 0x3f, 1135 SQ_OP2_INST_KILLGT_UINT = 0x40, 1136 SQ_OP2_INST_KILLGE_UINT = 0x41, 1137 SQ_OP2_INST_PRED_SETE_INT = 0x42, 1138 SQ_OP2_INST_PRED_SETGT_INT = 0x43, 1139 SQ_OP2_INST_PRED_SETGE_INT = 0x44, 1140 SQ_OP2_INST_PRED_SETNE_INT = 0x45, 1141 SQ_OP2_INST_KILLE_INT = 0x46, 1142 SQ_OP2_INST_KILLGT_INT = 0x47, 1143 SQ_OP2_INST_KILLGE_INT = 0x48, 1144 SQ_OP2_INST_KILLNE_INT = 0x49, 1145 SQ_OP2_INST_PRED_SETE_PUSH_INT = 0x4a, 1146 SQ_OP2_INST_PRED_SETGT_PUSH_INT = 0x4b, 1147 SQ_OP2_INST_PRED_SETGE_PUSH_INT = 0x4c, 1148 SQ_OP2_INST_PRED_SETNE_PUSH_INT = 0x4d, 1149 SQ_OP2_INST_PRED_SETLT_PUSH_INT = 0x4e, 1150 SQ_OP2_INST_PRED_SETLE_PUSH_INT = 0x4f, 1151 SQ_OP2_INST_FLT_TO_INT = 0x50, 1152 SQ_OP2_INST_BFREV_INT = 0x51, 1153 SQ_OP2_INST_ADDC_UINT = 0x52, 1154 SQ_OP2_INST_SUBB_UINT = 0x53, 1155 SQ_OP2_INST_GROUP_BARRIER = 0x54, 1156 SQ_OP2_INST_GROUP_SEQ_BEGIN = 0x55, 1157 SQ_OP2_INST_GROUP_SEQ_END = 0x56, 1158 SQ_OP2_INST_SET_MODE = 0x57, 1159 SQ_OP2_INST_SET_CF_IDX0 = 0x58, 1160 SQ_OP2_INST_SET_CF_IDX1 = 0x59, 1161 SQ_OP2_INST_SET_LDS_SIZE = 0x5a, 1162 SQ_OP2_INST_EXP_IEEE = 0x81, 1163 SQ_OP2_INST_LOG_CLAMPED = 0x82, 1164 SQ_OP2_INST_LOG_IEEE = 0x83, 1165 SQ_OP2_INST_RECIP_CLAMPED = 0x84, 1166 SQ_OP2_INST_RECIP_FF = 0x85, 1167 SQ_OP2_INST_RECIP_IEEE = 0x86, 1168 SQ_OP2_INST_RECIPSQRT_CLAMPED = 0x87, 1169 SQ_OP2_INST_RECIPSQRT_FF = 0x88, 1170 SQ_OP2_INST_RECIPSQRT_IEEE = 0x89, 1171 SQ_OP2_INST_SQRT_IEEE = 0x8a, 1172 SQ_OP2_INST_SIN = 0x8d, 1173 SQ_OP2_INST_COS = 0x8e, 1174 SQ_OP2_INST_MULLO_INT = 0x8f, 1175 SQ_OP2_INST_MULHI_INT = 0x90, 1176 SQ_OP2_INST_MULLO_UINT = 0x91, 1177 SQ_OP2_INST_MULHI_UINT = 0x92, 1178 SQ_OP2_INST_RECIP_INT = 0x93, 1179 SQ_OP2_INST_RECIP_UINT = 0x94, 1180 SQ_OP2_INST_RECIP_64 = 0x95, 1181 SQ_OP2_INST_RECIP_CLAMPED_64 = 0x96, 1182 SQ_OP2_INST_RECIPSQRT_64 = 0x97, 1183 SQ_OP2_INST_RECIPSQRT_CLAMPED_64 = 0x98, 1184 SQ_OP2_INST_SQRT_64 = 0x99, 1185 SQ_OP2_INST_FLT_TO_UINT = 0x9a, 1186 SQ_OP2_INST_INT_TO_FLT = 0x9b, 1187 SQ_OP2_INST_UINT_TO_FLT = 0x9c, 1188 SQ_OP2_INST_BFM_INT = 0xa0, 1189 SQ_OP2_INST_FLT32_TO_FLT16 = 0xa2, 1190 SQ_OP2_INST_FLT16_TO_FLT32 = 0xa3, 1191 SQ_OP2_INST_UBYTE0_FLT = 0xa4, 1192 SQ_OP2_INST_UBYTE1_FLT = 0xa5, 1193 SQ_OP2_INST_UBYTE2_FLT = 0xa6, 1194 SQ_OP2_INST_UBYTE3_FLT = 0xa7, 1195 SQ_OP2_INST_BCNT_INT = 0xaa, 1196 SQ_OP2_INST_FFBH_UINT = 0xab, 1197 SQ_OP2_INST_FFBL_INT = 0xac, 1198 SQ_OP2_INST_FFBH_INT = 0xad, 1199 SQ_OP2_INST_FLT_TO_UINT4 = 0xae, 1200 SQ_OP2_INST_DOT_IEEE = 0xaf, 1201 SQ_OP2_INST_FLT_TO_INT_RPI = 0xb0, 1202 SQ_OP2_INST_FLT_TO_INT_FLOOR = 0xb1, 1203 SQ_OP2_INST_MULHI_UINT24 = 0xb2, 1204 SQ_OP2_INST_MBCNT_32HI_INT = 0xb3, 1205 SQ_OP2_INST_OFFSET_TO_FLT = 0xb4, 1206 SQ_OP2_INST_MUL_UINT24 = 0xb5, 1207 SQ_OP2_INST_BCNT_ACCUM_PREV_INT = 0xb6, 1208 SQ_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 0xb7, 1209 SQ_OP2_INST_SETE_64 = 0xb8, 1210 SQ_OP2_INST_SETNE_64 = 0xb9, 1211 SQ_OP2_INST_SETGT_64 = 0xba, 1212 SQ_OP2_INST_SETGE_64 = 0xbb, 1213 SQ_OP2_INST_MIN_64 = 0xbc, 1214 SQ_OP2_INST_MAX_64 = 0xbd, 1215 SQ_OP2_INST_DOT4 = 0xbe, 1216 SQ_OP2_INST_DOT4_IEEE = 0xbf, 1217 SQ_OP2_INST_CUBE = 0xc0, 1218 SQ_OP2_INST_MAX4 = 0xc1, 1219 SQ_OP2_INST_FREXP_64 = 0xc4, 1220 SQ_OP2_INST_LDEXP_64 = 0xc5, 1221 SQ_OP2_INST_FRACT_64 = 0xc6, 1222 SQ_OP2_INST_PRED_SETGT_64 = 0xc7, 1223 SQ_OP2_INST_PRED_SETE_64 = 0xc8, 1224 SQ_OP2_INST_PRED_SETGE_64 = 0xc9, 1225 SQ_OP2_INST_MUL_64 = 0xca, 1226 SQ_OP2_INST_ADD_64 = 0xcb, 1227 SQ_OP2_INST_MOVA_INT = 0xcc, 1228 SQ_OP2_INST_FLT64_TO_FLT32 = 0xcd, 1229 SQ_OP2_INST_FLT32_TO_FLT64 = 0xce, 1230 SQ_OP2_INST_SAD_ACCUM_PREV_UINT = 0xcf, 1231 SQ_OP2_INST_DOT = 0xd0, 1232 SQ_OP2_INST_MUL_PREV = 0xd1, 1233 SQ_OP2_INST_MUL_IEEE_PREV = 0xd2, 1234 SQ_OP2_INST_ADD_PREV = 0xd3, 1235 SQ_OP2_INST_MULADD_PREV = 0xd4, 1236 SQ_OP2_INST_MULADD_IEEE_PREV = 0xd5, 1237 SQ_OP2_INST_INTERP_XY = 0xd6, 1238 SQ_OP2_INST_INTERP_ZW = 0xd7, 1239 SQ_OP2_INST_INTERP_X = 0xd8, 1240 SQ_OP2_INST_INTERP_Z = 0xd9, 1241 SQ_OP2_INST_STORE_FLAGS = 0xda, 1242 SQ_OP2_INST_LOAD_STORE_FLAGS = 0xdb, 1243 SQ_OP2_INST_INTERP_LOAD_P0 = 0xe0, 1244 SQ_OP2_INST_INTERP_LOAD_P10 = 0xe1, 1245 SQ_OP2_INST_INTERP_LOAD_P20 = 0xe2, 1246 SQ_CF_WORD1 = 0x00008dfc, 1247 POP_COUNT_mask = 0x07 << 0, 1248 POP_COUNT_shift = 0, 1249 CF_CONST_mask = 0x1f << 3, 1250 CF_CONST_shift = 3, 1251 COND_mask = 0x03 << 8, 1252 COND_shift = 8, 1253 SQ_CF_COND_ACTIVE = 0x00, 1254 SQ_CF_COND_FALSE = 0x01, 1255 SQ_CF_COND_BOOL = 0x02, 1256 SQ_CF_COND_NOT_BOOL = 0x03, 1257 SQ_CF_WORD1__COUNT_mask = 0x3f << 10, 1258 SQ_CF_WORD1__COUNT_shift = 10, 1259/* VALID_PIXEL_MODE_bit = 1 << 20, */ 1260 SQ_CF_WORD1__CF_INST_mask = 0xff << 22, 1261 SQ_CF_WORD1__CF_INST_shift = 22, 1262 SQ_CF_INST_NOP = 0x00, 1263 SQ_CF_INST_TC = 0x01, 1264 SQ_CF_INST_VC = 0x02, 1265 SQ_CF_INST_GDS = 0x03, 1266 SQ_CF_INST_LOOP_START = 0x04, 1267 SQ_CF_INST_LOOP_END = 0x05, 1268 SQ_CF_INST_LOOP_START_DX10 = 0x06, 1269 SQ_CF_INST_LOOP_START_NO_AL = 0x07, 1270 SQ_CF_INST_LOOP_CONTINUE = 0x08, 1271 SQ_CF_INST_LOOP_BREAK = 0x09, 1272 SQ_CF_INST_JUMP = 0x0a, 1273 SQ_CF_INST_PUSH = 0x0b, 1274 SQ_CF_INST_ELSE = 0x0d, 1275 SQ_CF_INST_POP = 0x0e, 1276 SQ_CF_INST_CALL = 0x12, 1277 SQ_CF_INST_CALL_FS = 0x13, 1278 SQ_CF_INST_RETURN = 0x14, 1279 SQ_CF_INST_EMIT_VERTEX = 0x15, 1280 SQ_CF_INST_EMIT_CUT_VERTEX = 0x16, 1281 SQ_CF_INST_CUT_VERTEX = 0x17, 1282 SQ_CF_INST_KILL = 0x18, 1283 SQ_CF_INST_WAIT_ACK = 0x1a, 1284 SQ_CF_INST_TC_ACK = 0x1b, 1285 SQ_CF_INST_VC_ACK = 0x1c, 1286 SQ_CF_INST_JUMPTABLE = 0x1d, 1287 SQ_CF_INST_GLOBAL_WAVE_SYNC = 0x1e, 1288 SQ_CF_INST_HALT = 0x1f, 1289 SQ_CF_INST_END = 0x20, 1290 SQ_CF_INST_LDS_DEALLOC = 0x21, 1291 SQ_CF_INST_PUSH_WQM = 0x22, 1292 SQ_CF_INST_POP_WQM = 0x23, 1293 SQ_CF_INST_ELSE_WQM = 0x24, 1294 SQ_CF_INST_JUMP_ANY = 0x25, 1295 SQ_CF_INST_REACTIVATE = 0x26, 1296 SQ_CF_INST_REACTIVATE_WQM = 0x27, 1297 SQ_CF_INST_INTERRUPT = 0x28, 1298 SQ_CF_INST_INTERRUPT_AND_SLEEP = 0x29, 1299 SQ_CF_INST_SET_PRIORITY = 0x2a, 1300/* BARRIER_bit = 1 << 31, */ 1301 SQ_VTX_WORD1_SEM = 0x00008dfc, 1302 SEMANTIC_ID_mask = 0xff << 0, 1303 SEMANTIC_ID_shift = 0, 1304 SQ_TEX_WORD0 = 0x00008dfc, 1305 TEX_INST_mask = 0x1f << 0, 1306 TEX_INST_shift = 0, 1307 SQ_TEX_INST_LD = 0x03, 1308 SQ_TEX_INST_GET_TEXTURE_RESINFO = 0x04, 1309 SQ_TEX_INST_GET_NUMBER_OF_SAMPLES = 0x05, 1310 SQ_TEX_INST_GET_LOD = 0x06, 1311 SQ_TEX_INST_GET_GRADIENTS_H = 0x07, 1312 SQ_TEX_INST_GET_GRADIENTS_V = 0x08, 1313 SQ_TEX_INST_SET_TEXTURE_OFFSETS = 0x09, 1314 SQ_TEX_INST_KEEP_GRADIENTS = 0x0a, 1315 SQ_TEX_INST_SET_GRADIENTS_H = 0x0b, 1316 SQ_TEX_INST_SET_GRADIENTS_V = 0x0c, 1317 SQ_TEX_INST_PASS = 0x0d, 1318 SQ_TEX_INST_SAMPLE = 0x10, 1319 SQ_TEX_INST_SAMPLE_L = 0x11, 1320 SQ_TEX_INST_SAMPLE_LB = 0x12, 1321 SQ_TEX_INST_SAMPLE_LZ = 0x13, 1322 SQ_TEX_INST_SAMPLE_G = 0x14, 1323 SQ_TEX_INST_GATHER4 = 0x15, 1324 SQ_TEX_INST_SAMPLE_G_LB = 0x16, 1325 SQ_TEX_INST_GATHER4_O = 0x17, 1326 SQ_TEX_INST_SAMPLE_C = 0x18, 1327 SQ_TEX_INST_SAMPLE_C_L = 0x19, 1328 SQ_TEX_INST_SAMPLE_C_LB = 0x1a, 1329 SQ_TEX_INST_SAMPLE_C_LZ = 0x1b, 1330 SQ_TEX_INST_SAMPLE_C_G = 0x1c, 1331 SQ_TEX_INST_GATHER4_C = 0x1d, 1332 SQ_TEX_INST_SAMPLE_C_G_LB = 0x1e, 1333 SQ_TEX_INST_GATHER4_C_O = 0x1f, 1334 INST_MOD_mask = 0x03 << 5, 1335 INST_MOD_shift = 5, 1336/* FETCH_WHOLE_QUAD_bit = 1 << 7, */ 1337 RESOURCE_ID_mask = 0xff << 8, 1338 RESOURCE_ID_shift = 8, 1339 SQ_TEX_WORD0__SRC_GPR_mask = 0x7f << 16, 1340 SQ_TEX_WORD0__SRC_GPR_shift = 16, 1341/* SRC_REL_bit = 1 << 23, */ 1342 SQ_TEX_WORD0__ALT_CONST_bit = 1 << 24, 1343 RESOURCE_INDEX_MODE_mask = 0x03 << 25, 1344 RESOURCE_INDEX_MODE_shift = 25, 1345/* SQ_CF_INDEX_NONE = 0x00, */ 1346/* SQ_CF_INDEX_0 = 0x01, */ 1347/* SQ_CF_INDEX_1 = 0x02, */ 1348/* SQ_CF_INVALID = 0x03, */ 1349 SAMPLER_INDEX_MODE_mask = 0x03 << 27, 1350 SAMPLER_INDEX_MODE_shift = 27, 1351/* SQ_CF_INDEX_NONE = 0x00, */ 1352/* SQ_CF_INDEX_0 = 0x01, */ 1353/* SQ_CF_INDEX_1 = 0x02, */ 1354/* SQ_CF_INVALID = 0x03, */ 1355 SQ_VTX_WORD1_GPR = 0x00008dfc, 1356 SQ_VTX_WORD1_GPR__DST_GPR_mask = 0x7f << 0, 1357 SQ_VTX_WORD1_GPR__DST_GPR_shift = 0, 1358 SQ_VTX_WORD1_GPR__DST_REL_bit = 1 << 7, 1359 SQ_ALU_WORD1_LDS_IDX_OP = 0x00008dfc, 1360/* SRC2_SEL_mask = 0x1ff << 0, */ 1361/* SRC2_SEL_shift = 0, */ 1362/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 1363/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 1364/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 1365/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 1366/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 1367/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 1368/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 1369/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 1370/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 1371/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 1372/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 1373/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 1374/* SQ_ALU_SRC_SE_ID = 0xe9, */ 1375/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 1376/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 1377/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 1378/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 1379/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 1380/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 1381/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 1382/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 1383/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 1384/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 1385/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 1386/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 1387/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 1388/* SQ_ALU_SRC_0 = 0xf8, */ 1389/* SQ_ALU_SRC_1 = 0xf9, */ 1390/* SQ_ALU_SRC_1_INT = 0xfa, */ 1391/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 1392/* SQ_ALU_SRC_0_5 = 0xfc, */ 1393/* SQ_ALU_SRC_LITERAL = 0xfd, */ 1394/* SQ_ALU_SRC_PV = 0xfe, */ 1395/* SQ_ALU_SRC_PS = 0xff, */ 1396/* SRC2_REL_bit = 1 << 9, */ 1397/* SRC2_CHAN_mask = 0x03 << 10, */ 1398/* SRC2_CHAN_shift = 10, */ 1399/* SQ_CHAN_X = 0x00, */ 1400/* SQ_CHAN_Y = 0x01, */ 1401/* SQ_CHAN_Z = 0x02, */ 1402/* SQ_CHAN_W = 0x03, */ 1403 IDX_OFFSET_1_bit = 1 << 12, 1404 SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_mask = 0x1f << 13, 1405 SQ_ALU_WORD1_LDS_IDX_OP__ALU_INST_shift = 13, 1406/* SQ_OP3_INST_BFE_UINT = 0x04, */ 1407/* SQ_OP3_INST_BFE_INT = 0x05, */ 1408/* SQ_OP3_INST_BFI_INT = 0x06, */ 1409/* SQ_OP3_INST_FMA = 0x07, */ 1410/* SQ_OP3_INST_CNDNE_64 = 0x09, */ 1411/* SQ_OP3_INST_FMA_64 = 0x0a, */ 1412/* SQ_OP3_INST_LERP_UINT = 0x0b, */ 1413/* SQ_OP3_INST_BIT_ALIGN_INT = 0x0c, */ 1414/* SQ_OP3_INST_BYTE_ALIGN_INT = 0x0d, */ 1415/* SQ_OP3_INST_SAD_ACCUM_UINT = 0x0e, */ 1416/* SQ_OP3_INST_SAD_ACCUM_HI_UINT = 0x0f, */ 1417/* SQ_OP3_INST_MULADD_UINT24 = 0x10, */ 1418/* SQ_OP3_INST_LDS_IDX_OP = 0x11, */ 1419/* SQ_OP3_INST_MULADD = 0x14, */ 1420/* SQ_OP3_INST_MULADD_M2 = 0x15, */ 1421/* SQ_OP3_INST_MULADD_M4 = 0x16, */ 1422/* SQ_OP3_INST_MULADD_D2 = 0x17, */ 1423/* SQ_OP3_INST_MULADD_IEEE = 0x18, */ 1424/* SQ_OP3_INST_CNDE = 0x19, */ 1425/* SQ_OP3_INST_CNDGT = 0x1a, */ 1426/* SQ_OP3_INST_CNDGE = 0x1b, */ 1427/* SQ_OP3_INST_CNDE_INT = 0x1c, */ 1428/* SQ_OP3_INST_CNDGT_INT = 0x1d, */ 1429/* SQ_OP3_INST_CNDGE_INT = 0x1e, */ 1430/* SQ_OP3_INST_MUL_LIT = 0x1f, */ 1431/* BANK_SWIZZLE_mask = 0x07 << 18, */ 1432/* BANK_SWIZZLE_shift = 18, */ 1433/* SQ_ALU_VEC_012 = 0x00, */ 1434/* SQ_ALU_VEC_021 = 0x01, */ 1435/* SQ_ALU_VEC_120 = 0x02, */ 1436/* SQ_ALU_VEC_102 = 0x03, */ 1437/* SQ_ALU_VEC_201 = 0x04, */ 1438/* SQ_ALU_VEC_210 = 0x05, */ 1439 LDS_OP_mask = 0x3f << 21, 1440 LDS_OP_shift = 21, 1441/* SQ_DS_INST_ADD = 0x00, */ 1442/* SQ_DS_INST_SUB = 0x01, */ 1443/* SQ_DS_INST_RSUB = 0x02, */ 1444/* SQ_DS_INST_INC = 0x03, */ 1445/* SQ_DS_INST_DEC = 0x04, */ 1446/* SQ_DS_INST_MIN_INT = 0x05, */ 1447/* SQ_DS_INST_MAX_INT = 0x06, */ 1448/* SQ_DS_INST_MIN_UINT = 0x07, */ 1449/* SQ_DS_INST_MAX_UINT = 0x08, */ 1450/* SQ_DS_INST_AND = 0x09, */ 1451/* SQ_DS_INST_OR = 0x0a, */ 1452/* SQ_DS_INST_XOR = 0x0b, */ 1453/* SQ_DS_INST_MSKOR = 0x0c, */ 1454/* SQ_DS_INST_WRITE = 0x0d, */ 1455/* SQ_DS_INST_WRITE_REL = 0x0e, */ 1456/* SQ_DS_INST_WRITE2 = 0x0f, */ 1457/* SQ_DS_INST_CMP_STORE = 0x10, */ 1458/* SQ_DS_INST_CMP_STORE_SPF = 0x11, */ 1459/* SQ_DS_INST_BYTE_WRITE = 0x12, */ 1460/* SQ_DS_INST_SHORT_WRITE = 0x13, */ 1461/* SQ_DS_INST_ADD_RET = 0x20, */ 1462/* SQ_DS_INST_SUB_RET = 0x21, */ 1463/* SQ_DS_INST_RSUB_RET = 0x22, */ 1464/* SQ_DS_INST_INC_RET = 0x23, */ 1465/* SQ_DS_INST_DEC_RET = 0x24, */ 1466/* SQ_DS_INST_MIN_INT_RET = 0x25, */ 1467/* SQ_DS_INST_MAX_INT_RET = 0x26, */ 1468/* SQ_DS_INST_MIN_UINT_RET = 0x27, */ 1469/* SQ_DS_INST_MAX_UINT_RET = 0x28, */ 1470/* SQ_DS_INST_AND_RET = 0x29, */ 1471/* SQ_DS_INST_OR_RET = 0x2a, */ 1472/* SQ_DS_INST_XOR_RET = 0x2b, */ 1473/* SQ_DS_INST_MSKOR_RET = 0x2c, */ 1474/* SQ_DS_INST_XCHG_RET = 0x2d, */ 1475/* SQ_DS_INST_XCHG_REL_RET = 0x2e, */ 1476/* SQ_DS_INST_XCHG2_RET = 0x2f, */ 1477/* SQ_DS_INST_CMP_XCHG_RET = 0x30, */ 1478/* SQ_DS_INST_CMP_XCHG_SPF_RET = 0x31, */ 1479/* SQ_DS_INST_READ_RET = 0x32, */ 1480/* SQ_DS_INST_READ_REL_RET = 0x33, */ 1481/* SQ_DS_INST_READ2_RET = 0x34, */ 1482/* SQ_DS_INST_READWRITE_RET = 0x35, */ 1483/* SQ_DS_INST_BYTE_READ_RET = 0x36, */ 1484/* SQ_DS_INST_UBYTE_READ_RET = 0x37, */ 1485/* SQ_DS_INST_SHORT_READ_RET = 0x38, */ 1486/* SQ_DS_INST_USHORT_READ_RET = 0x39, */ 1487/* SQ_DS_INST_ATOMIC_ORDERED_ALLOC_RET = 0x3f, */ 1488 IDX_OFFSET_0_bit = 1 << 27, 1489 IDX_OFFSET_2_bit = 1 << 28, 1490/* DST_CHAN_mask = 0x03 << 29, */ 1491/* DST_CHAN_shift = 29, */ 1492/* CHAN_X = 0x00, */ 1493/* CHAN_Y = 0x01, */ 1494/* CHAN_Z = 0x02, */ 1495/* CHAN_W = 0x03, */ 1496 IDX_OFFSET_3_bit = 1 << 31, 1497 SQ_CF_ENCODING_WORD1 = 0x00008dfc, 1498 SQ_CF_ENCODING_WORD1__ENCODING_mask = 0x03 << 28, 1499 SQ_CF_ENCODING_WORD1__ENCODING_shift = 28, 1500 SQ_CF_ENCODING_INST_CF = 0x00, 1501 SQ_CF_ENCODING_INST_ALLOC_EXPORT = 0x01, 1502 SQ_CF_ENCODING_INST_ALU0 = 0x02, 1503 SQ_CF_ENCODING_INST_ALU1 = 0x03, 1504 SQ_ALU_WORD0 = 0x00008dfc, 1505/* SRC0_SEL_mask = 0x1ff << 0, */ 1506/* SRC0_SEL_shift = 0, */ 1507/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 1508/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 1509/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 1510/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 1511/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 1512/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 1513/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 1514/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 1515/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 1516/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 1517/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 1518/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 1519/* SQ_ALU_SRC_SE_ID = 0xe9, */ 1520/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 1521/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 1522/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 1523/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 1524/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 1525/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 1526/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 1527/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 1528/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 1529/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 1530/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 1531/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 1532/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 1533/* SQ_ALU_SRC_0 = 0xf8, */ 1534/* SQ_ALU_SRC_1 = 0xf9, */ 1535/* SQ_ALU_SRC_1_INT = 0xfa, */ 1536/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 1537/* SQ_ALU_SRC_0_5 = 0xfc, */ 1538/* SQ_ALU_SRC_LITERAL = 0xfd, */ 1539/* SQ_ALU_SRC_PV = 0xfe, */ 1540/* SQ_ALU_SRC_PS = 0xff, */ 1541/* SRC0_REL_bit = 1 << 9, */ 1542/* SRC0_CHAN_mask = 0x03 << 10, */ 1543/* SRC0_CHAN_shift = 10, */ 1544/* SQ_CHAN_X = 0x00, */ 1545/* SQ_CHAN_Y = 0x01, */ 1546/* SQ_CHAN_Z = 0x02, */ 1547/* SQ_CHAN_W = 0x03, */ 1548 SRC0_NEG_bit = 1 << 12, 1549/* SRC1_SEL_mask = 0x1ff << 13, */ 1550/* SRC1_SEL_shift = 13, */ 1551/* SQ_ALU_SRC_LDS_OQ_A = 0xdb, */ 1552/* SQ_ALU_SRC_LDS_OQ_B = 0xdc, */ 1553/* SQ_ALU_SRC_LDS_OQ_A_POP = 0xdd, */ 1554/* SQ_ALU_SRC_LDS_OQ_B_POP = 0xde, */ 1555/* SQ_ALU_SRC_LDS_DIRECT_A = 0xdf, */ 1556/* SQ_ALU_SRC_LDS_DIRECT_B = 0xe0, */ 1557/* SQ_ALU_SRC_TIME_HI = 0xe3, */ 1558/* SQ_ALU_SRC_TIME_LO = 0xe4, */ 1559/* SQ_ALU_SRC_MASK_HI = 0xe5, */ 1560/* SQ_ALU_SRC_MASK_LO = 0xe6, */ 1561/* SQ_ALU_SRC_HW_WAVE_ID = 0xe7, */ 1562/* SQ_ALU_SRC_SIMD_ID = 0xe8, */ 1563/* SQ_ALU_SRC_SE_ID = 0xe9, */ 1564/* SQ_ALU_SRC_HW_THREADGRP_ID = 0xea, */ 1565/* SQ_ALU_SRC_WAVE_ID_IN_GRP = 0xeb, */ 1566/* SQ_ALU_SRC_NUM_THREADGRP_WAVES = 0xec, */ 1567/* SQ_ALU_SRC_HW_ALU_ODD = 0xed, */ 1568/* SQ_ALU_SRC_LOOP_IDX = 0xee, */ 1569/* SQ_ALU_SRC_PARAM_BASE_ADDR = 0xf0, */ 1570/* SQ_ALU_SRC_NEW_PRIM_MASK = 0xf1, */ 1571/* SQ_ALU_SRC_PRIM_MASK_HI = 0xf2, */ 1572/* SQ_ALU_SRC_PRIM_MASK_LO = 0xf3, */ 1573/* SQ_ALU_SRC_1_DBL_L = 0xf4, */ 1574/* SQ_ALU_SRC_1_DBL_M = 0xf5, */ 1575/* SQ_ALU_SRC_0_5_DBL_L = 0xf6, */ 1576/* SQ_ALU_SRC_0_5_DBL_M = 0xf7, */ 1577/* SQ_ALU_SRC_0 = 0xf8, */ 1578/* SQ_ALU_SRC_1 = 0xf9, */ 1579/* SQ_ALU_SRC_1_INT = 0xfa, */ 1580/* SQ_ALU_SRC_M_1_INT = 0xfb, */ 1581/* SQ_ALU_SRC_0_5 = 0xfc, */ 1582/* SQ_ALU_SRC_LITERAL = 0xfd, */ 1583/* SQ_ALU_SRC_PV = 0xfe, */ 1584/* SQ_ALU_SRC_PS = 0xff, */ 1585/* SRC1_REL_bit = 1 << 22, */ 1586/* SRC1_CHAN_mask = 0x03 << 23, */ 1587/* SRC1_CHAN_shift = 23, */ 1588/* SQ_CHAN_X = 0x00, */ 1589/* SQ_CHAN_Y = 0x01, */ 1590/* SQ_CHAN_Z = 0x02, */ 1591/* SQ_CHAN_W = 0x03, */ 1592 SRC1_NEG_bit = 1 << 25, 1593/* INDEX_MODE_mask = 0x07 << 26, */ 1594/* INDEX_MODE_shift = 26, */ 1595/* SQ_INDEX_AR_X = 0x00, */ 1596/* SQ_INDEX_LOOP = 0x04, */ 1597/* SQ_INDEX_GLOBAL = 0x05, */ 1598/* SQ_INDEX_GLOBAL_AR_X = 0x06, */ 1599/* PRED_SEL_mask = 0x03 << 29, */ 1600/* PRED_SEL_shift = 29, */ 1601/* SQ_PRED_SEL_OFF = 0x00, */ 1602/* SQ_PRED_SEL_ZERO = 0x02, */ 1603/* SQ_PRED_SEL_ONE = 0x03, */ 1604/* LAST_bit = 1 << 31, */ 1605 SQ_MEM_RD_WORD1 = 0x00008dfc, 1606 SQ_MEM_RD_WORD1__DST_GPR_mask = 0x7f << 0, 1607 SQ_MEM_RD_WORD1__DST_GPR_shift = 0, 1608 SQ_MEM_RD_WORD1__DST_REL_bit = 1 << 7, 1609 SQ_MEM_RD_WORD1__DST_SEL_X_mask = 0x07 << 9, 1610 SQ_MEM_RD_WORD1__DST_SEL_X_shift = 9, 1611/* SQ_SEL_X = 0x00, */ 1612/* SQ_SEL_Y = 0x01, */ 1613/* SQ_SEL_Z = 0x02, */ 1614/* SQ_SEL_W = 0x03, */ 1615/* SQ_SEL_0 = 0x04, */ 1616/* SQ_SEL_1 = 0x05, */ 1617/* SQ_SEL_MASK = 0x07, */ 1618 SQ_MEM_RD_WORD1__DST_SEL_Y_mask = 0x07 << 12, 1619 SQ_MEM_RD_WORD1__DST_SEL_Y_shift = 12, 1620/* SQ_SEL_X = 0x00, */ 1621/* SQ_SEL_Y = 0x01, */ 1622/* SQ_SEL_Z = 0x02, */ 1623/* SQ_SEL_W = 0x03, */ 1624/* SQ_SEL_0 = 0x04, */ 1625/* SQ_SEL_1 = 0x05, */ 1626/* SQ_SEL_MASK = 0x07, */ 1627 SQ_MEM_RD_WORD1__DST_SEL_Z_mask = 0x07 << 15, 1628 SQ_MEM_RD_WORD1__DST_SEL_Z_shift = 15, 1629/* SQ_SEL_X = 0x00, */ 1630/* SQ_SEL_Y = 0x01, */ 1631/* SQ_SEL_Z = 0x02, */ 1632/* SQ_SEL_W = 0x03, */ 1633/* SQ_SEL_0 = 0x04, */ 1634/* SQ_SEL_1 = 0x05, */ 1635/* SQ_SEL_MASK = 0x07, */ 1636 SQ_MEM_RD_WORD1__DST_SEL_W_mask = 0x07 << 18, 1637 SQ_MEM_RD_WORD1__DST_SEL_W_shift = 18, 1638/* SQ_SEL_X = 0x00, */ 1639/* SQ_SEL_Y = 0x01, */ 1640/* SQ_SEL_Z = 0x02, */ 1641/* SQ_SEL_W = 0x03, */ 1642/* SQ_SEL_0 = 0x04, */ 1643/* SQ_SEL_1 = 0x05, */ 1644/* SQ_SEL_MASK = 0x07, */ 1645 SQ_MEM_RD_WORD1__DATA_FORMAT_mask = 0x3f << 22, 1646 SQ_MEM_RD_WORD1__DATA_FORMAT_shift = 22, 1647 SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_mask = 0x03 << 28, 1648 SQ_MEM_RD_WORD1__NUM_FORMAT_ALL_shift = 28, 1649/* SQ_NUM_FORMAT_NORM = 0x00, */ 1650/* SQ_NUM_FORMAT_INT = 0x01, */ 1651/* SQ_NUM_FORMAT_SCALED = 0x02, */ 1652 SQ_MEM_RD_WORD1__FORMAT_COMP_ALL_bit = 1 << 30, 1653 SQ_MEM_RD_WORD1__SRF_MODE_ALL_bit = 1 << 31, 1654 SQ_LSTMP_RING_BASE = 0x00008e10, 1655 SQ_LSTMP_RING_SIZE = 0x00008e14, 1656 SQ_HSTMP_RING_BASE = 0x00008e18, 1657 SQ_HSTMP_RING_SIZE = 0x00008e1c, 1658 SQ_EX_ALLOC_TABLE_SLOTS = 0x00008e48, 1659 PIX_SLOTS_mask = 0x7f << 0, 1660 PIX_SLOTS_shift = 0, 1661 POS_SLOTS_mask = 0x7f << 8, 1662 POS_SLOTS_shift = 8, 1663 SMX_SLOTS_mask = 0x7f << 16, 1664 SMX_SLOTS_shift = 16, 1665 SX_EXPORT_BUFFER_SIZES = 0x0000900c, 1666 COLOR_BUFFER_SIZE_mask = 0xff << 0, 1667 COLOR_BUFFER_SIZE_shift = 0, 1668 POSITION_BUFFER_SIZE_mask = 0xff << 8, 1669 POSITION_BUFFER_SIZE_shift = 8, 1670 SMX_BUFFER_SIZE_mask = 0xff << 16, 1671 SMX_BUFFER_SIZE_shift = 16, 1672 SX_MEMORY_EXPORT_BASE = 0x00009010, 1673 SX_MEMORY_EXPORT_SIZE = 0x00009014, 1674 SPI_CONFIG_CNTL = 0x00009100, 1675 GPR_WRITE_PRIORITY_mask = 0x3ffff << 0, 1676 GPR_WRITE_PRIORITY_shift = 0, 1677 SPI_CONFIG_CNTL_1 = 0x0000913c, 1678 VTX_DONE_DELAY_mask = 0x0f << 0, 1679 VTX_DONE_DELAY_shift = 0, 1680 X_DELAY_14_CLKS = 0x00, 1681 X_DELAY_16_CLKS = 0x01, 1682 X_DELAY_18_CLKS = 0x02, 1683 X_DELAY_20_CLKS = 0x03, 1684 X_DELAY_22_CLKS = 0x04, 1685 X_DELAY_24_CLKS = 0x05, 1686 X_DELAY_26_CLKS = 0x06, 1687 X_DELAY_28_CLKS = 0x07, 1688 X_DELAY_30_CLKS = 0x08, 1689 X_DELAY_32_CLKS = 0x09, 1690 X_DELAY_34_CLKS = 0x0a, 1691 X_DELAY_4_CLKS = 0x0b, 1692 X_DELAY_6_CLKS = 0x0c, 1693 X_DELAY_8_CLKS = 0x0d, 1694 X_DELAY_10_CLKS = 0x0e, 1695 X_DELAY_12_CLKS = 0x0f, 1696 INTERP_ONE_PRIM_PER_ROW_bit = 1 << 4, 1697 BC_OPTIMIZE_DISABLE_bit = 1 << 5, 1698 PC_LIMIT_ENABLE_bit = 1 << 6, 1699 PC_LIMIT_STRICT_bit = 1 << 7, 1700 PC_LIMIT_SIZE_mask = 0xffff << 16, 1701 PC_LIMIT_SIZE_shift = 16, 1702 TD_CNTL = 0x00009494, 1703 SYNC_PHASE_SH_mask = 0x03 << 0, 1704 SYNC_PHASE_SH_shift = 0, 1705 PAD_STALL_EN_bit = 1 << 8, 1706 EXTEND_LDS_STALL_mask = 0x03 << 9, 1707 EXTEND_LDS_STALL_shift = 9, 1708 X_0 = 0x00, 1709 EXTEND_LDS_STALL__X_1 = 0x01, 1710 X_2 = 0x02, 1711 X_3 = 0x03, 1712 GATHER4_FLOAT_MODE_bit = 1 << 16, 1713 LD_FLOAT_MODE_bit = 1 << 18, 1714 GATHER4_DX9_MODE_bit = 1 << 19, 1715 TD_STATUS = 0x00009498, 1716 BUSY_bit = 1 << 31, 1717 DB_SUBTILE_CONTROL = 0x00009858, 1718 MSAA1_X_mask = 0x03 << 0, 1719 MSAA1_X_shift = 0, 1720 MSAA1_Y_mask = 0x03 << 2, 1721 MSAA1_Y_shift = 2, 1722 MSAA2_X_mask = 0x03 << 4, 1723 MSAA2_X_shift = 4, 1724 MSAA2_Y_mask = 0x03 << 6, 1725 MSAA2_Y_shift = 6, 1726 MSAA4_X_mask = 0x03 << 8, 1727 MSAA4_X_shift = 8, 1728 MSAA4_Y_mask = 0x03 << 10, 1729 MSAA4_Y_shift = 10, 1730 MSAA8_X_mask = 0x03 << 12, 1731 MSAA8_X_shift = 12, 1732 MSAA8_Y_mask = 0x03 << 14, 1733 MSAA8_Y_shift = 14, 1734 MSAA16_X_mask = 0x03 << 16, 1735 MSAA16_X_shift = 16, 1736 MSAA16_Y_mask = 0x03 << 18, 1737 MSAA16_Y_shift = 18, 1738 DB_ZPASS_COUNT_LOW = 0x00009870, 1739 DB_ZPASS_COUNT_HI = 0x00009874, 1740 COUNT_HI_mask = 0x7fffffff << 0, 1741 COUNT_HI_shift = 0, 1742 TD_PS_BORDER_COLOR_INDEX = 0x0000a400, 1743 INDEX_mask = 0x1f << 0, 1744 INDEX_shift = 0, 1745 TD_PS_BORDER_COLOR_RED = 0x0000a404, 1746 TD_PS_BORDER_COLOR_GREEN = 0x0000a408, 1747 TD_PS_BORDER_COLOR_BLUE = 0x0000a40c, 1748 TD_PS_BORDER_COLOR_ALPHA = 0x0000a410, 1749 TD_VS_BORDER_COLOR_INDEX = 0x0000a414, 1750/* INDEX_mask = 0x1f << 0, */ 1751/* INDEX_shift = 0, */ 1752 TD_VS_BORDER_COLOR_RED = 0x0000a418, 1753 TD_VS_BORDER_COLOR_GREEN = 0x0000a41c, 1754 TD_VS_BORDER_COLOR_BLUE = 0x0000a420, 1755 TD_VS_BORDER_COLOR_ALPHA = 0x0000a424, 1756 TD_GS_BORDER_COLOR_INDEX = 0x0000a428, 1757/* INDEX_mask = 0x1f << 0, */ 1758/* INDEX_shift = 0, */ 1759 TD_GS_BORDER_COLOR_RED = 0x0000a42c, 1760 TD_GS_BORDER_COLOR_GREEN = 0x0000a430, 1761 TD_GS_BORDER_COLOR_BLUE = 0x0000a434, 1762 TD_GS_BORDER_COLOR_ALPHA = 0x0000a438, 1763 TD_HS_BORDER_COLOR_INDEX = 0x0000a43c, 1764/* INDEX_mask = 0x1f << 0, */ 1765/* INDEX_shift = 0, */ 1766 TD_HS_BORDER_COLOR_RED = 0x0000a440, 1767 TD_HS_BORDER_COLOR_GREEN = 0x0000a444, 1768 TD_HS_BORDER_COLOR_BLUE = 0x0000a448, 1769 TD_HS_BORDER_COLOR_ALPHA = 0x0000a44c, 1770 TD_LS_BORDER_COLOR_INDEX = 0x0000a450, 1771/* INDEX_mask = 0x1f << 0, */ 1772/* INDEX_shift = 0, */ 1773 TD_LS_BORDER_COLOR_RED = 0x0000a454, 1774 TD_LS_BORDER_COLOR_GREEN = 0x0000a458, 1775 TD_LS_BORDER_COLOR_BLUE = 0x0000a45c, 1776 TD_LS_BORDER_COLOR_ALPHA = 0x0000a460, 1777 TD_CS_BORDER_COLOR_INDEX = 0x0000a464, 1778/* INDEX_mask = 0x1f << 0, */ 1779/* INDEX_shift = 0, */ 1780 TD_CS_BORDER_COLOR_RED = 0x0000a468, 1781 TD_CS_BORDER_COLOR_GREEN = 0x0000a46c, 1782 TD_CS_BORDER_COLOR_BLUE = 0x0000a470, 1783 TD_CS_BORDER_COLOR_ALPHA = 0x0000a474, 1784 DB_RENDER_CONTROL = 0x00028000, 1785 DEPTH_CLEAR_ENABLE_bit = 1 << 0, 1786 STENCIL_CLEAR_ENABLE_bit = 1 << 1, 1787 DEPTH_COPY_bit = 1 << 2, 1788 STENCIL_COPY_bit = 1 << 3, 1789 RESUMMARIZE_ENABLE_bit = 1 << 4, 1790 STENCIL_COMPRESS_DISABLE_bit = 1 << 5, 1791 DEPTH_COMPRESS_DISABLE_bit = 1 << 6, 1792 COPY_CENTROID_bit = 1 << 7, 1793 COPY_SAMPLE_mask = 0x0f << 8, 1794 COPY_SAMPLE_shift = 8, 1795 DB_COUNT_CONTROL = 0x00028004, 1796 ZPASS_INCREMENT_DISABLE_bit = 1 << 0, 1797 PERFECT_ZPASS_COUNTS_bit = 1 << 1, 1798 SAMPLE_RATE_mask = 0x07 << 4, 1799 SAMPLE_RATE_shift = 4, 1800 DB_DEPTH_VIEW = 0x00028008, 1801 SLICE_START_mask = 0x7ff << 0, 1802 SLICE_START_shift = 0, 1803 SLICE_MAX_mask = 0x7ff << 13, 1804 SLICE_MAX_shift = 13, 1805 Z_READ_ONLY_bit = 1 << 24, 1806 STENCIL_READ_ONLY_bit = 1 << 25, 1807 DB_RENDER_OVERRIDE = 0x0002800c, 1808 FORCE_HIZ_ENABLE_mask = 0x03 << 0, 1809 FORCE_HIZ_ENABLE_shift = 0, 1810 FORCE_OFF = 0x00, 1811 FORCE_ENABLE = 0x01, 1812 FORCE_DISABLE = 0x02, 1813 FORCE_RESERVED = 0x03, 1814 FORCE_HIS_ENABLE0_mask = 0x03 << 2, 1815 FORCE_HIS_ENABLE0_shift = 2, 1816/* FORCE_OFF = 0x00, */ 1817/* FORCE_ENABLE = 0x01, */ 1818/* FORCE_DISABLE = 0x02, */ 1819/* FORCE_RESERVED = 0x03, */ 1820 FORCE_HIS_ENABLE1_mask = 0x03 << 4, 1821 FORCE_HIS_ENABLE1_shift = 4, 1822/* FORCE_OFF = 0x00, */ 1823/* FORCE_ENABLE = 0x01, */ 1824/* FORCE_DISABLE = 0x02, */ 1825/* FORCE_RESERVED = 0x03, */ 1826 FORCE_SHADER_Z_ORDER_bit = 1 << 6, 1827 FAST_Z_DISABLE_bit = 1 << 7, 1828 FAST_STENCIL_DISABLE_bit = 1 << 8, 1829 NOOP_CULL_DISABLE_bit = 1 << 9, 1830 FORCE_COLOR_KILL_bit = 1 << 10, 1831 FORCE_Z_READ_bit = 1 << 11, 1832 FORCE_STENCIL_READ_bit = 1 << 12, 1833 FORCE_FULL_Z_RANGE_mask = 0x03 << 13, 1834 FORCE_FULL_Z_RANGE_shift = 13, 1835/* FORCE_OFF = 0x00, */ 1836/* FORCE_ENABLE = 0x01, */ 1837/* FORCE_DISABLE = 0x02, */ 1838/* FORCE_RESERVED = 0x03, */ 1839 FORCE_QC_SMASK_CONFLICT_bit = 1 << 15, 1840 DISABLE_VIEWPORT_CLAMP_bit = 1 << 16, 1841 IGNORE_SC_ZRANGE_bit = 1 << 17, 1842 DISABLE_FULLY_COVERED_bit = 1 << 18, 1843 FORCE_Z_LIMIT_SUMM_mask = 0x03 << 19, 1844 FORCE_Z_LIMIT_SUMM_shift = 19, 1845 FORCE_SUMM_OFF = 0x00, 1846 FORCE_SUMM_MINZ = 0x01, 1847 FORCE_SUMM_MAXZ = 0x02, 1848 FORCE_SUMM_BOTH = 0x03, 1849 MAX_TILES_IN_DTT_mask = 0x1f << 21, 1850 MAX_TILES_IN_DTT_shift = 21, 1851 DISABLE_TILE_RATE_TILES_bit = 1 << 26, 1852 FORCE_Z_DIRTY_bit = 1 << 27, 1853 FORCE_STENCIL_DIRTY_bit = 1 << 28, 1854 FORCE_Z_VALID_bit = 1 << 29, 1855 FORCE_STENCIL_VALID_bit = 1 << 30, 1856 PRESERVE_COMPRESSION_bit = 1 << 31, 1857 DB_RENDER_OVERRIDE2 = 0x00028010, 1858 PARTIAL_SQUAD_LAUNCH_CONTROL_mask = 0x03 << 0, 1859 PARTIAL_SQUAD_LAUNCH_CONTROL_shift = 0, 1860 PSLC_AUTO = 0x00, 1861 PSLC_ON_HANG_ONLY = 0x01, 1862 PSLC_ASAP = 0x02, 1863 PSLC_COUNTDOWN = 0x03, 1864 PARTIAL_SQUAD_LAUNCH_COUNTDOWN_mask = 0x07 << 2, 1865 PARTIAL_SQUAD_LAUNCH_COUNTDOWN_shift = 2, 1866 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATIO_bit = 1 << 5, 1867 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_bit = 1 << 6, 1868 DISABLE_COLOR_ON_VALIDATION_bit = 1 << 7, 1869 DECOMPRESS_Z_ON_FLUSH_bit = 1 << 8, 1870 DB_HTILE_DATA_BASE = 0x00028014, 1871 DB_STENCIL_CLEAR = 0x00028028, 1872 DB_STENCIL_CLEAR__CLEAR_mask = 0xff << 0, 1873 DB_STENCIL_CLEAR__CLEAR_shift = 0, 1874 DB_DEPTH_CLEAR = 0x0002802c, 1875 PA_SC_SCREEN_SCISSOR_TL = 0x00028030, 1876 PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0, 1877 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift = 0, 1878 PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16, 1879 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift = 16, 1880 PA_SC_SCREEN_SCISSOR_BR = 0x00028034, 1881 PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0, 1882 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift = 0, 1883 PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16, 1884 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift = 16, 1885 DB_DEPTH_INFO = 0x0002803c, 1886 ADDR5_SWIZZLE_MASK_mask = 0x0f << 0, 1887 ADDR5_SWIZZLE_MASK_shift = 0, 1888 DB_Z_INFO = 0x00028040, 1889 DB_Z_INFO__FORMAT_mask = 0x03 << 0, 1890 DB_Z_INFO__FORMAT_shift = 0, 1891 Z_INVALID = 0x00, 1892 Z_16 = 0x01, 1893 Z_24 = 0x02, 1894 Z_32_FLOAT = 0x03, 1895 DB_Z_INFO__NUM_SAMPLES_mask = 0x03 << 2, 1896 DB_Z_INFO__NUM_SAMPLES_shift = 2, 1897 DB_Z_INFO__ARRAY_MODE_mask = 0x0f << 4, 1898 DB_Z_INFO__ARRAY_MODE_shift = 4, 1899 ARRAY_1D_TILED_THIN1 = 0x02, 1900 ARRAY_2D_TILED_THIN1 = 0x04, 1901 DB_Z_INFO__TILE_SPLIT_mask = 0x07 << 8, 1902 DB_Z_INFO__TILE_SPLIT_shift = 8, 1903 ADDR_SURF_TILE_SPLIT_64B = 0x00, 1904 ADDR_SURF_TILE_SPLIT_128B = 0x01, 1905 ADDR_SURF_TILE_SPLIT_256B = 0x02, 1906 ADDR_SURF_TILE_SPLIT_512B = 0x03, 1907 ADDR_SURF_TILE_SPLIT_1KB = 0x04, 1908 ADDR_SURF_TILE_SPLIT_2KB = 0x05, 1909 ADDR_SURF_TILE_SPLIT_4KB = 0x06, 1910 DB_Z_INFO__NUM_BANKS_mask = 0x03 << 12, 1911 DB_Z_INFO__NUM_BANKS_shift = 12, 1912 ADDR_SURF_2_BANK = 0x00, 1913 ADDR_SURF_4_BANK = 0x01, 1914 ADDR_SURF_8_BANK = 0x02, 1915 ADDR_SURF_16_BANK = 0x03, 1916 DB_Z_INFO__BANK_WIDTH_mask = 0x03 << 16, 1917 DB_Z_INFO__BANK_WIDTH_shift = 16, 1918 ADDR_SURF_BANK_WIDTH_1 = 0x00, 1919 ADDR_SURF_BANK_WIDTH_2 = 0x01, 1920 ADDR_SURF_BANK_WIDTH_4 = 0x02, 1921 ADDR_SURF_BANK_WIDTH_8 = 0x03, 1922 DB_Z_INFO__BANK_HEIGHT_mask = 0x03 << 20, 1923 DB_Z_INFO__BANK_HEIGHT_shift = 20, 1924 ADDR_SURF_BANK_HEIGHT_1 = 0x00, 1925 ADDR_SURF_BANK_HEIGHT_2 = 0x01, 1926 ADDR_SURF_BANK_HEIGHT_4 = 0x02, 1927 ADDR_SURF_BANK_HEIGHT_8 = 0x03, 1928 DB_Z_INFO__MACRO_TILE_ASPECT_mask = 0x03 << 24, 1929 DB_Z_INFO__MACRO_TILE_ASPECT_shift = 24, 1930 ADDR_SURF_MACRO_ASPECT_1 = 0x00, 1931 ADDR_SURF_MACRO_ASPECT_2 = 0x01, 1932 ADDR_SURF_MACRO_ASPECT_4 = 0x02, 1933 ADDR_SURF_MACRO_ASPECT_8 = 0x03, 1934 ALLOW_EXPCLEAR_bit = 1 << 27, 1935 READ_SIZE_bit = 1 << 28, 1936 TILE_SURFACE_ENABLE_bit = 1 << 29, 1937 ZRANGE_PRECISION_bit = 1 << 31, 1938 DB_STENCIL_INFO = 0x00028044, 1939 DB_STENCIL_INFO__FORMAT_bit = 1 << 0, 1940 DB_STENCIL_INFO__TILE_SPLIT_mask = 0x07 << 8, 1941 DB_STENCIL_INFO__TILE_SPLIT_shift = 8, 1942/* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ 1943/* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ 1944/* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ 1945/* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ 1946/* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ 1947/* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ 1948/* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ 1949/* ALLOW_EXPCLEAR_bit = 1 << 27, */ 1950 TILE_STENCIL_DISABLE_bit = 1 << 29, 1951 DB_Z_READ_BASE = 0x00028048, 1952 DB_STENCIL_READ_BASE = 0x0002804c, 1953 DB_Z_WRITE_BASE = 0x00028050, 1954 DB_STENCIL_WRITE_BASE = 0x00028054, 1955 DB_DEPTH_SIZE = 0x00028058, 1956 PITCH_TILE_MAX_mask = 0x7ff << 0, 1957 PITCH_TILE_MAX_shift = 0, 1958 HEIGHT_TILE_MAX_mask = 0x7ff << 11, 1959 HEIGHT_TILE_MAX_shift = 11, 1960 DB_DEPTH_SLICE = 0x0002805c, 1961 SLICE_TILE_MAX_mask = 0x3fffff << 0, 1962 SLICE_TILE_MAX_shift = 0, 1963 SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x00028140, 1964 SQ_ALU_CONST_BUFFER_SIZE_PS_0_num = 16, 1965 SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_mask = 0x1ff << 0, 1966 SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA_shift = 0, 1967 SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x00028180, 1968 SQ_ALU_CONST_BUFFER_SIZE_VS_0_num = 16, 1969 SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_mask = 0x1ff << 0, 1970 SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA_shift = 0, 1971 SQ_ALU_CONST_BUFFER_SIZE_GS_0 = 0x000281c0, 1972 SQ_ALU_CONST_BUFFER_SIZE_GS_0_num = 16, 1973 SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_mask = 0x1ff << 0, 1974 SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA_shift = 0, 1975 PA_SC_WINDOW_OFFSET = 0x00028200, 1976 WINDOW_X_OFFSET_mask = 0xffff << 0, 1977 WINDOW_X_OFFSET_shift = 0, 1978 WINDOW_Y_OFFSET_mask = 0xffff << 16, 1979 WINDOW_Y_OFFSET_shift = 16, 1980 PA_SC_WINDOW_SCISSOR_TL = 0x00028204, 1981 PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0, 1982 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift = 0, 1983 PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, 1984 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift = 16, 1985 WINDOW_OFFSET_DISABLE_bit = 1 << 31, 1986 PA_SC_WINDOW_SCISSOR_BR = 0x00028208, 1987 PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0, 1988 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift = 0, 1989 PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, 1990 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift = 16, 1991 PA_SC_CLIPRECT_RULE = 0x0002820c, 1992 CLIP_RULE_mask = 0xffff << 0, 1993 CLIP_RULE_shift = 0, 1994 PA_SC_CLIPRECT_0_TL = 0x00028210, 1995 PA_SC_CLIPRECT_0_TL_num = 4, 1996 PA_SC_CLIPRECT_0_TL_offset = 8, 1997 PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0, 1998 PA_SC_CLIPRECT_0_TL__TL_X_shift = 0, 1999 PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16, 2000 PA_SC_CLIPRECT_0_TL__TL_Y_shift = 16, 2001 PA_SC_CLIPRECT_0_BR = 0x00028214, 2002 PA_SC_CLIPRECT_0_BR_num = 4, 2003 PA_SC_CLIPRECT_0_BR_offset = 8, 2004 PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0, 2005 PA_SC_CLIPRECT_0_BR__BR_X_shift = 0, 2006 PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16, 2007 PA_SC_CLIPRECT_0_BR__BR_Y_shift = 16, 2008 PA_SC_EDGERULE = 0x00028230, 2009 ER_TRI_mask = 0x0f << 0, 2010 ER_TRI_shift = 0, 2011 ER_POINT_mask = 0x0f << 4, 2012 ER_POINT_shift = 4, 2013 ER_RECT_mask = 0x0f << 8, 2014 ER_RECT_shift = 8, 2015 ER_LINE_LR_mask = 0x3f << 12, 2016 ER_LINE_LR_shift = 12, 2017 ER_LINE_RL_mask = 0x3f << 18, 2018 ER_LINE_RL_shift = 18, 2019 ER_LINE_TB_mask = 0x0f << 24, 2020 ER_LINE_TB_shift = 24, 2021 ER_LINE_BT_mask = 0x0f << 28, 2022 ER_LINE_BT_shift = 28, 2023 PA_SU_HARDWARE_SCREEN_OFFSET = 0x00028234, 2024 HW_SCREEN_OFFSET_X_mask = 0x1f << 0, 2025 HW_SCREEN_OFFSET_X_shift = 0, 2026 HW_SCREEN_OFFSET_Y_mask = 0x1f << 8, 2027 HW_SCREEN_OFFSET_Y_shift = 8, 2028 CB_TARGET_MASK = 0x00028238, 2029 TARGET0_ENABLE_mask = 0x0f << 0, 2030 TARGET0_ENABLE_shift = 0, 2031 TARGET1_ENABLE_mask = 0x0f << 4, 2032 TARGET1_ENABLE_shift = 4, 2033 TARGET2_ENABLE_mask = 0x0f << 8, 2034 TARGET2_ENABLE_shift = 8, 2035 TARGET3_ENABLE_mask = 0x0f << 12, 2036 TARGET3_ENABLE_shift = 12, 2037 TARGET4_ENABLE_mask = 0x0f << 16, 2038 TARGET4_ENABLE_shift = 16, 2039 TARGET5_ENABLE_mask = 0x0f << 20, 2040 TARGET5_ENABLE_shift = 20, 2041 TARGET6_ENABLE_mask = 0x0f << 24, 2042 TARGET6_ENABLE_shift = 24, 2043 TARGET7_ENABLE_mask = 0x0f << 28, 2044 TARGET7_ENABLE_shift = 28, 2045 CB_SHADER_MASK = 0x0002823c, 2046 OUTPUT0_ENABLE_mask = 0x0f << 0, 2047 OUTPUT0_ENABLE_shift = 0, 2048 OUTPUT1_ENABLE_mask = 0x0f << 4, 2049 OUTPUT1_ENABLE_shift = 4, 2050 OUTPUT2_ENABLE_mask = 0x0f << 8, 2051 OUTPUT2_ENABLE_shift = 8, 2052 OUTPUT3_ENABLE_mask = 0x0f << 12, 2053 OUTPUT3_ENABLE_shift = 12, 2054 OUTPUT4_ENABLE_mask = 0x0f << 16, 2055 OUTPUT4_ENABLE_shift = 16, 2056 OUTPUT5_ENABLE_mask = 0x0f << 20, 2057 OUTPUT5_ENABLE_shift = 20, 2058 OUTPUT6_ENABLE_mask = 0x0f << 24, 2059 OUTPUT6_ENABLE_shift = 24, 2060 OUTPUT7_ENABLE_mask = 0x0f << 28, 2061 OUTPUT7_ENABLE_shift = 28, 2062 PA_SC_GENERIC_SCISSOR_TL = 0x00028240, 2063 PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0, 2064 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift = 0, 2065 PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16, 2066 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift = 16, 2067/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ 2068 PA_SC_GENERIC_SCISSOR_BR = 0x00028244, 2069 PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0, 2070 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift = 0, 2071 PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16, 2072 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift = 16, 2073 PA_SC_VPORT_SCISSOR_0_TL = 0x00028250, 2074 PA_SC_VPORT_SCISSOR_0_TL_num = 16, 2075 PA_SC_VPORT_SCISSOR_0_TL_offset = 8, 2076 PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0, 2077 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift = 0, 2078 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16, 2079 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift = 16, 2080/* WINDOW_OFFSET_DISABLE_bit = 1 << 31, */ 2081 PA_SC_VPORT_SCISSOR_0_BR = 0x00028254, 2082 PA_SC_VPORT_SCISSOR_0_BR_num = 16, 2083 PA_SC_VPORT_SCISSOR_0_BR_offset = 8, 2084 PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0, 2085 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift = 0, 2086 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16, 2087 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift = 16, 2088 PA_SC_VPORT_ZMIN_0 = 0x000282d0, 2089 PA_SC_VPORT_ZMIN_0_num = 16, 2090 PA_SC_VPORT_ZMIN_0_offset = 8, 2091 PA_SC_VPORT_ZMAX_0 = 0x000282d4, 2092 PA_SC_VPORT_ZMAX_0_num = 16, 2093 PA_SC_VPORT_ZMAX_0_offset = 8, 2094 SX_MISC = 0x00028350, 2095 MULTIPASS_bit = 1 << 0, 2096 SX_SURFACE_SYNC = 0x00028354, 2097 SURFACE_SYNC_MASK_mask = 0x3ff << 0, 2098 SURFACE_SYNC_MASK_shift = 0, 2099 SX_SCATTER_EXPORT_BASE = 0x00028358, 2100 SX_SCATTER_EXPORT_SIZE = 0x0002835c, 2101 SQ_VTX_SEMANTIC_0 = 0x00028380, 2102 SQ_VTX_SEMANTIC_0_num = 32, 2103/* SEMANTIC_ID_mask = 0xff << 0, */ 2104/* SEMANTIC_ID_shift = 0, */ 2105 VGT_MAX_VTX_INDX = 0x00028400, 2106 VGT_MIN_VTX_INDX = 0x00028404, 2107 VGT_INDX_OFFSET = 0x00028408, 2108 VGT_MULTI_PRIM_IB_RESET_INDX = 0x0002840c, 2109 SX_ALPHA_TEST_CONTROL = 0x00028410, 2110 ALPHA_FUNC_mask = 0x07 << 0, 2111 ALPHA_FUNC_shift = 0, 2112 REF_NEVER = 0x00, 2113 REF_LESS = 0x01, 2114 REF_EQUAL = 0x02, 2115 REF_LEQUAL = 0x03, 2116 REF_GREATER = 0x04, 2117 REF_NOTEQUAL = 0x05, 2118 REF_GEQUAL = 0x06, 2119 REF_ALWAYS = 0x07, 2120 ALPHA_TEST_ENABLE_bit = 1 << 3, 2121 ALPHA_TEST_BYPASS_bit = 1 << 8, 2122 CB_BLEND_RED = 0x00028414, 2123 CB_BLEND_GREEN = 0x00028418, 2124 CB_BLEND_BLUE = 0x0002841c, 2125 CB_BLEND_ALPHA = 0x00028420, 2126 DB_STENCILREFMASK = 0x00028430, 2127 STENCILREF_mask = 0xff << 0, 2128 STENCILREF_shift = 0, 2129 STENCILMASK_mask = 0xff << 8, 2130 STENCILMASK_shift = 8, 2131 STENCILWRITEMASK_mask = 0xff << 16, 2132 STENCILWRITEMASK_shift = 16, 2133 DB_STENCILREFMASK_BF = 0x00028434, 2134 STENCILREF_BF_mask = 0xff << 0, 2135 STENCILREF_BF_shift = 0, 2136 STENCILMASK_BF_mask = 0xff << 8, 2137 STENCILMASK_BF_shift = 8, 2138 STENCILWRITEMASK_BF_mask = 0xff << 16, 2139 STENCILWRITEMASK_BF_shift = 16, 2140 SX_ALPHA_REF = 0x00028438, 2141 PA_CL_VPORT_XSCALE_0 = 0x0002843c, 2142 PA_CL_VPORT_XSCALE_0_num = 16, 2143 PA_CL_VPORT_XSCALE_0_offset = 24, 2144 PA_CL_VPORT_XOFFSET_0 = 0x00028440, 2145 PA_CL_VPORT_XOFFSET_0_num = 16, 2146 PA_CL_VPORT_XOFFSET_0_offset = 24, 2147 PA_CL_VPORT_YSCALE_0 = 0x00028444, 2148 PA_CL_VPORT_YSCALE_0_num = 16, 2149 PA_CL_VPORT_YSCALE_0_offset = 24, 2150 PA_CL_VPORT_YOFFSET_0 = 0x00028448, 2151 PA_CL_VPORT_YOFFSET_0_num = 16, 2152 PA_CL_VPORT_YOFFSET_0_offset = 24, 2153 PA_CL_VPORT_ZSCALE_0 = 0x0002844c, 2154 PA_CL_VPORT_ZSCALE_0_num = 16, 2155 PA_CL_VPORT_ZSCALE_0_offset = 24, 2156 PA_CL_VPORT_ZOFFSET_0 = 0x00028450, 2157 PA_CL_VPORT_ZOFFSET_0_num = 16, 2158 PA_CL_VPORT_ZOFFSET_0_offset = 24, 2159 PA_CL_UCP_0_X = 0x000285bc, 2160 PA_CL_UCP_0_X_num = 6, 2161 PA_CL_UCP_0_X_offset = 16, 2162 PA_CL_UCP_0_Y = 0x000285c0, 2163 PA_CL_UCP_0_Y_num = 6, 2164 PA_CL_UCP_0_Y_offset = 16, 2165 PA_CL_UCP_0_Z = 0x000285c4, 2166 PA_CL_UCP_0_Z_num = 6, 2167 PA_CL_UCP_0_Z_offset = 16, 2168 PA_CL_UCP_0_W = 0x000285c8, 2169 PA_CL_UCP_0_W_num = 6, 2170 PA_CL_UCP_0_W_offset = 16, 2171 SPI_VS_OUT_ID_0 = 0x0002861c, 2172 SPI_VS_OUT_ID_0_num = 10, 2173 SEMANTIC_0_mask = 0xff << 0, 2174 SEMANTIC_0_shift = 0, 2175 SEMANTIC_1_mask = 0xff << 8, 2176 SEMANTIC_1_shift = 8, 2177 SEMANTIC_2_mask = 0xff << 16, 2178 SEMANTIC_2_shift = 16, 2179 SEMANTIC_3_mask = 0xff << 24, 2180 SEMANTIC_3_shift = 24, 2181 SPI_PS_INPUT_CNTL_0 = 0x00028644, 2182 SPI_PS_INPUT_CNTL_0_num = 32, 2183 SEMANTIC_mask = 0xff << 0, 2184 SEMANTIC_shift = 0, 2185 DEFAULT_VAL_mask = 0x03 << 8, 2186 DEFAULT_VAL_shift = 8, 2187 X_0_0F = 0x00, 2188 FLAT_SHADE_bit = 1 << 10, 2189 CYL_WRAP_mask = 0x0f << 13, 2190 CYL_WRAP_shift = 13, 2191 PT_SPRITE_TEX_bit = 1 << 17, 2192 SPI_VS_OUT_CONFIG = 0x000286c4, 2193 VS_PER_COMPONENT_bit = 1 << 0, 2194 VS_EXPORT_COUNT_mask = 0x1f << 1, 2195 VS_EXPORT_COUNT_shift = 1, 2196 VS_HALF_PACK_bit = 1 << 6, 2197 VS_EXPORTS_FOG_bit = 1 << 8, 2198 VS_OUT_FOG_VEC_ADDR_mask = 0x1f << 9, 2199 VS_OUT_FOG_VEC_ADDR_shift = 9, 2200 SPI_PS_IN_CONTROL_0 = 0x000286cc, 2201 NUM_INTERP_mask = 0x3f << 0, 2202 NUM_INTERP_shift = 0, 2203 POSITION_ENA_bit = 1 << 8, 2204 POSITION_CENTROID_bit = 1 << 9, 2205 POSITION_ADDR_mask = 0x1f << 10, 2206 POSITION_ADDR_shift = 10, 2207 PARAM_GEN_mask = 0x0f << 15, 2208 PARAM_GEN_shift = 15, 2209 PERSP_GRADIENT_ENA_bit = 1 << 28, 2210 LINEAR_GRADIENT_ENA_bit = 1 << 29, 2211 POSITION_SAMPLE_bit = 1 << 30, 2212 SPI_PS_IN_CONTROL_1 = 0x000286d0, 2213 FRONT_FACE_ENA_bit = 1 << 8, 2214 FRONT_FACE_ALL_BITS_bit = 1 << 11, 2215 FRONT_FACE_ADDR_mask = 0x1f << 12, 2216 FRONT_FACE_ADDR_shift = 12, 2217 FOG_ADDR_mask = 0x7f << 17, 2218 FOG_ADDR_shift = 17, 2219 FIXED_PT_POSITION_ENA_bit = 1 << 24, 2220 FIXED_PT_POSITION_ADDR_mask = 0x1f << 25, 2221 FIXED_PT_POSITION_ADDR_shift = 25, 2222 POSITION_ULC_bit = 1 << 30, 2223 SPI_INTERP_CONTROL_0 = 0x000286d4, 2224 FLAT_SHADE_ENA_bit = 1 << 0, 2225 PNT_SPRITE_ENA_bit = 1 << 1, 2226 PNT_SPRITE_OVRD_X_mask = 0x07 << 2, 2227 PNT_SPRITE_OVRD_X_shift = 2, 2228 SPI_PNT_SPRITE_SEL_0 = 0x00, 2229 SPI_PNT_SPRITE_SEL_1 = 0x01, 2230 SPI_PNT_SPRITE_SEL_S = 0x02, 2231 SPI_PNT_SPRITE_SEL_T = 0x03, 2232 SPI_PNT_SPRITE_SEL_NONE = 0x04, 2233 PNT_SPRITE_OVRD_Y_mask = 0x07 << 5, 2234 PNT_SPRITE_OVRD_Y_shift = 5, 2235/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ 2236/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ 2237/* SPI_PNT_SPRITE_SEL_S = 0x02, */ 2238/* SPI_PNT_SPRITE_SEL_T = 0x03, */ 2239/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ 2240 PNT_SPRITE_OVRD_Z_mask = 0x07 << 8, 2241 PNT_SPRITE_OVRD_Z_shift = 8, 2242/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ 2243/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ 2244/* SPI_PNT_SPRITE_SEL_S = 0x02, */ 2245/* SPI_PNT_SPRITE_SEL_T = 0x03, */ 2246/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ 2247 PNT_SPRITE_OVRD_W_mask = 0x07 << 11, 2248 PNT_SPRITE_OVRD_W_shift = 11, 2249/* SPI_PNT_SPRITE_SEL_0 = 0x00, */ 2250/* SPI_PNT_SPRITE_SEL_1 = 0x01, */ 2251/* SPI_PNT_SPRITE_SEL_S = 0x02, */ 2252/* SPI_PNT_SPRITE_SEL_T = 0x03, */ 2253/* SPI_PNT_SPRITE_SEL_NONE = 0x04, */ 2254 PNT_SPRITE_TOP_1_bit = 1 << 14, 2255 SPI_INPUT_Z = 0x000286d8, 2256 PROVIDE_Z_TO_SPI_bit = 1 << 0, 2257 SPI_FOG_CNTL = 0x000286dc, 2258 PASS_FOG_THROUGH_PS_bit = 1 << 0, 2259 SPI_BARYC_CNTL = 0x000286e0, 2260 PERSP_CENTER_ENA_mask = 0x03 << 0, 2261 PERSP_CENTER_ENA_shift = 0, 2262 X_OFF = 0x00, 2263 PERSP_CENTER_ENA__X_ON_AT_CENTER = 0x01, 2264 PERSP_CENTER_ENA__X_ON_AT_CENTROID = 0x02, 2265 PERSP_CENTROID_ENA_mask = 0x03 << 4, 2266 PERSP_CENTROID_ENA_shift = 4, 2267/* X_OFF = 0x00, */ 2268 PERSP_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, 2269 PERSP_CENTROID_ENA__X_ON_AT_CENTER = 0x02, 2270 PERSP_SAMPLE_ENA_mask = 0x03 << 8, 2271 PERSP_SAMPLE_ENA_shift = 8, 2272/* X_OFF = 0x00, */ 2273 PERSP_PULL_MODEL_ENA_mask = 0x03 << 12, 2274 PERSP_PULL_MODEL_ENA_shift = 12, 2275/* X_OFF = 0x00, */ 2276 LINEAR_CENTER_ENA_mask = 0x03 << 16, 2277 LINEAR_CENTER_ENA_shift = 16, 2278/* X_OFF = 0x00, */ 2279 LINEAR_CENTER_ENA__X_ON_AT_CENTER = 0x01, 2280 LINEAR_CENTER_ENA__X_ON_AT_CENTROID = 0x02, 2281 LINEAR_CENTROID_ENA_mask = 0x03 << 20, 2282 LINEAR_CENTROID_ENA_shift = 20, 2283/* X_OFF = 0x00, */ 2284 LINEAR_CENTROID_ENA__X_ON_AT_CENTROID = 0x01, 2285 LINEAR_CENTROID_ENA__X_ON_AT_CENTER = 0x02, 2286 LINEAR_SAMPLE_ENA_mask = 0x03 << 24, 2287 LINEAR_SAMPLE_ENA_shift = 24, 2288/* X_OFF = 0x00, */ 2289 SPI_PS_IN_CONTROL_2 = 0x000286e4, 2290 LINE_STIPPLE_TEX_ADDR_mask = 0xff << 0, 2291 LINE_STIPPLE_TEX_ADDR_shift = 0, 2292 LINE_STIPPLE_TEX_ENA_bit = 1 << 8, 2293 SPI_GPR_MGMT = 0x000286f8, 2294 SPI_GPR_MGMT__NUM_PS_GPRS_mask = 0x1f << 0, 2295 SPI_GPR_MGMT__NUM_PS_GPRS_shift = 0, 2296 SPI_GPR_MGMT__NUM_VS_GPRS_mask = 0x1f << 5, 2297 SPI_GPR_MGMT__NUM_VS_GPRS_shift = 5, 2298 NUM_GS_GPRS_mask = 0x1f << 10, 2299 NUM_GS_GPRS_shift = 10, 2300 NUM_ES_GPRS_mask = 0x1f << 15, 2301 NUM_ES_GPRS_shift = 15, 2302 NUM_HS_GPRS_mask = 0x1f << 20, 2303 NUM_HS_GPRS_shift = 20, 2304 NUM_LS_GPRS_mask = 0x1f << 25, 2305 NUM_LS_GPRS_shift = 25, 2306 SPI_LDS_MGMT = 0x000286fc, 2307 NUM_PS_LDS_mask = 0xff << 0, 2308 NUM_PS_LDS_shift = 0, 2309 NUM_LS_LDS_mask = 0xff << 8, 2310 NUM_LS_LDS_shift = 8, 2311 SPI_STACK_MGMT = 0x00028700, 2312 NUM_PS_STACK_mask = 0x1f << 0, 2313 NUM_PS_STACK_shift = 0, 2314 NUM_VS_STACK_mask = 0x1f << 5, 2315 NUM_VS_STACK_shift = 5, 2316 NUM_GS_STACK_mask = 0x1f << 10, 2317 NUM_GS_STACK_shift = 10, 2318 NUM_ES_STACK_mask = 0x1f << 15, 2319 NUM_ES_STACK_shift = 15, 2320 NUM_HS_STACK_mask = 0x1f << 20, 2321 NUM_HS_STACK_shift = 20, 2322 NUM_LS_STACK_mask = 0x1f << 25, 2323 NUM_LS_STACK_shift = 25, 2324 SPI_WAVE_MGMT_1 = 0x00028704, 2325 NUM_PS_WAVES_mask = 0x1f << 0, 2326 NUM_PS_WAVES_shift = 0, 2327 NUM_VS_WAVES_mask = 0x1f << 5, 2328 NUM_VS_WAVES_shift = 5, 2329 NUM_GS_WAVES_mask = 0x1f << 10, 2330 NUM_GS_WAVES_shift = 10, 2331 NUM_ES_WAVES_mask = 0x1f << 15, 2332 NUM_ES_WAVES_shift = 15, 2333 NUM_HS_WAVES_mask = 0x1f << 20, 2334 NUM_HS_WAVES_shift = 20, 2335 NUM_LS_WAVES_mask = 0x1f << 25, 2336 NUM_LS_WAVES_shift = 25, 2337 SPI_WAVE_MGMT_2 = 0x00028708, 2338 NUM_CS_WAVES_ONE_RING_mask = 0x1f << 0, 2339 NUM_CS_WAVES_ONE_RING_shift = 0, 2340 NUM_CS_WAVES_MULTI_RING_mask = 0x1f << 5, 2341 NUM_CS_WAVES_MULTI_RING_shift = 5, 2342 CB_BLEND0_CONTROL = 0x00028780, 2343 CB_BLEND0_CONTROL_num = 8, 2344 COLOR_SRCBLEND_mask = 0x1f << 0, 2345 COLOR_SRCBLEND_shift = 0, 2346 BLEND_ZERO = 0x00, 2347 BLEND_ONE = 0x01, 2348 BLEND_SRC_COLOR = 0x02, 2349 BLEND_ONE_MINUS_SRC_COLOR = 0x03, 2350 BLEND_SRC_ALPHA = 0x04, 2351 BLEND_ONE_MINUS_SRC_ALPHA = 0x05, 2352 BLEND_DST_ALPHA = 0x06, 2353 BLEND_ONE_MINUS_DST_ALPHA = 0x07, 2354 BLEND_DST_COLOR = 0x08, 2355 BLEND_ONE_MINUS_DST_COLOR = 0x09, 2356 BLEND_SRC_ALPHA_SATURATE = 0x0a, 2357 BLEND_BOTH_SRC_ALPHA = 0x0b, 2358 BLEND_BOTH_INV_SRC_ALPHA = 0x0c, 2359 BLEND_CONSTANT_COLOR = 0x0d, 2360 BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, 2361 BLEND_SRC1_COLOR = 0x0f, 2362 BLEND_INV_SRC1_COLOR = 0x10, 2363 BLEND_SRC1_ALPHA = 0x11, 2364 BLEND_INV_SRC1_ALPHA = 0x12, 2365 BLEND_CONSTANT_ALPHA = 0x13, 2366 BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, 2367 COLOR_COMB_FCN_mask = 0x07 << 5, 2368 COLOR_COMB_FCN_shift = 5, 2369 COMB_DST_PLUS_SRC = 0x00, 2370 COMB_SRC_MINUS_DST = 0x01, 2371 COMB_MIN_DST_SRC = 0x02, 2372 COMB_MAX_DST_SRC = 0x03, 2373 COMB_DST_MINUS_SRC = 0x04, 2374 COLOR_DESTBLEND_mask = 0x1f << 8, 2375 COLOR_DESTBLEND_shift = 8, 2376/* BLEND_ZERO = 0x00, */ 2377/* BLEND_ONE = 0x01, */ 2378/* BLEND_SRC_COLOR = 0x02, */ 2379/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ 2380/* BLEND_SRC_ALPHA = 0x04, */ 2381/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ 2382/* BLEND_DST_ALPHA = 0x06, */ 2383/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ 2384/* BLEND_DST_COLOR = 0x08, */ 2385/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ 2386/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ 2387/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ 2388/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ 2389/* BLEND_CONSTANT_COLOR = 0x0d, */ 2390/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ 2391/* BLEND_SRC1_COLOR = 0x0f, */ 2392/* BLEND_INV_SRC1_COLOR = 0x10, */ 2393/* BLEND_SRC1_ALPHA = 0x11, */ 2394/* BLEND_INV_SRC1_ALPHA = 0x12, */ 2395/* BLEND_CONSTANT_ALPHA = 0x13, */ 2396/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ 2397 ALPHA_SRCBLEND_mask = 0x1f << 16, 2398 ALPHA_SRCBLEND_shift = 16, 2399/* BLEND_ZERO = 0x00, */ 2400/* BLEND_ONE = 0x01, */ 2401/* BLEND_SRC_COLOR = 0x02, */ 2402/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ 2403/* BLEND_SRC_ALPHA = 0x04, */ 2404/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ 2405/* BLEND_DST_ALPHA = 0x06, */ 2406/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ 2407/* BLEND_DST_COLOR = 0x08, */ 2408/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ 2409/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ 2410/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ 2411/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ 2412/* BLEND_CONSTANT_COLOR = 0x0d, */ 2413/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ 2414/* BLEND_SRC1_COLOR = 0x0f, */ 2415/* BLEND_INV_SRC1_COLOR = 0x10, */ 2416/* BLEND_SRC1_ALPHA = 0x11, */ 2417/* BLEND_INV_SRC1_ALPHA = 0x12, */ 2418/* BLEND_CONSTANT_ALPHA = 0x13, */ 2419/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ 2420 ALPHA_COMB_FCN_mask = 0x07 << 21, 2421 ALPHA_COMB_FCN_shift = 21, 2422/* COMB_DST_PLUS_SRC = 0x00, */ 2423/* COMB_SRC_MINUS_DST = 0x01, */ 2424/* COMB_MIN_DST_SRC = 0x02, */ 2425/* COMB_MAX_DST_SRC = 0x03, */ 2426/* COMB_DST_MINUS_SRC = 0x04, */ 2427 ALPHA_DESTBLEND_mask = 0x1f << 24, 2428 ALPHA_DESTBLEND_shift = 24, 2429/* BLEND_ZERO = 0x00, */ 2430/* BLEND_ONE = 0x01, */ 2431/* BLEND_SRC_COLOR = 0x02, */ 2432/* BLEND_ONE_MINUS_SRC_COLOR = 0x03, */ 2433/* BLEND_SRC_ALPHA = 0x04, */ 2434/* BLEND_ONE_MINUS_SRC_ALPHA = 0x05, */ 2435/* BLEND_DST_ALPHA = 0x06, */ 2436/* BLEND_ONE_MINUS_DST_ALPHA = 0x07, */ 2437/* BLEND_DST_COLOR = 0x08, */ 2438/* BLEND_ONE_MINUS_DST_COLOR = 0x09, */ 2439/* BLEND_SRC_ALPHA_SATURATE = 0x0a, */ 2440/* BLEND_BOTH_SRC_ALPHA = 0x0b, */ 2441/* BLEND_BOTH_INV_SRC_ALPHA = 0x0c, */ 2442/* BLEND_CONSTANT_COLOR = 0x0d, */ 2443/* BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0e, */ 2444/* BLEND_SRC1_COLOR = 0x0f, */ 2445/* BLEND_INV_SRC1_COLOR = 0x10, */ 2446/* BLEND_SRC1_ALPHA = 0x11, */ 2447/* BLEND_INV_SRC1_ALPHA = 0x12, */ 2448/* BLEND_CONSTANT_ALPHA = 0x13, */ 2449/* BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, */ 2450 SEPARATE_ALPHA_BLEND_bit = 1 << 29, 2451 CB_BLEND0_CONTROL__ENABLE_bit = 1 << 30, 2452 PA_CL_POINT_X_RAD = 0x000287d4, 2453 PA_CL_POINT_Y_RAD = 0x000287d8, 2454 PA_CL_POINT_SIZE = 0x000287dc, 2455 PA_CL_POINT_CULL_RAD = 0x000287e0, 2456 VGT_DMA_BASE_HI = 0x000287e4, 2457 VGT_DMA_BASE_HI__BASE_ADDR_mask = 0xff << 0, 2458 VGT_DMA_BASE_HI__BASE_ADDR_shift = 0, 2459 VGT_DMA_BASE = 0x000287e8, 2460 VGT_DRAW_INITIATOR = 0x000287f0, 2461 SOURCE_SELECT_mask = 0x03 << 0, 2462 SOURCE_SELECT_shift = 0, 2463 DI_SRC_SEL_DMA = 0x00, 2464 DI_SRC_SEL_IMMEDIATE = 0x01, 2465 DI_SRC_SEL_AUTO_INDEX = 0x02, 2466 DI_SRC_SEL_RESERVED = 0x03, 2467 MAJOR_MODE_mask = 0x03 << 2, 2468 MAJOR_MODE_shift = 2, 2469 DI_MAJOR_MODE_0 = 0x00, 2470 DI_MAJOR_MODE_1 = 0x01, 2471 NOT_EOP_bit = 1 << 5, 2472 USE_OPAQUE_bit = 1 << 6, 2473 VGT_IMMED_DATA = 0x000287f4, 2474 VGT_EVENT_ADDRESS_REG = 0x000287f8, 2475 ADDRESS_LOW_mask = 0xfffffff << 0, 2476 ADDRESS_LOW_shift = 0, 2477 DB_DEPTH_CONTROL = 0x00028800, 2478 STENCIL_ENABLE_bit = 1 << 0, 2479 Z_ENABLE_bit = 1 << 1, 2480 Z_WRITE_ENABLE_bit = 1 << 2, 2481 ZFUNC_mask = 0x07 << 4, 2482 ZFUNC_shift = 4, 2483 FRAG_NEVER = 0x00, 2484 FRAG_LESS = 0x01, 2485 FRAG_EQUAL = 0x02, 2486 FRAG_LEQUAL = 0x03, 2487 FRAG_GREATER = 0x04, 2488 FRAG_NOTEQUAL = 0x05, 2489 FRAG_GEQUAL = 0x06, 2490 FRAG_ALWAYS = 0x07, 2491 BACKFACE_ENABLE_bit = 1 << 7, 2492 STENCILFUNC_mask = 0x07 << 8, 2493 STENCILFUNC_shift = 8, 2494/* REF_NEVER = 0x00, */ 2495/* REF_LESS = 0x01, */ 2496/* REF_EQUAL = 0x02, */ 2497/* REF_LEQUAL = 0x03, */ 2498/* REF_GREATER = 0x04, */ 2499/* REF_NOTEQUAL = 0x05, */ 2500/* REF_GEQUAL = 0x06, */ 2501/* REF_ALWAYS = 0x07, */ 2502 STENCILFAIL_mask = 0x07 << 11, 2503 STENCILFAIL_shift = 11, 2504 STENCIL_KEEP = 0x00, 2505 STENCIL_ZERO = 0x01, 2506 STENCIL_REPLACE = 0x02, 2507 STENCIL_INCR_CLAMP = 0x03, 2508 STENCIL_DECR_CLAMP = 0x04, 2509 STENCIL_INVERT = 0x05, 2510 STENCIL_INCR_WRAP = 0x06, 2511 STENCIL_DECR_WRAP = 0x07, 2512 STENCILZPASS_mask = 0x07 << 14, 2513 STENCILZPASS_shift = 14, 2514/* STENCIL_KEEP = 0x00, */ 2515/* STENCIL_ZERO = 0x01, */ 2516/* STENCIL_REPLACE = 0x02, */ 2517/* STENCIL_INCR_CLAMP = 0x03, */ 2518/* STENCIL_DECR_CLAMP = 0x04, */ 2519/* STENCIL_INVERT = 0x05, */ 2520/* STENCIL_INCR_WRAP = 0x06, */ 2521/* STENCIL_DECR_WRAP = 0x07, */ 2522 STENCILZFAIL_mask = 0x07 << 17, 2523 STENCILZFAIL_shift = 17, 2524/* STENCIL_KEEP = 0x00, */ 2525/* STENCIL_ZERO = 0x01, */ 2526/* STENCIL_REPLACE = 0x02, */ 2527/* STENCIL_INCR_CLAMP = 0x03, */ 2528/* STENCIL_DECR_CLAMP = 0x04, */ 2529/* STENCIL_INVERT = 0x05, */ 2530/* STENCIL_INCR_WRAP = 0x06, */ 2531/* STENCIL_DECR_WRAP = 0x07, */ 2532 STENCILFUNC_BF_mask = 0x07 << 20, 2533 STENCILFUNC_BF_shift = 20, 2534/* REF_NEVER = 0x00, */ 2535/* REF_LESS = 0x01, */ 2536/* REF_EQUAL = 0x02, */ 2537/* REF_LEQUAL = 0x03, */ 2538/* REF_GREATER = 0x04, */ 2539/* REF_NOTEQUAL = 0x05, */ 2540/* REF_GEQUAL = 0x06, */ 2541/* REF_ALWAYS = 0x07, */ 2542 STENCILFAIL_BF_mask = 0x07 << 23, 2543 STENCILFAIL_BF_shift = 23, 2544/* STENCIL_KEEP = 0x00, */ 2545/* STENCIL_ZERO = 0x01, */ 2546/* STENCIL_REPLACE = 0x02, */ 2547/* STENCIL_INCR_CLAMP = 0x03, */ 2548/* STENCIL_DECR_CLAMP = 0x04, */ 2549/* STENCIL_INVERT = 0x05, */ 2550/* STENCIL_INCR_WRAP = 0x06, */ 2551/* STENCIL_DECR_WRAP = 0x07, */ 2552 STENCILZPASS_BF_mask = 0x07 << 26, 2553 STENCILZPASS_BF_shift = 26, 2554/* STENCIL_KEEP = 0x00, */ 2555/* STENCIL_ZERO = 0x01, */ 2556/* STENCIL_REPLACE = 0x02, */ 2557/* STENCIL_INCR_CLAMP = 0x03, */ 2558/* STENCIL_DECR_CLAMP = 0x04, */ 2559/* STENCIL_INVERT = 0x05, */ 2560/* STENCIL_INCR_WRAP = 0x06, */ 2561/* STENCIL_DECR_WRAP = 0x07, */ 2562 STENCILZFAIL_BF_mask = 0x07 << 29, 2563 STENCILZFAIL_BF_shift = 29, 2564/* STENCIL_KEEP = 0x00, */ 2565/* STENCIL_ZERO = 0x01, */ 2566/* STENCIL_REPLACE = 0x02, */ 2567/* STENCIL_INCR_CLAMP = 0x03, */ 2568/* STENCIL_DECR_CLAMP = 0x04, */ 2569/* STENCIL_INVERT = 0x05, */ 2570/* STENCIL_INCR_WRAP = 0x06, */ 2571/* STENCIL_DECR_WRAP = 0x07, */ 2572 DB_EQAA = 0x00028804, 2573 CB_COLOR_CONTROL = 0x00028808, 2574 DEGAMMA_ENABLE_bit = 1 << 3, 2575 CB_COLOR_CONTROL__MODE_mask = 0x07 << 4, 2576 CB_COLOR_CONTROL__MODE_shift = 4, 2577 CB_DISABLE = 0x00, 2578 CB_NORMAL = 0x01, 2579 CB_ELIMINATE_FAST_CLEAR = 0x02, 2580 CB_RESOLVE = 0x03, 2581 CB_DECOMPRESS = 0x04, 2582 CB_FMASK_DECOMPRESS = 0x05, 2583 ROP3_mask = 0xff << 16, 2584 ROP3_shift = 16, 2585 X_0X00 = 0x00, 2586 X_0X05 = 0x05, 2587 X_0X0A = 0x0a, 2588 X_0X0F = 0x0f, 2589 X_0X11 = 0x11, 2590 X_0X22 = 0x22, 2591 X_0X33 = 0x33, 2592 X_0X44 = 0x44, 2593 X_0X50 = 0x50, 2594 X_0X55 = 0x55, 2595 X_0X5A = 0x5a, 2596 X_0X5F = 0x5f, 2597 X_0X66 = 0x66, 2598 X_0X77 = 0x77, 2599 X_0X88 = 0x88, 2600 X_0X99 = 0x99, 2601 X_0XA0 = 0xa0, 2602 X_0XA5 = 0xa5, 2603 X_0XAA = 0xaa, 2604 X_0XAF = 0xaf, 2605 X_0XBB = 0xbb, 2606 X_0XCC = 0xcc, 2607 X_0XDD = 0xdd, 2608 X_0XEE = 0xee, 2609 X_0XF0 = 0xf0, 2610 X_0XF5 = 0xf5, 2611 X_0XFA = 0xfa, 2612 X_0XFF = 0xff, 2613 DB_SHADER_CONTROL = 0x0002880c, 2614 Z_EXPORT_ENABLE_bit = 1 << 0, 2615 STENCIL_REF_EXPORT_ENABLE_bit = 1 << 1, 2616 Z_ORDER_mask = 0x03 << 4, 2617 Z_ORDER_shift = 4, 2618 LATE_Z = 0x00, 2619 EARLY_Z_THEN_LATE_Z = 0x01, 2620 RE_Z = 0x02, 2621 EARLY_Z_THEN_RE_Z = 0x03, 2622 KILL_ENABLE_bit = 1 << 6, 2623 COVERAGE_TO_MASK_ENABLE_bit = 1 << 7, 2624 MASK_EXPORT_ENABLE_bit = 1 << 8, 2625 DUAL_EXPORT_ENABLE_bit = 1 << 9, 2626 EXEC_ON_HIER_FAIL_bit = 1 << 10, 2627 EXEC_ON_NOOP_bit = 1 << 11, 2628 ALPHA_TO_MASK_DISABLE_bit = 1 << 12, 2629 DB_SOURCE_FORMAT_mask = 0x03 << 13, 2630 DB_SOURCE_FORMAT_shift = 13, 2631 EXPORT_DB_FULL = 0x00, 2632 EXPORT_DB_FOUR16 = 0x01, 2633 EXPORT_DB_TWO = 0x02, 2634 DEPTH_BEFORE_SHADER_bit = 1 << 15, 2635 CONSERVATIVE_Z_EXPORT_mask = 0x03 << 16, 2636 CONSERVATIVE_Z_EXPORT_shift = 16, 2637 EXPORT_ANY_Z = 0x00, 2638 EXPORT_LESS_THAN_Z = 0x01, 2639 EXPORT_GREATER_THAN_Z = 0x02, 2640 EXPORT_RESERVED = 0x03, 2641 PA_CL_CLIP_CNTL = 0x00028810, 2642 UCP_ENA_0_bit = 1 << 0, 2643 UCP_ENA_1_bit = 1 << 1, 2644 UCP_ENA_2_bit = 1 << 2, 2645 UCP_ENA_3_bit = 1 << 3, 2646 UCP_ENA_4_bit = 1 << 4, 2647 UCP_ENA_5_bit = 1 << 5, 2648 PS_UCP_Y_SCALE_NEG_bit = 1 << 13, 2649 PS_UCP_MODE_mask = 0x03 << 14, 2650 PS_UCP_MODE_shift = 14, 2651 CLIP_DISABLE_bit = 1 << 16, 2652 UCP_CULL_ONLY_ENA_bit = 1 << 17, 2653 BOUNDARY_EDGE_FLAG_ENA_bit = 1 << 18, 2654 DX_CLIP_SPACE_DEF_bit = 1 << 19, 2655 DIS_CLIP_ERR_DETECT_bit = 1 << 20, 2656 VTX_KILL_OR_bit = 1 << 21, 2657 DX_RASTERIZATION_KILL_bit = 1 << 22, 2658 DX_LINEAR_ATTR_CLIP_ENA_bit = 1 << 24, 2659 VTE_VPORT_PROVOKE_DISABLE_bit = 1 << 25, 2660 ZCLIP_NEAR_DISABLE_bit = 1 << 26, 2661 ZCLIP_FAR_DISABLE_bit = 1 << 27, 2662 PA_SU_SC_MODE_CNTL = 0x00028814, 2663 CULL_FRONT_bit = 1 << 0, 2664 CULL_BACK_bit = 1 << 1, 2665 FACE_bit = 1 << 2, 2666 POLY_MODE_mask = 0x03 << 3, 2667 POLY_MODE_shift = 3, 2668 X_DISABLE_POLY_MODE = 0x00, 2669 X_DUAL_MODE = 0x01, 2670 POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, 2671 POLYMODE_FRONT_PTYPE_shift = 5, 2672 X_DRAW_POINTS = 0x00, 2673 X_DRAW_LINES = 0x01, 2674 X_DRAW_TRIANGLES = 0x02, 2675 POLYMODE_BACK_PTYPE_mask = 0x07 << 8, 2676 POLYMODE_BACK_PTYPE_shift = 8, 2677/* X_DRAW_POINTS = 0x00, */ 2678/* X_DRAW_LINES = 0x01, */ 2679/* X_DRAW_TRIANGLES = 0x02, */ 2680 POLY_OFFSET_FRONT_ENABLE_bit = 1 << 11, 2681 POLY_OFFSET_BACK_ENABLE_bit = 1 << 12, 2682 POLY_OFFSET_PARA_ENABLE_bit = 1 << 13, 2683 VTX_WINDOW_OFFSET_ENABLE_bit = 1 << 16, 2684 PROVOKING_VTX_LAST_bit = 1 << 19, 2685 PERSP_CORR_DIS_bit = 1 << 20, 2686 MULTI_PRIM_IB_ENA_bit = 1 << 21, 2687 PA_CL_VTE_CNTL = 0x00028818, 2688 VPORT_X_SCALE_ENA_bit = 1 << 0, 2689 VPORT_X_OFFSET_ENA_bit = 1 << 1, 2690 VPORT_Y_SCALE_ENA_bit = 1 << 2, 2691 VPORT_Y_OFFSET_ENA_bit = 1 << 3, 2692 VPORT_Z_SCALE_ENA_bit = 1 << 4, 2693 VPORT_Z_OFFSET_ENA_bit = 1 << 5, 2694 VTX_XY_FMT_bit = 1 << 8, 2695 VTX_Z_FMT_bit = 1 << 9, 2696 VTX_W0_FMT_bit = 1 << 10, 2697 PA_CL_VS_OUT_CNTL = 0x0002881c, 2698 CLIP_DIST_ENA_0_bit = 1 << 0, 2699 CLIP_DIST_ENA_1_bit = 1 << 1, 2700 CLIP_DIST_ENA_2_bit = 1 << 2, 2701 CLIP_DIST_ENA_3_bit = 1 << 3, 2702 CLIP_DIST_ENA_4_bit = 1 << 4, 2703 CLIP_DIST_ENA_5_bit = 1 << 5, 2704 CLIP_DIST_ENA_6_bit = 1 << 6, 2705 CLIP_DIST_ENA_7_bit = 1 << 7, 2706 CULL_DIST_ENA_0_bit = 1 << 8, 2707 CULL_DIST_ENA_1_bit = 1 << 9, 2708 CULL_DIST_ENA_2_bit = 1 << 10, 2709 CULL_DIST_ENA_3_bit = 1 << 11, 2710 CULL_DIST_ENA_4_bit = 1 << 12, 2711 CULL_DIST_ENA_5_bit = 1 << 13, 2712 CULL_DIST_ENA_6_bit = 1 << 14, 2713 CULL_DIST_ENA_7_bit = 1 << 15, 2714 USE_VTX_POINT_SIZE_bit = 1 << 16, 2715 USE_VTX_EDGE_FLAG_bit = 1 << 17, 2716 USE_VTX_RENDER_TARGET_INDX_bit = 1 << 18, 2717 USE_VTX_VIEWPORT_INDX_bit = 1 << 19, 2718 USE_VTX_KILL_FLAG_bit = 1 << 20, 2719 VS_OUT_MISC_VEC_ENA_bit = 1 << 21, 2720 VS_OUT_CCDIST0_VEC_ENA_bit = 1 << 22, 2721 VS_OUT_CCDIST1_VEC_ENA_bit = 1 << 23, 2722 PA_CL_NANINF_CNTL = 0x00028820, 2723 VTE_XY_INF_DISCARD_bit = 1 << 0, 2724 VTE_Z_INF_DISCARD_bit = 1 << 1, 2725 VTE_W_INF_DISCARD_bit = 1 << 2, 2726 VTE_0XNANINF_IS_0_bit = 1 << 3, 2727 VTE_XY_NAN_RETAIN_bit = 1 << 4, 2728 VTE_Z_NAN_RETAIN_bit = 1 << 5, 2729 VTE_W_NAN_RETAIN_bit = 1 << 6, 2730 VTE_W_RECIP_NAN_IS_0_bit = 1 << 7, 2731 VS_XY_NAN_TO_INF_bit = 1 << 8, 2732 VS_XY_INF_RETAIN_bit = 1 << 9, 2733 VS_Z_NAN_TO_INF_bit = 1 << 10, 2734 VS_Z_INF_RETAIN_bit = 1 << 11, 2735 VS_W_NAN_TO_INF_bit = 1 << 12, 2736 VS_W_INF_RETAIN_bit = 1 << 13, 2737 VS_CLIP_DIST_INF_DISCARD_bit = 1 << 14, 2738 VTE_NO_OUTPUT_NEG_0_bit = 1 << 20, 2739 PA_SU_LINE_STIPPLE_CNTL = 0x00028824, 2740 LINE_STIPPLE_RESET_mask = 0x03 << 0, 2741 LINE_STIPPLE_RESET_shift = 0, 2742 EXPAND_FULL_LENGTH_bit = 1 << 2, 2743 FRACTIONAL_ACCUM_bit = 1 << 3, 2744 DIAMOND_ADJUST_bit = 1 << 4, 2745 PA_SU_LINE_STIPPLE_SCALE = 0x00028828, 2746 PA_SU_PRIM_FILTER_CNTL = 0x0002882c, 2747 TRIANGLE_FILTER_DISABLE_bit = 1 << 0, 2748 LINE_FILTER_DISABLE_bit = 1 << 1, 2749 POINT_FILTER_DISABLE_bit = 1 << 2, 2750 RECTANGLE_FILTER_DISABLE_bit = 1 << 3, 2751 TRIANGLE_EXPAND_ENA_bit = 1 << 4, 2752 LINE_EXPAND_ENA_bit = 1 << 5, 2753 POINT_EXPAND_ENA_bit = 1 << 6, 2754 RECTANGLE_EXPAND_ENA_bit = 1 << 7, 2755 PRIM_EXPAND_CONSTANT_mask = 0xff << 8, 2756 PRIM_EXPAND_CONSTANT_shift = 8, 2757 SQ_LSTMP_RING_ITEMSIZE = 0x00028830, 2758 ITEMSIZE_mask = 0x7fff << 0, 2759 ITEMSIZE_shift = 0, 2760 SQ_HSTMP_RING_ITEMSIZE = 0x00028834, 2761/* ITEMSIZE_mask = 0x7fff << 0, */ 2762/* ITEMSIZE_shift = 0, */ 2763 SQ_PGM_START_PS = 0x00028840, 2764 SQ_PGM_RESOURCES_PS = 0x00028844, 2765 NUM_GPRS_mask = 0xff << 0, 2766 NUM_GPRS_shift = 0, 2767 STACK_SIZE_mask = 0xff << 8, 2768 STACK_SIZE_shift = 8, 2769 DX10_CLAMP_bit = 1 << 21, 2770 UNCACHED_FIRST_INST_bit = 1 << 28, 2771 CLAMP_CONSTS_bit = 1 << 31, 2772 SQ_PGM_RESOURCES_2_PS = 0x00028848, 2773 SINGLE_ROUND_mask = 0x03 << 0, 2774 SINGLE_ROUND_shift = 0, 2775 SQ_ROUND_NEAREST_EVEN = 0x00, 2776 SQ_ROUND_PLUS_INFINITY = 0x01, 2777 SQ_ROUND_MINUS_INFINITY = 0x02, 2778 SQ_ROUND_TO_ZERO = 0x03, 2779 DOUBLE_ROUND_mask = 0x03 << 2, 2780 DOUBLE_ROUND_shift = 2, 2781/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2782/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2783/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2784/* SQ_ROUND_TO_ZERO = 0x03, */ 2785 ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, 2786 ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, 2787 ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, 2788 ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, 2789 SINGLE_IEEE_MODE_bit = 1 << 8, 2790 DOUBLE_IEEE_MODE_bit = 1 << 9, 2791 SQ_PGM_EXPORTS_PS = 0x0002884c, 2792 EXPORT_MODE_mask = 0x1f << 0, 2793 EXPORT_MODE_shift = 0, 2794 SQ_PGM_START_VS = 0x0002885c, 2795 SQ_PGM_RESOURCES_VS = 0x00028860, 2796/* NUM_GPRS_mask = 0xff << 0, */ 2797/* NUM_GPRS_shift = 0, */ 2798/* STACK_SIZE_mask = 0xff << 8, */ 2799/* STACK_SIZE_shift = 8, */ 2800 USE_LS_CONSTS_bit = 1 << 16, 2801/* DX10_CLAMP_bit = 1 << 21, */ 2802/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2803 SQ_PGM_RESOURCES_2_VS = 0x00028864, 2804/* SINGLE_ROUND_mask = 0x03 << 0, */ 2805/* SINGLE_ROUND_shift = 0, */ 2806/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2807/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2808/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2809/* SQ_ROUND_TO_ZERO = 0x03, */ 2810/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2811/* DOUBLE_ROUND_shift = 2, */ 2812/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2813/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2814/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2815/* SQ_ROUND_TO_ZERO = 0x03, */ 2816/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2817/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2818/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2819/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2820/* SINGLE_IEEE_MODE_bit = 1 << 8, */ 2821/* DOUBLE_IEEE_MODE_bit = 1 << 9, */ 2822 SQ_PGM_START_GS = 0x00028874, 2823 SQ_PGM_RESOURCES_GS = 0x00028878, 2824/* NUM_GPRS_mask = 0xff << 0, */ 2825/* NUM_GPRS_shift = 0, */ 2826/* STACK_SIZE_mask = 0xff << 8, */ 2827/* STACK_SIZE_shift = 8, */ 2828/* DX10_CLAMP_bit = 1 << 21, */ 2829/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2830 SQ_PGM_RESOURCES_2_GS = 0x0002887c, 2831/* SINGLE_ROUND_mask = 0x03 << 0, */ 2832/* SINGLE_ROUND_shift = 0, */ 2833/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2834/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2835/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2836/* SQ_ROUND_TO_ZERO = 0x03, */ 2837/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2838/* DOUBLE_ROUND_shift = 2, */ 2839/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2840/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2841/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2842/* SQ_ROUND_TO_ZERO = 0x03, */ 2843/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2844/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2845/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2846/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2847/* SINGLE_IEEE_MODE_bit = 1 << 8, */ 2848/* DOUBLE_IEEE_MODE_bit = 1 << 9, */ 2849 SQ_PGM_START_ES = 0x0002888c, 2850 SQ_PGM_RESOURCES_ES = 0x00028890, 2851/* NUM_GPRS_mask = 0xff << 0, */ 2852/* NUM_GPRS_shift = 0, */ 2853/* STACK_SIZE_mask = 0xff << 8, */ 2854/* STACK_SIZE_shift = 8, */ 2855/* USE_LS_CONSTS_bit = 1 << 16, */ 2856/* DX10_CLAMP_bit = 1 << 21, */ 2857/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2858 SQ_PGM_RESOURCES_2_ES = 0x00028894, 2859/* SINGLE_ROUND_mask = 0x03 << 0, */ 2860/* SINGLE_ROUND_shift = 0, */ 2861/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2862/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2863/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2864/* SQ_ROUND_TO_ZERO = 0x03, */ 2865/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2866/* DOUBLE_ROUND_shift = 2, */ 2867/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2868/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2869/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2870/* SQ_ROUND_TO_ZERO = 0x03, */ 2871/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2872/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2873/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2874/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2875/* SINGLE_IEEE_MODE_bit = 1 << 8, */ 2876/* DOUBLE_IEEE_MODE_bit = 1 << 9, */ 2877 SQ_PGM_START_FS = 0x000288a4, 2878 SQ_PGM_RESOURCES_FS = 0x000288a8, 2879/* NUM_GPRS_mask = 0xff << 0, */ 2880/* NUM_GPRS_shift = 0, */ 2881/* STACK_SIZE_mask = 0xff << 8, */ 2882/* STACK_SIZE_shift = 8, */ 2883/* DX10_CLAMP_bit = 1 << 21, */ 2884 SQ_PGM_START_HS = 0x000288b8, 2885 SQ_PGM_RESOURCES_HS = 0x000288bc, 2886/* NUM_GPRS_mask = 0xff << 0, */ 2887/* NUM_GPRS_shift = 0, */ 2888/* STACK_SIZE_mask = 0xff << 8, */ 2889/* STACK_SIZE_shift = 8, */ 2890/* DX10_CLAMP_bit = 1 << 21, */ 2891/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2892 SQ_PGM_RESOURCES_2_HS = 0x000288c0, 2893/* SINGLE_ROUND_mask = 0x03 << 0, */ 2894/* SINGLE_ROUND_shift = 0, */ 2895/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2896/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2897/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2898/* SQ_ROUND_TO_ZERO = 0x03, */ 2899/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2900/* DOUBLE_ROUND_shift = 2, */ 2901/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2902/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2903/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2904/* SQ_ROUND_TO_ZERO = 0x03, */ 2905/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2906/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2907/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2908/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2909/* SINGLE_IEEE_MODE_bit = 1 << 8, */ 2910/* DOUBLE_IEEE_MODE_bit = 1 << 9, */ 2911 SQ_PGM_START_LS = 0x000288d0, 2912 SQ_PGM_RESOURCES_LS = 0x000288d4, 2913/* NUM_GPRS_mask = 0xff << 0, */ 2914/* NUM_GPRS_shift = 0, */ 2915/* STACK_SIZE_mask = 0xff << 8, */ 2916/* STACK_SIZE_shift = 8, */ 2917 USE_VS_CONSTS_bit = 1 << 16, 2918/* DX10_CLAMP_bit = 1 << 21, */ 2919/* UNCACHED_FIRST_INST_bit = 1 << 28, */ 2920 SQ_PGM_RESOURCES_2_LS = 0x000288d8, 2921/* SINGLE_ROUND_mask = 0x03 << 0, */ 2922/* SINGLE_ROUND_shift = 0, */ 2923/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2924/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2925/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2926/* SQ_ROUND_TO_ZERO = 0x03, */ 2927/* DOUBLE_ROUND_mask = 0x03 << 2, */ 2928/* DOUBLE_ROUND_shift = 2, */ 2929/* SQ_ROUND_NEAREST_EVEN = 0x00, */ 2930/* SQ_ROUND_PLUS_INFINITY = 0x01, */ 2931/* SQ_ROUND_MINUS_INFINITY = 0x02, */ 2932/* SQ_ROUND_TO_ZERO = 0x03, */ 2933/* ALLOW_SINGLE_DENORM_IN_bit = 1 << 4, */ 2934/* ALLOW_SINGLE_DENORM_OUT_bit = 1 << 5, */ 2935/* ALLOW_DOUBLE_DENORM_IN_bit = 1 << 6, */ 2936/* ALLOW_DOUBLE_DENORM_OUT_bit = 1 << 7, */ 2937/* SINGLE_IEEE_MODE_bit = 1 << 8, */ 2938/* DOUBLE_IEEE_MODE_bit = 1 << 9, */ 2939 SQ_VTX_SEMANTIC_CLEAR = 0x000288f0, 2940 SQ_ESGS_RING_ITEMSIZE = 0x00028900, 2941/* ITEMSIZE_mask = 0x7fff << 0, */ 2942/* ITEMSIZE_shift = 0, */ 2943 SQ_GSVS_RING_ITEMSIZE = 0x00028904, 2944/* ITEMSIZE_mask = 0x7fff << 0, */ 2945/* ITEMSIZE_shift = 0, */ 2946 SQ_ESTMP_RING_ITEMSIZE = 0x00028908, 2947/* ITEMSIZE_mask = 0x7fff << 0, */ 2948/* ITEMSIZE_shift = 0, */ 2949 SQ_GSTMP_RING_ITEMSIZE = 0x0002890c, 2950/* ITEMSIZE_mask = 0x7fff << 0, */ 2951/* ITEMSIZE_shift = 0, */ 2952 SQ_VSTMP_RING_ITEMSIZE = 0x00028910, 2953/* ITEMSIZE_mask = 0x7fff << 0, */ 2954/* ITEMSIZE_shift = 0, */ 2955 SQ_PSTMP_RING_ITEMSIZE = 0x00028914, 2956/* ITEMSIZE_mask = 0x7fff << 0, */ 2957/* ITEMSIZE_shift = 0, */ 2958 SQ_GS_VERT_ITEMSIZE = 0x0002891c, 2959/* ITEMSIZE_mask = 0x7fff << 0, */ 2960/* ITEMSIZE_shift = 0, */ 2961 SQ_GS_VERT_ITEMSIZE_1 = 0x00028920, 2962/* ITEMSIZE_mask = 0x7fff << 0, */ 2963/* ITEMSIZE_shift = 0, */ 2964 SQ_GS_VERT_ITEMSIZE_2 = 0x00028924, 2965/* ITEMSIZE_mask = 0x7fff << 0, */ 2966/* ITEMSIZE_shift = 0, */ 2967 SQ_GS_VERT_ITEMSIZE_3 = 0x00028928, 2968/* ITEMSIZE_mask = 0x7fff << 0, */ 2969/* ITEMSIZE_shift = 0, */ 2970 SQ_GSVS_RING_OFFSET_1 = 0x0002892c, 2971 SQ_GSVS_RING_OFFSET_1__OFFSET_mask = 0x7fff << 0, 2972 SQ_GSVS_RING_OFFSET_1__OFFSET_shift = 0, 2973 SQ_GSVS_RING_OFFSET_2 = 0x00028930, 2974 SQ_GSVS_RING_OFFSET_2__OFFSET_mask = 0x7fff << 0, 2975 SQ_GSVS_RING_OFFSET_2__OFFSET_shift = 0, 2976 SQ_GSVS_RING_OFFSET_3 = 0x00028934, 2977 SQ_GSVS_RING_OFFSET_3__OFFSET_mask = 0x7fff << 0, 2978 SQ_GSVS_RING_OFFSET_3__OFFSET_shift = 0, 2979 SQ_ALU_CONST_CACHE_PS_0 = 0x00028940, 2980 SQ_ALU_CONST_CACHE_PS_0_num = 16, 2981 SQ_ALU_CONST_CACHE_VS_0 = 0x00028980, 2982 SQ_ALU_CONST_CACHE_VS_0_num = 16, 2983 SQ_ALU_CONST_CACHE_GS_0 = 0x000289c0, 2984 SQ_ALU_CONST_CACHE_GS_0_num = 16, 2985 PA_SU_POINT_SIZE = 0x00028a00, 2986 HEIGHT_mask = 0xffff << 0, 2987 HEIGHT_shift = 0, 2988 PA_SU_POINT_SIZE__WIDTH_mask = 0xffff << 16, 2989 PA_SU_POINT_SIZE__WIDTH_shift = 16, 2990 PA_SU_POINT_MINMAX = 0x00028a04, 2991 MIN_SIZE_mask = 0xffff << 0, 2992 MIN_SIZE_shift = 0, 2993 PA_SU_POINT_MINMAX__MAX_SIZE_mask = 0xffff << 16, 2994 PA_SU_POINT_MINMAX__MAX_SIZE_shift = 16, 2995 PA_SU_LINE_CNTL = 0x00028a08, 2996 PA_SU_LINE_CNTL__WIDTH_mask = 0xffff << 0, 2997 PA_SU_LINE_CNTL__WIDTH_shift = 0, 2998 PA_SC_LINE_STIPPLE = 0x00028a0c, 2999 LINE_PATTERN_mask = 0xffff << 0, 3000 LINE_PATTERN_shift = 0, 3001 REPEAT_COUNT_mask = 0xff << 16, 3002 REPEAT_COUNT_shift = 16, 3003 PATTERN_BIT_ORDER_bit = 1 << 28, 3004 AUTO_RESET_CNTL_mask = 0x03 << 29, 3005 AUTO_RESET_CNTL_shift = 29, 3006 VGT_OUTPUT_PATH_CNTL = 0x00028a10, 3007 PATH_SELECT_mask = 0x07 << 0, 3008 PATH_SELECT_shift = 0, 3009 VGT_OUTPATH_VTX_REUSE = 0x00, 3010 VGT_OUTPATH_TESS_EN = 0x01, 3011 VGT_OUTPATH_PASSTHRU = 0x02, 3012 VGT_OUTPATH_GS_BLOCK = 0x03, 3013 VGT_OUTPATH_HS_BLOCK = 0x04, 3014 VGT_HOS_CNTL = 0x00028a14, 3015 TESS_MODE_mask = 0x03 << 0, 3016 TESS_MODE_shift = 0, 3017 VGT_HOS_MAX_TESS_LEVEL = 0x00028a18, 3018 VGT_HOS_MIN_TESS_LEVEL = 0x00028a1c, 3019 VGT_HOS_REUSE_DEPTH = 0x00028a20, 3020 REUSE_DEPTH_mask = 0xff << 0, 3021 REUSE_DEPTH_shift = 0, 3022 VGT_GROUP_PRIM_TYPE = 0x00028a24, 3023 VGT_GROUP_PRIM_TYPE__PRIM_TYPE_mask = 0x1f << 0, 3024 VGT_GROUP_PRIM_TYPE__PRIM_TYPE_shift = 0, 3025 VGT_GRP_3D_POINT = 0x00, 3026 VGT_GRP_3D_LINE = 0x01, 3027 VGT_GRP_3D_TRI = 0x02, 3028 VGT_GRP_3D_RECT = 0x03, 3029 VGT_GRP_3D_QUAD = 0x04, 3030 VGT_GRP_2D_COPY_RECT_V0 = 0x05, 3031 VGT_GRP_2D_COPY_RECT_V1 = 0x06, 3032 VGT_GRP_2D_COPY_RECT_V2 = 0x07, 3033 VGT_GRP_2D_COPY_RECT_V3 = 0x08, 3034 VGT_GRP_2D_FILL_RECT = 0x09, 3035 VGT_GRP_2D_LINE = 0x0a, 3036 VGT_GRP_2D_TRI = 0x0b, 3037 VGT_GRP_PRIM_INDEX_LINE = 0x0c, 3038 VGT_GRP_PRIM_INDEX_TRI = 0x0d, 3039 VGT_GRP_PRIM_INDEX_QUAD = 0x0e, 3040 VGT_GRP_3D_LINE_ADJ = 0x0f, 3041 VGT_GRP_3D_TRI_ADJ = 0x10, 3042 VGT_GRP_3D_PATCH = 0x11, 3043 RETAIN_ORDER_bit = 1 << 14, 3044 RETAIN_QUADS_bit = 1 << 15, 3045 PRIM_ORDER_mask = 0x07 << 16, 3046 PRIM_ORDER_shift = 16, 3047 VGT_GRP_LIST = 0x00, 3048 VGT_GRP_STRIP = 0x01, 3049 VGT_GRP_FAN = 0x02, 3050 VGT_GRP_LOOP = 0x03, 3051 VGT_GRP_POLYGON = 0x04, 3052 VGT_GROUP_FIRST_DECR = 0x00028a28, 3053 FIRST_DECR_mask = 0x0f << 0, 3054 FIRST_DECR_shift = 0, 3055 VGT_GROUP_DECR = 0x00028a2c, 3056 DECR_mask = 0x0f << 0, 3057 DECR_shift = 0, 3058 VGT_GROUP_VECT_0_CNTL = 0x00028a30, 3059 COMP_X_EN_bit = 1 << 0, 3060 COMP_Y_EN_bit = 1 << 1, 3061 COMP_Z_EN_bit = 1 << 2, 3062 COMP_W_EN_bit = 1 << 3, 3063 VGT_GROUP_VECT_0_CNTL__STRIDE_mask = 0xff << 8, 3064 VGT_GROUP_VECT_0_CNTL__STRIDE_shift = 8, 3065 SHIFT_mask = 0xff << 16, 3066 SHIFT_shift = 16, 3067 VGT_GROUP_VECT_1_CNTL = 0x00028a34, 3068/* COMP_X_EN_bit = 1 << 0, */ 3069/* COMP_Y_EN_bit = 1 << 1, */ 3070/* COMP_Z_EN_bit = 1 << 2, */ 3071/* COMP_W_EN_bit = 1 << 3, */ 3072 VGT_GROUP_VECT_1_CNTL__STRIDE_mask = 0xff << 8, 3073 VGT_GROUP_VECT_1_CNTL__STRIDE_shift = 8, 3074/* SHIFT_mask = 0xff << 16, */ 3075/* SHIFT_shift = 16, */ 3076 VGT_GROUP_VECT_0_FMT_CNTL = 0x00028a38, 3077 X_CONV_mask = 0x0f << 0, 3078 X_CONV_shift = 0, 3079 VGT_GRP_INDEX_16 = 0x00, 3080 VGT_GRP_INDEX_32 = 0x01, 3081 VGT_GRP_UINT_16 = 0x02, 3082 VGT_GRP_UINT_32 = 0x03, 3083 VGT_GRP_SINT_16 = 0x04, 3084 VGT_GRP_SINT_32 = 0x05, 3085 VGT_GRP_FLOAT_32 = 0x06, 3086 VGT_GRP_AUTO_PRIM = 0x07, 3087 VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, 3088 X_OFFSET_mask = 0x0f << 4, 3089 X_OFFSET_shift = 4, 3090 Y_CONV_mask = 0x0f << 8, 3091 Y_CONV_shift = 8, 3092/* VGT_GRP_INDEX_16 = 0x00, */ 3093/* VGT_GRP_INDEX_32 = 0x01, */ 3094/* VGT_GRP_UINT_16 = 0x02, */ 3095/* VGT_GRP_UINT_32 = 0x03, */ 3096/* VGT_GRP_SINT_16 = 0x04, */ 3097/* VGT_GRP_SINT_32 = 0x05, */ 3098/* VGT_GRP_FLOAT_32 = 0x06, */ 3099/* VGT_GRP_AUTO_PRIM = 0x07, */ 3100/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3101 Y_OFFSET_mask = 0x0f << 12, 3102 Y_OFFSET_shift = 12, 3103 Z_CONV_mask = 0x0f << 16, 3104 Z_CONV_shift = 16, 3105/* VGT_GRP_INDEX_16 = 0x00, */ 3106/* VGT_GRP_INDEX_32 = 0x01, */ 3107/* VGT_GRP_UINT_16 = 0x02, */ 3108/* VGT_GRP_UINT_32 = 0x03, */ 3109/* VGT_GRP_SINT_16 = 0x04, */ 3110/* VGT_GRP_SINT_32 = 0x05, */ 3111/* VGT_GRP_FLOAT_32 = 0x06, */ 3112/* VGT_GRP_AUTO_PRIM = 0x07, */ 3113/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3114 Z_OFFSET_mask = 0x0f << 20, 3115 Z_OFFSET_shift = 20, 3116 W_CONV_mask = 0x0f << 24, 3117 W_CONV_shift = 24, 3118/* VGT_GRP_INDEX_16 = 0x00, */ 3119/* VGT_GRP_INDEX_32 = 0x01, */ 3120/* VGT_GRP_UINT_16 = 0x02, */ 3121/* VGT_GRP_UINT_32 = 0x03, */ 3122/* VGT_GRP_SINT_16 = 0x04, */ 3123/* VGT_GRP_SINT_32 = 0x05, */ 3124/* VGT_GRP_FLOAT_32 = 0x06, */ 3125/* VGT_GRP_AUTO_PRIM = 0x07, */ 3126/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3127 W_OFFSET_mask = 0x0f << 28, 3128 W_OFFSET_shift = 28, 3129 VGT_GROUP_VECT_1_FMT_CNTL = 0x00028a3c, 3130/* X_CONV_mask = 0x0f << 0, */ 3131/* X_CONV_shift = 0, */ 3132/* VGT_GRP_INDEX_16 = 0x00, */ 3133/* VGT_GRP_INDEX_32 = 0x01, */ 3134/* VGT_GRP_UINT_16 = 0x02, */ 3135/* VGT_GRP_UINT_32 = 0x03, */ 3136/* VGT_GRP_SINT_16 = 0x04, */ 3137/* VGT_GRP_SINT_32 = 0x05, */ 3138/* VGT_GRP_FLOAT_32 = 0x06, */ 3139/* VGT_GRP_AUTO_PRIM = 0x07, */ 3140/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3141/* X_OFFSET_mask = 0x0f << 4, */ 3142/* X_OFFSET_shift = 4, */ 3143/* Y_CONV_mask = 0x0f << 8, */ 3144/* Y_CONV_shift = 8, */ 3145/* VGT_GRP_INDEX_16 = 0x00, */ 3146/* VGT_GRP_INDEX_32 = 0x01, */ 3147/* VGT_GRP_UINT_16 = 0x02, */ 3148/* VGT_GRP_UINT_32 = 0x03, */ 3149/* VGT_GRP_SINT_16 = 0x04, */ 3150/* VGT_GRP_SINT_32 = 0x05, */ 3151/* VGT_GRP_FLOAT_32 = 0x06, */ 3152/* VGT_GRP_AUTO_PRIM = 0x07, */ 3153/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3154/* Y_OFFSET_mask = 0x0f << 12, */ 3155/* Y_OFFSET_shift = 12, */ 3156/* Z_CONV_mask = 0x0f << 16, */ 3157/* Z_CONV_shift = 16, */ 3158/* VGT_GRP_INDEX_16 = 0x00, */ 3159/* VGT_GRP_INDEX_32 = 0x01, */ 3160/* VGT_GRP_UINT_16 = 0x02, */ 3161/* VGT_GRP_UINT_32 = 0x03, */ 3162/* VGT_GRP_SINT_16 = 0x04, */ 3163/* VGT_GRP_SINT_32 = 0x05, */ 3164/* VGT_GRP_FLOAT_32 = 0x06, */ 3165/* VGT_GRP_AUTO_PRIM = 0x07, */ 3166/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3167/* Z_OFFSET_mask = 0x0f << 20, */ 3168/* Z_OFFSET_shift = 20, */ 3169/* W_CONV_mask = 0x0f << 24, */ 3170/* W_CONV_shift = 24, */ 3171/* VGT_GRP_INDEX_16 = 0x00, */ 3172/* VGT_GRP_INDEX_32 = 0x01, */ 3173/* VGT_GRP_UINT_16 = 0x02, */ 3174/* VGT_GRP_UINT_32 = 0x03, */ 3175/* VGT_GRP_SINT_16 = 0x04, */ 3176/* VGT_GRP_SINT_32 = 0x05, */ 3177/* VGT_GRP_FLOAT_32 = 0x06, */ 3178/* VGT_GRP_AUTO_PRIM = 0x07, */ 3179/* VGT_GRP_FIX_1_23_TO_FLOAT = 0x08, */ 3180/* W_OFFSET_mask = 0x0f << 28, */ 3181/* W_OFFSET_shift = 28, */ 3182 VGT_GS_MODE = 0x00028a40, 3183 VGT_GS_MODE__MODE_mask = 0x03 << 0, 3184 VGT_GS_MODE__MODE_shift = 0, 3185 GS_OFF = 0x00, 3186 GS_SCENARIO_A = 0x01, 3187 GS_SCENARIO_B = 0x02, 3188 GS_SCENARIO_G = 0x03, 3189 GS_SCENARIO_C = 0x04, 3190 SPRITE_EN = 0x05, 3191 ES_PASSTHRU_bit = 1 << 2, 3192 CUT_MODE_mask = 0x03 << 3, 3193 CUT_MODE_shift = 3, 3194 GS_CUT_1024 = 0x00, 3195 GS_CUT_512 = 0x01, 3196 GS_CUT_256 = 0x02, 3197 GS_CUT_128 = 0x03, 3198 MODE_HI_bit = 1 << 8, 3199 PA_SC_MODE_CNTL_0 = 0x00028a48, 3200 MSAA_ENABLE_bit = 1 << 0, 3201 VPORT_SCISSOR_ENABLE_bit = 1 << 1, 3202 LINE_STIPPLE_ENABLE_bit = 1 << 2, 3203 VGT_ENHANCE = 0x00028a50, 3204 VGT_GS_PER_ES = 0x00028a54, 3205 GS_PER_ES_mask = 0x7ff << 0, 3206 GS_PER_ES_shift = 0, 3207 VGT_ES_PER_GS = 0x00028a58, 3208 ES_PER_GS_mask = 0x7ff << 0, 3209 ES_PER_GS_shift = 0, 3210 VGT_GS_PER_VS = 0x00028a5c, 3211 GS_PER_VS_mask = 0x0f << 0, 3212 GS_PER_VS_shift = 0, 3213 VGT_GS_OUT_PRIM_TYPE = 0x00028a6c, 3214 OUTPRIM_TYPE_mask = 0x3f << 0, 3215 OUTPRIM_TYPE_shift = 0, 3216 POINTLIST = 0x00, 3217 LINESTRIP = 0x01, 3218 TRISTRIP = 0x02, 3219 VGT_DMA_SIZE = 0x00028a74, 3220 VGT_DMA_MAX_SIZE = 0x00028a78, 3221 VGT_DMA_INDEX_TYPE = 0x00028a7c, 3222/* INDEX_TYPE_mask = 0x03 << 0, */ 3223/* INDEX_TYPE_shift = 0, */ 3224 VGT_INDEX_16 = 0x00, 3225 VGT_INDEX_32 = 0x01, 3226 SWAP_MODE_mask = 0x03 << 2, 3227 SWAP_MODE_shift = 2, 3228 VGT_DMA_SWAP_NONE = 0x00, 3229 VGT_DMA_SWAP_16_BIT = 0x01, 3230 VGT_DMA_SWAP_32_BIT = 0x02, 3231 VGT_DMA_SWAP_WORD = 0x03, 3232 VGT_PRIMITIVEID_EN = 0x00028a84, 3233 PRIMITIVEID_EN_bit = 1 << 0, 3234 VGT_DMA_NUM_INSTANCES = 0x00028a88, 3235 VGT_EVENT_INITIATOR = 0x00028a90, 3236 EVENT_TYPE_mask = 0x3f << 0, 3237 EVENT_TYPE_shift = 0, 3238 SAMPLE_STREAMOUTSTATS1 = 0x01, 3239 SAMPLE_STREAMOUTSTATS2 = 0x02, 3240 SAMPLE_STREAMOUTSTATS3 = 0x03, 3241 CACHE_FLUSH_TS = 0x04, 3242 CONTEXT_DONE = 0x05, 3243 CACHE_FLUSH = 0x06, 3244 CS_PARTIAL_FLUSH = 0x07, 3245 VGT_STREAMOUT_SYNC = 0x08, 3246 RST_PIX_CNT = 0x0d, 3247 VS_PARTIAL_FLUSH = 0x0f, 3248 PS_PARTIAL_FLUSH = 0x10, 3249 FLUSH_HS_OUTPUT = 0x11, 3250 FLUSH_LS_OUTPUT = 0x12, 3251 CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, 3252 ZPASS_DONE = 0x15, 3253 CACHE_FLUSH_AND_INV_EVENT = 0x16, 3254 PERFCOUNTER_START = 0x17, 3255 PERFCOUNTER_STOP = 0x18, 3256 PIPELINESTAT_START = 0x19, 3257 PIPELINESTAT_STOP = 0x1a, 3258 PERFCOUNTER_SAMPLE = 0x1b, 3259 FLUSH_ES_OUTPUT = 0x1c, 3260 FLUSH_GS_OUTPUT = 0x1d, 3261 SAMPLE_PIPELINESTAT = 0x1e, 3262 SO_VGTSTREAMOUT_FLUSH = 0x1f, 3263 SAMPLE_STREAMOUTSTATS = 0x20, 3264 RESET_VTX_CNT = 0x21, 3265 BLOCK_CONTEXT_DONE = 0x22, 3266 CS_CONTEXT_DONE = 0x23, 3267 VGT_FLUSH = 0x24, 3268 SQ_NON_EVENT = 0x26, 3269 SC_SEND_DB_VPZ = 0x27, 3270 BOTTOM_OF_PIPE_TS = 0x28, 3271 FLUSH_SX_TS = 0x29, 3272 DB_CACHE_FLUSH_AND_INV = 0x2a, 3273 FLUSH_AND_INV_DB_DATA_TS = 0x2b, 3274 FLUSH_AND_INV_DB_META = 0x2c, 3275 FLUSH_AND_INV_CB_DATA_TS = 0x2d, 3276 FLUSH_AND_INV_CB_META = 0x2e, 3277 CS_DONE = 0x2f, 3278 PS_DONE = 0x30, 3279 FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, 3280 SX_CB_RAT_ACK_REQUEST = 0x32, 3281 ADDRESS_HI_mask = 0x1ff << 18, 3282 ADDRESS_HI_shift = 18, 3283 EXTENDED_EVENT_bit = 1 << 27, 3284 VGT_MULTI_PRIM_IB_RESET_EN = 0x00028a94, 3285 RESET_EN_bit = 1 << 0, 3286 VGT_INSTANCE_STEP_RATE_0 = 0x00028aa0, 3287 VGT_INSTANCE_STEP_RATE_1 = 0x00028aa4, 3288 VGT_REUSE_OFF = 0x00028ab4, 3289 REUSE_OFF_bit = 1 << 0, 3290 VGT_VTX_CNT_EN = 0x00028ab8, 3291 VTX_CNT_EN_bit = 1 << 0, 3292 DB_HTILE_SURFACE = 0x00028abc, 3293 HTILE_WIDTH_bit = 1 << 0, 3294 HTILE_HEIGHT_bit = 1 << 1, 3295 LINEAR_bit = 1 << 2, 3296 FULL_CACHE_bit = 1 << 3, 3297 HTILE_USES_PRELOAD_WIN_bit = 1 << 4, 3298 PRELOAD_bit = 1 << 5, 3299 PREFETCH_WIDTH_mask = 0x3f << 6, 3300 PREFETCH_WIDTH_shift = 6, 3301 PREFETCH_HEIGHT_mask = 0x3f << 12, 3302 PREFETCH_HEIGHT_shift = 12, 3303 DB_SRESULTS_COMPARE_STATE0 = 0x00028ac0, 3304 COMPAREFUNC0_mask = 0x07 << 0, 3305 COMPAREFUNC0_shift = 0, 3306/* REF_NEVER = 0x00, */ 3307/* REF_LESS = 0x01, */ 3308/* REF_EQUAL = 0x02, */ 3309/* REF_LEQUAL = 0x03, */ 3310/* REF_GREATER = 0x04, */ 3311/* REF_NOTEQUAL = 0x05, */ 3312/* REF_GEQUAL = 0x06, */ 3313/* REF_ALWAYS = 0x07, */ 3314 COMPAREVALUE0_mask = 0xff << 4, 3315 COMPAREVALUE0_shift = 4, 3316 COMPAREMASK0_mask = 0xff << 12, 3317 COMPAREMASK0_shift = 12, 3318 ENABLE0_bit = 1 << 24, 3319 DB_SRESULTS_COMPARE_STATE1 = 0x00028ac4, 3320 COMPAREFUNC1_mask = 0x07 << 0, 3321 COMPAREFUNC1_shift = 0, 3322/* REF_NEVER = 0x00, */ 3323/* REF_LESS = 0x01, */ 3324/* REF_EQUAL = 0x02, */ 3325/* REF_LEQUAL = 0x03, */ 3326/* REF_GREATER = 0x04, */ 3327/* REF_NOTEQUAL = 0x05, */ 3328/* REF_GEQUAL = 0x06, */ 3329/* REF_ALWAYS = 0x07, */ 3330 COMPAREVALUE1_mask = 0xff << 4, 3331 COMPAREVALUE1_shift = 4, 3332 COMPAREMASK1_mask = 0xff << 12, 3333 COMPAREMASK1_shift = 12, 3334 ENABLE1_bit = 1 << 24, 3335 DB_PRELOAD_CONTROL = 0x00028ac8, 3336 START_X_mask = 0xff << 0, 3337 START_X_shift = 0, 3338 START_Y_mask = 0xff << 8, 3339 START_Y_shift = 8, 3340 MAX_X_mask = 0xff << 16, 3341 MAX_X_shift = 16, 3342 MAX_Y_mask = 0xff << 24, 3343 MAX_Y_shift = 24, 3344 VGT_STRMOUT_BUFFER_SIZE_0 = 0x00028ad0, 3345 VGT_STRMOUT_VTX_STRIDE_0 = 0x00028ad4, 3346 VGT_STRMOUT_VTX_STRIDE_0__STRIDE_mask = 0x3ff << 0, 3347 VGT_STRMOUT_VTX_STRIDE_0__STRIDE_shift = 0, 3348 VGT_STRMOUT_BUFFER_BASE_0 = 0x00028ad8, 3349 VGT_STRMOUT_BUFFER_OFFSET_0 = 0x00028adc, 3350 VGT_STRMOUT_BUFFER_SIZE_1 = 0x00028ae0, 3351 VGT_STRMOUT_VTX_STRIDE_1 = 0x00028ae4, 3352 VGT_STRMOUT_VTX_STRIDE_1__STRIDE_mask = 0x3ff << 0, 3353 VGT_STRMOUT_VTX_STRIDE_1__STRIDE_shift = 0, 3354 VGT_STRMOUT_BUFFER_BASE_1 = 0x00028ae8, 3355 VGT_STRMOUT_BUFFER_OFFSET_1 = 0x00028aec, 3356 VGT_STRMOUT_BUFFER_SIZE_2 = 0x00028af0, 3357 VGT_STRMOUT_VTX_STRIDE_2 = 0x00028af4, 3358 VGT_STRMOUT_VTX_STRIDE_2__STRIDE_mask = 0x3ff << 0, 3359 VGT_STRMOUT_VTX_STRIDE_2__STRIDE_shift = 0, 3360 VGT_STRMOUT_BUFFER_BASE_2 = 0x00028af8, 3361 VGT_STRMOUT_BUFFER_OFFSET_2 = 0x00028afc, 3362 VGT_STRMOUT_BUFFER_SIZE_3 = 0x00028b00, 3363 VGT_STRMOUT_VTX_STRIDE_3 = 0x00028b04, 3364 VGT_STRMOUT_VTX_STRIDE_3__STRIDE_mask = 0x3ff << 0, 3365 VGT_STRMOUT_VTX_STRIDE_3__STRIDE_shift = 0, 3366 VGT_STRMOUT_BUFFER_BASE_3 = 0x00028b08, 3367 VGT_STRMOUT_BUFFER_OFFSET_3 = 0x00028b0c, 3368 VGT_STRMOUT_BASE_OFFSET_0 = 0x00028b10, 3369 VGT_STRMOUT_BASE_OFFSET_1 = 0x00028b14, 3370 VGT_STRMOUT_BASE_OFFSET_2 = 0x00028b18, 3371 VGT_STRMOUT_BASE_OFFSET_3 = 0x00028b1c, 3372 VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x00028b28, 3373 VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x00028b2c, 3374 VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x00028b30, 3375 VERTEX_STRIDE_mask = 0x1ff << 0, 3376 VERTEX_STRIDE_shift = 0, 3377 VGT_GS_MAX_VERT_OUT = 0x00028b38, 3378 MAX_VERT_OUT_mask = 0x7ff << 0, 3379 MAX_VERT_OUT_shift = 0, 3380 VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x00028b44, 3381 VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_mask = 0x3f << 0, 3382 VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET_shift = 0, 3383 VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x00028b48, 3384 VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_mask = 0x3f << 0, 3385 VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET_shift = 0, 3386 VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x00028b4c, 3387 VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_mask = 0x3f << 0, 3388 VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET_shift = 0, 3389 VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x00028b50, 3390 VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_mask = 0x3f << 0, 3391 VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET_shift = 0, 3392 VGT_SHADER_STAGES_EN = 0x00028b54, 3393 LS_EN_mask = 0x03 << 0, 3394 LS_EN_shift = 0, 3395 LS_STAGE_OFF = 0x00, 3396 LS_STAGE_ON = 0x01, 3397 CS_STAGE_ON = 0x02, 3398 HS_EN_bit = 1 << 2, 3399 ES_EN_mask = 0x03 << 3, 3400 ES_EN_shift = 3, 3401 ES_STAGE_OFF = 0x00, 3402 ES_STAGE_DS = 0x01, 3403 ES_STAGE_REAL = 0x02, 3404 GS_EN_bit = 1 << 5, 3405 VS_EN_mask = 0x03 << 6, 3406 VS_EN_shift = 6, 3407 VS_STAGE_REAL = 0x00, 3408 VS_STAGE_DS = 0x01, 3409 VS_STAGE_COPY_SHADER = 0x02, 3410 DYNAMIC_HS_bit = 1 << 8, 3411 VGT_LS_HS_CONFIG = 0x00028b58, 3412 NUM_PATCHES_mask = 0xff << 0, 3413 NUM_PATCHES_shift = 0, 3414 HS_NUM_INPUT_CP_mask = 0x3f << 8, 3415 HS_NUM_INPUT_CP_shift = 8, 3416 HS_NUM_OUTPUT_CP_mask = 0x3f << 14, 3417 HS_NUM_OUTPUT_CP_shift = 14, 3418 DB_ALPHA_TO_MASK = 0x00028b70, 3419 ALPHA_TO_MASK_ENABLE_bit = 1 << 0, 3420 ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, 3421 ALPHA_TO_MASK_OFFSET0_shift = 8, 3422 ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, 3423 ALPHA_TO_MASK_OFFSET1_shift = 10, 3424 ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, 3425 ALPHA_TO_MASK_OFFSET2_shift = 12, 3426 ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, 3427 ALPHA_TO_MASK_OFFSET3_shift = 14, 3428 OFFSET_ROUND_bit = 1 << 16, 3429 PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x00028b78, 3430 POLY_OFFSET_NEG_NUM_DB_BITS_mask = 0xff << 0, 3431 POLY_OFFSET_NEG_NUM_DB_BITS_shift = 0, 3432 POLY_OFFSET_DB_IS_FLOAT_FMT_bit = 1 << 8, 3433 PA_SU_POLY_OFFSET_CLAMP = 0x00028b7c, 3434 PA_SU_POLY_OFFSET_FRONT_SCALE = 0x00028b80, 3435 PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x00028b84, 3436 PA_SU_POLY_OFFSET_BACK_SCALE = 0x00028b88, 3437 PA_SU_POLY_OFFSET_BACK_OFFSET = 0x00028b8c, 3438 VGT_GS_INSTANCE_CNT = 0x00028b90, 3439 VGT_GS_INSTANCE_CNT__ENABLE_bit = 1 << 0, 3440 CNT_mask = 0x7f << 2, 3441 CNT_shift = 2, 3442 VGT_STRMOUT_CONFIG = 0x00028b94, 3443 STREAMOUT_0_EN_bit = 1 << 0, 3444 STREAMOUT_1_EN_bit = 1 << 1, 3445 STREAMOUT_2_EN_bit = 1 << 2, 3446 STREAMOUT_3_EN_bit = 1 << 3, 3447 RAST_STREAM_mask = 0x07 << 4, 3448 RAST_STREAM_shift = 4, 3449 VGT_STRMOUT_BUFFER_CONFIG = 0x00028b98, 3450 STREAM_0_BUFFER_EN_mask = 0x0f << 0, 3451 STREAM_0_BUFFER_EN_shift = 0, 3452 STREAM_1_BUFFER_EN_mask = 0x0f << 4, 3453 STREAM_1_BUFFER_EN_shift = 4, 3454 STREAM_2_BUFFER_EN_mask = 0x0f << 8, 3455 STREAM_2_BUFFER_EN_shift = 8, 3456 STREAM_3_BUFFER_EN_mask = 0x0f << 12, 3457 STREAM_3_BUFFER_EN_shift = 12, 3458 CB_IMMED0_BASE = 0x00028b9c, 3459 CB_IMMED0_BASE_num = 12, 3460 PA_SC_CENTROID_PRIORITY_0 = 0x00028bd4, 3461 DISTANCE_0_mask = 0x0f << 0, 3462 DISTANCE_0_shift = 0, 3463 DISTANCE_1_mask = 0x0f << 4, 3464 DISTANCE_1_shift = 4, 3465 DISTANCE_2_mask = 0x0f << 8, 3466 DISTANCE_2_shift = 8, 3467 DISTANCE_3_mask = 0x0f << 12, 3468 DISTANCE_3_shift = 12, 3469 DISTANCE_4_mask = 0x0f << 16, 3470 DISTANCE_4_shift = 16, 3471 DISTANCE_5_mask = 0x0f << 20, 3472 DISTANCE_5_shift = 20, 3473 DISTANCE_6_mask = 0x0f << 24, 3474 DISTANCE_6_shift = 24, 3475 DISTANCE_7_mask = 0x0f << 28, 3476 DISTANCE_7_shift = 28, 3477 PA_SC_CENTROID_PRIORITY_1 = 0x00028bd8, 3478 DISTANCE_8_mask = 0x0f << 0, 3479 DISTANCE_8_shift = 0, 3480 DISTANCE_9_mask = 0x0f << 4, 3481 DISTANCE_9_shift = 4, 3482 DISTANCE_10_mask = 0x0f << 8, 3483 DISTANCE_10_shift = 8, 3484 DISTANCE_11_mask = 0x0f << 12, 3485 DISTANCE_11_shift = 12, 3486 DISTANCE_12_mask = 0x0f << 16, 3487 DISTANCE_12_shift = 16, 3488 DISTANCE_13_mask = 0x0f << 20, 3489 DISTANCE_13_shift = 20, 3490 DISTANCE_14_mask = 0x0f << 24, 3491 DISTANCE_14_shift = 24, 3492 DISTANCE_15_mask = 0x0f << 28, 3493 DISTANCE_15_shift = 28, 3494 PA_SC_LINE_CNTL = 0x00028bdc, 3495 EXPAND_LINE_WIDTH_bit = 1 << 9, 3496 LAST_PIXEL_bit = 1 << 10, 3497 PERPENDICULAR_ENDCAP_ENA_bit = 1 << 11, 3498 DX10_DIAMOND_TEST_ENA_bit = 1 << 12, 3499 PA_SC_AA_CONFIG = 0x00028be0, 3500 MSAA_NUM_SAMPLES_mask = 0x07 << 0, 3501 MSAA_NUM_SAMPLES_shift = 0, 3502 AA_MASK_CENTROID_DTMN_bit = 1 << 4, 3503 MAX_SAMPLE_DIST_mask = 0x0f << 13, 3504 MAX_SAMPLE_DIST_shift = 13, 3505 MSAA_EXPOSED_SAMPLES_mask = 0x07 << 20, 3506 MSAA_EXPOSED_SAMPLES_shift = 20, 3507 DETAIL_TO_EXPOSED_MODE_mask = 0x03 << 24, 3508 DETAIL_TO_EXPOSED_MODE_shift = 24, 3509 PA_SU_VTX_CNTL = 0x00028be4, 3510 PIX_CENTER_bit = 1 << 0, 3511 PA_SU_VTX_CNTL__ROUND_MODE_mask = 0x03 << 1, 3512 PA_SU_VTX_CNTL__ROUND_MODE_shift = 1, 3513 X_TRUNCATE = 0x00, 3514 X_ROUND = 0x01, 3515 X_ROUND_TO_EVEN = 0x02, 3516 X_ROUND_TO_ODD = 0x03, 3517 QUANT_MODE_mask = 0x07 << 3, 3518 QUANT_MODE_shift = 3, 3519 X_1_16TH = 0x00, 3520 X_1_8TH = 0x01, 3521 X_1_4TH = 0x02, 3522 X_1_2 = 0x03, 3523 QUANT_MODE__X_1 = 0x04, 3524 X_1_256TH = 0x05, 3525 X_1_1024TH = 0x06, 3526 X_1_4096TH = 0x07, 3527 PA_CL_GB_VERT_CLIP_ADJ = 0x00028be8, 3528 PA_CL_GB_HORZ_CLIP_ADJ = 0x00028bf0, 3529 PA_CL_GB_HORZ_DISC_ADJ = 0x00028bf4, 3530 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x00028bf8, 3531 S0_X_mask = 0x0f << 0, 3532 S0_X_shift = 0, 3533 S0_Y_mask = 0x0f << 4, 3534 S0_Y_shift = 4, 3535 S1_X_mask = 0x0f << 8, 3536 S1_X_shift = 8, 3537 S1_Y_mask = 0x0f << 12, 3538 S1_Y_shift = 12, 3539 S2_X_mask = 0x0f << 16, 3540 S2_X_shift = 16, 3541 S2_Y_mask = 0x0f << 20, 3542 S2_Y_shift = 20, 3543 S3_X_mask = 0x0f << 24, 3544 S3_X_shift = 24, 3545 S3_Y_mask = 0x0f << 28, 3546 S3_Y_shift = 28, 3547 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 = 0x00028bfc, 3548 S4_X_mask = 0x0f << 0, 3549 S4_X_shift = 0, 3550 S4_Y_mask = 0x0f << 4, 3551 S4_Y_shift = 4, 3552 S5_X_mask = 0x0f << 8, 3553 S5_X_shift = 8, 3554 S5_Y_mask = 0x0f << 12, 3555 S5_Y_shift = 12, 3556 S6_X_mask = 0x0f << 16, 3557 S6_X_shift = 16, 3558 S6_Y_mask = 0x0f << 20, 3559 S6_Y_shift = 20, 3560 S7_X_mask = 0x0f << 24, 3561 S7_X_shift = 24, 3562 S7_Y_mask = 0x0f << 28, 3563 S7_Y_shift = 28, 3564 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 = 0x00028c00, 3565 S8_X_mask = 0x0f << 0, 3566 S8_X_shift = 0, 3567 S8_Y_mask = 0x0f << 4, 3568 S8_Y_shift = 4, 3569 S9_X_mask = 0x0f << 8, 3570 S9_X_shift = 8, 3571 S9_Y_mask = 0x0f << 12, 3572 S9_Y_shift = 12, 3573 S10_X_mask = 0x0f << 16, 3574 S10_X_shift = 16, 3575 S10_Y_mask = 0x0f << 20, 3576 S10_Y_shift = 20, 3577 S11_X_mask = 0x0f << 24, 3578 S11_X_shift = 24, 3579 S11_Y_mask = 0x0f << 28, 3580 S11_Y_shift = 28, 3581 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 = 0x00028c04, 3582 S12_X_mask = 0x0f << 0, 3583 S12_X_shift = 0, 3584 S12_Y_mask = 0x0f << 4, 3585 S12_Y_shift = 4, 3586 S13_X_mask = 0x0f << 8, 3587 S13_X_shift = 8, 3588 S13_Y_mask = 0x0f << 12, 3589 S13_Y_shift = 12, 3590 S14_X_mask = 0x0f << 16, 3591 S14_X_shift = 16, 3592 S14_Y_mask = 0x0f << 20, 3593 S14_Y_shift = 20, 3594 S15_X_mask = 0x0f << 24, 3595 S15_X_shift = 24, 3596 S15_Y_mask = 0x0f << 28, 3597 S15_Y_shift = 28, 3598 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 = 0x00028c08, 3599/* S0_X_mask = 0x0f << 0, */ 3600/* S0_X_shift = 0, */ 3601/* S0_Y_mask = 0x0f << 4, */ 3602/* S0_Y_shift = 4, */ 3603/* S1_X_mask = 0x0f << 8, */ 3604/* S1_X_shift = 8, */ 3605/* S1_Y_mask = 0x0f << 12, */ 3606/* S1_Y_shift = 12, */ 3607/* S2_X_mask = 0x0f << 16, */ 3608/* S2_X_shift = 16, */ 3609/* S2_Y_mask = 0x0f << 20, */ 3610/* S2_Y_shift = 20, */ 3611/* S3_X_mask = 0x0f << 24, */ 3612/* S3_X_shift = 24, */ 3613/* S3_Y_mask = 0x0f << 28, */ 3614/* S3_Y_shift = 28, */ 3615 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 = 0x00028c0c, 3616/* S4_X_mask = 0x0f << 0, */ 3617/* S4_X_shift = 0, */ 3618/* S4_Y_mask = 0x0f << 4, */ 3619/* S4_Y_shift = 4, */ 3620/* S5_X_mask = 0x0f << 8, */ 3621/* S5_X_shift = 8, */ 3622/* S5_Y_mask = 0x0f << 12, */ 3623/* S5_Y_shift = 12, */ 3624/* S6_X_mask = 0x0f << 16, */ 3625/* S6_X_shift = 16, */ 3626/* S6_Y_mask = 0x0f << 20, */ 3627/* S6_Y_shift = 20, */ 3628/* S7_X_mask = 0x0f << 24, */ 3629/* S7_X_shift = 24, */ 3630/* S7_Y_mask = 0x0f << 28, */ 3631/* S7_Y_shift = 28, */ 3632 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 = 0x00028c10, 3633/* S8_X_mask = 0x0f << 0, */ 3634/* S8_X_shift = 0, */ 3635/* S8_Y_mask = 0x0f << 4, */ 3636/* S8_Y_shift = 4, */ 3637/* S9_X_mask = 0x0f << 8, */ 3638/* S9_X_shift = 8, */ 3639/* S9_Y_mask = 0x0f << 12, */ 3640/* S9_Y_shift = 12, */ 3641/* S10_X_mask = 0x0f << 16, */ 3642/* S10_X_shift = 16, */ 3643/* S10_Y_mask = 0x0f << 20, */ 3644/* S10_Y_shift = 20, */ 3645/* S11_X_mask = 0x0f << 24, */ 3646/* S11_X_shift = 24, */ 3647/* S11_Y_mask = 0x0f << 28, */ 3648/* S11_Y_shift = 28, */ 3649 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 = 0x00028c14, 3650/* S12_X_mask = 0x0f << 0, */ 3651/* S12_X_shift = 0, */ 3652/* S12_Y_mask = 0x0f << 4, */ 3653/* S12_Y_shift = 4, */ 3654/* S13_X_mask = 0x0f << 8, */ 3655/* S13_X_shift = 8, */ 3656/* S13_Y_mask = 0x0f << 12, */ 3657/* S13_Y_shift = 12, */ 3658/* S14_X_mask = 0x0f << 16, */ 3659/* S14_X_shift = 16, */ 3660/* S14_Y_mask = 0x0f << 20, */ 3661/* S14_Y_shift = 20, */ 3662/* S15_X_mask = 0x0f << 24, */ 3663/* S15_X_shift = 24, */ 3664/* S15_Y_mask = 0x0f << 28, */ 3665/* S15_Y_shift = 28, */ 3666 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 = 0x00028c18, 3667/* S0_X_mask = 0x0f << 0, */ 3668/* S0_X_shift = 0, */ 3669/* S0_Y_mask = 0x0f << 4, */ 3670/* S0_Y_shift = 4, */ 3671/* S1_X_mask = 0x0f << 8, */ 3672/* S1_X_shift = 8, */ 3673/* S1_Y_mask = 0x0f << 12, */ 3674/* S1_Y_shift = 12, */ 3675/* S2_X_mask = 0x0f << 16, */ 3676/* S2_X_shift = 16, */ 3677/* S2_Y_mask = 0x0f << 20, */ 3678/* S2_Y_shift = 20, */ 3679/* S3_X_mask = 0x0f << 24, */ 3680/* S3_X_shift = 24, */ 3681/* S3_Y_mask = 0x0f << 28, */ 3682/* S3_Y_shift = 28, */ 3683 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 = 0x00028c1c, 3684/* S4_X_mask = 0x0f << 0, */ 3685/* S4_X_shift = 0, */ 3686/* S4_Y_mask = 0x0f << 4, */ 3687/* S4_Y_shift = 4, */ 3688/* S5_X_mask = 0x0f << 8, */ 3689/* S5_X_shift = 8, */ 3690/* S5_Y_mask = 0x0f << 12, */ 3691/* S5_Y_shift = 12, */ 3692/* S6_X_mask = 0x0f << 16, */ 3693/* S6_X_shift = 16, */ 3694/* S6_Y_mask = 0x0f << 20, */ 3695/* S6_Y_shift = 20, */ 3696/* S7_X_mask = 0x0f << 24, */ 3697/* S7_X_shift = 24, */ 3698/* S7_Y_mask = 0x0f << 28, */ 3699/* S7_Y_shift = 28, */ 3700 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 = 0x00028c20, 3701/* S8_X_mask = 0x0f << 0, */ 3702/* S8_X_shift = 0, */ 3703/* S8_Y_mask = 0x0f << 4, */ 3704/* S8_Y_shift = 4, */ 3705/* S9_X_mask = 0x0f << 8, */ 3706/* S9_X_shift = 8, */ 3707/* S9_Y_mask = 0x0f << 12, */ 3708/* S9_Y_shift = 12, */ 3709/* S10_X_mask = 0x0f << 16, */ 3710/* S10_X_shift = 16, */ 3711/* S10_Y_mask = 0x0f << 20, */ 3712/* S10_Y_shift = 20, */ 3713/* S11_X_mask = 0x0f << 24, */ 3714/* S11_X_shift = 24, */ 3715/* S11_Y_mask = 0x0f << 28, */ 3716/* S11_Y_shift = 28, */ 3717 PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 = 0x00028c24, 3718/* S12_X_mask = 0x0f << 0, */ 3719/* S12_X_shift = 0, */ 3720/* S12_Y_mask = 0x0f << 4, */ 3721/* S12_Y_shift = 4, */ 3722/* S13_X_mask = 0x0f << 8, */ 3723/* S13_X_shift = 8, */ 3724/* S13_Y_mask = 0x0f << 12, */ 3725/* S13_Y_shift = 12, */ 3726/* S14_X_mask = 0x0f << 16, */ 3727/* S14_X_shift = 16, */ 3728/* S14_Y_mask = 0x0f << 20, */ 3729/* S14_Y_shift = 20, */ 3730/* S15_X_mask = 0x0f << 24, */ 3731/* S15_X_shift = 24, */ 3732/* S15_Y_mask = 0x0f << 28, */ 3733/* S15_Y_shift = 28, */ 3734 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 = 0x00028c28, 3735/* S0_X_mask = 0x0f << 0, */ 3736/* S0_X_shift = 0, */ 3737/* S0_Y_mask = 0x0f << 4, */ 3738/* S0_Y_shift = 4, */ 3739/* S1_X_mask = 0x0f << 8, */ 3740/* S1_X_shift = 8, */ 3741/* S1_Y_mask = 0x0f << 12, */ 3742/* S1_Y_shift = 12, */ 3743/* S2_X_mask = 0x0f << 16, */ 3744/* S2_X_shift = 16, */ 3745/* S2_Y_mask = 0x0f << 20, */ 3746/* S2_Y_shift = 20, */ 3747/* S3_X_mask = 0x0f << 24, */ 3748/* S3_X_shift = 24, */ 3749/* S3_Y_mask = 0x0f << 28, */ 3750/* S3_Y_shift = 28, */ 3751 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 = 0x00028c2c, 3752/* S4_X_mask = 0x0f << 0, */ 3753/* S4_X_shift = 0, */ 3754/* S4_Y_mask = 0x0f << 4, */ 3755/* S4_Y_shift = 4, */ 3756/* S5_X_mask = 0x0f << 8, */ 3757/* S5_X_shift = 8, */ 3758/* S5_Y_mask = 0x0f << 12, */ 3759/* S5_Y_shift = 12, */ 3760/* S6_X_mask = 0x0f << 16, */ 3761/* S6_X_shift = 16, */ 3762/* S6_Y_mask = 0x0f << 20, */ 3763/* S6_Y_shift = 20, */ 3764/* S7_X_mask = 0x0f << 24, */ 3765/* S7_X_shift = 24, */ 3766/* S7_Y_mask = 0x0f << 28, */ 3767/* S7_Y_shift = 28, */ 3768 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 = 0x00028c30, 3769/* S8_X_mask = 0x0f << 0, */ 3770/* S8_X_shift = 0, */ 3771/* S8_Y_mask = 0x0f << 4, */ 3772/* S8_Y_shift = 4, */ 3773/* S9_X_mask = 0x0f << 8, */ 3774/* S9_X_shift = 8, */ 3775/* S9_Y_mask = 0x0f << 12, */ 3776/* S9_Y_shift = 12, */ 3777/* S10_X_mask = 0x0f << 16, */ 3778/* S10_X_shift = 16, */ 3779/* S10_Y_mask = 0x0f << 20, */ 3780/* S10_Y_shift = 20, */ 3781/* S11_X_mask = 0x0f << 24, */ 3782/* S11_X_shift = 24, */ 3783/* S11_Y_mask = 0x0f << 28, */ 3784/* S11_Y_shift = 28, */ 3785 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 = 0x00028c34, 3786/* S12_X_mask = 0x0f << 0, */ 3787/* S12_X_shift = 0, */ 3788/* S12_Y_mask = 0x0f << 4, */ 3789/* S12_Y_shift = 4, */ 3790/* S13_X_mask = 0x0f << 8, */ 3791/* S13_X_shift = 8, */ 3792/* S13_Y_mask = 0x0f << 12, */ 3793/* S13_Y_shift = 12, */ 3794/* S14_X_mask = 0x0f << 16, */ 3795/* S14_X_shift = 16, */ 3796/* S14_Y_mask = 0x0f << 20, */ 3797/* S14_Y_shift = 20, */ 3798/* S15_X_mask = 0x0f << 24, */ 3799/* S15_X_shift = 24, */ 3800/* S15_Y_mask = 0x0f << 28, */ 3801/* S15_Y_shift = 28, */ 3802 PA_SC_AA_MASK_X0Y0_X1Y0 = 0x00028c38, 3803 AA_MASK_X0Y0_mask = 0xffff << 0, 3804 AA_MASK_X0Y0_shift = 0, 3805 AA_MASK_X1Y0_mask = 0xffff << 16, 3806 AA_MASK_X1Y0_shift = 16, 3807 PA_SC_AA_MASK_X0Y1_X1Y1 = 0x00028c3c, 3808 AA_MASK_X0Y1_mask = 0xffff << 0, 3809 AA_MASK_X0Y1_shift = 0, 3810 AA_MASK_X1Y1_mask = 0xffff << 16, 3811 AA_MASK_X1Y1_shift = 16, 3812 VGT_VERTEX_REUSE_BLOCK_CNTL = 0x00028c58, 3813 VTX_REUSE_DEPTH_mask = 0xff << 0, 3814 VTX_REUSE_DEPTH_shift = 0, 3815 VGT_OUT_DEALLOC_CNTL = 0x00028c5c, 3816 DEALLOC_DIST_mask = 0x7f << 0, 3817 DEALLOC_DIST_shift = 0, 3818 CB_COLOR0_BASE = 0x00028c60, 3819 CB_COLOR0_BASE_num = 12, 3820 CB_COLOR0_BASE_offset = 51, 3821 CB_COLOR0_PITCH = 0x00028c64, 3822 CB_COLOR0_PITCH_num = 12, 3823 CB_COLOR0_PITCH_offset = 51, 3824 CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff << 0, 3825 CB_COLOR0_PITCH__TILE_MAX_shift = 0, 3826 CB_COLOR0_SLICE = 0x00028c68, 3827 CB_COLOR0_SLICE_num = 12, 3828 CB_COLOR0_SLICE_offset = 51, 3829 CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff << 0, 3830 CB_COLOR0_SLICE__TILE_MAX_shift = 0, 3831 CB_COLOR0_VIEW = 0x00028c6c, 3832 CB_COLOR0_VIEW_num = 12, 3833 CB_COLOR0_VIEW_offset = 51, 3834/* SLICE_START_mask = 0x7ff << 0, */ 3835/* SLICE_START_shift = 0, */ 3836/* SLICE_MAX_mask = 0x7ff << 13, */ 3837/* SLICE_MAX_shift = 13, */ 3838 CB_COLOR0_INFO = 0x00028c70, 3839 CB_COLOR0_INFO_num = 12, 3840 CB_COLOR0_INFO_offset = 51, 3841 ENDIAN_mask = 0x03 << 0, 3842 ENDIAN_shift = 0, 3843 ENDIAN_NONE = 0x00, 3844 ENDIAN_8IN16 = 0x01, 3845 ENDIAN_8IN32 = 0x02, 3846 ENDIAN_8IN64 = 0x03, 3847 CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2, 3848 CB_COLOR0_INFO__FORMAT_shift = 2, 3849 COLOR_INVALID = 0x00, 3850 COLOR_8 = 0x01, 3851 COLOR_16 = 0x05, 3852 COLOR_16_FLOAT = 0x06, 3853 COLOR_8_8 = 0x07, 3854 COLOR_5_6_5 = 0x08, 3855 COLOR_1_5_5_5 = 0x0a, 3856 COLOR_4_4_4_4 = 0x0b, 3857 COLOR_5_5_5_1 = 0x0c, 3858 COLOR_32 = 0x0d, 3859 COLOR_32_FLOAT = 0x0e, 3860 COLOR_16_16 = 0x0f, 3861 COLOR_16_16_FLOAT = 0x10, 3862 COLOR_8_24 = 0x11, 3863 COLOR_24_8 = 0x13, 3864 COLOR_10_11_11 = 0x15, 3865 COLOR_10_11_11_FLOAT = 0x16, 3866 COLOR_2_10_10_10 = 0x19, 3867 COLOR_8_8_8_8 = 0x1a, 3868 COLOR_10_10_10_2 = 0x1b, 3869 COLOR_X24_8_32_FLOAT = 0x1c, 3870 COLOR_32_32 = 0x1d, 3871 COLOR_32_32_FLOAT = 0x1e, 3872 COLOR_16_16_16_16 = 0x1f, 3873 COLOR_16_16_16_16_FLOAT = 0x20, 3874 COLOR_32_32_32_32 = 0x22, 3875 COLOR_32_32_32_32_FLOAT = 0x23, 3876 CB_COLOR0_INFO__ARRAY_MODE_mask = 0x0f << 8, 3877 CB_COLOR0_INFO__ARRAY_MODE_shift = 8, 3878 ARRAY_LINEAR_GENERAL = 0x00, 3879 ARRAY_LINEAR_ALIGNED = 0x01, 3880/* ARRAY_1D_TILED_THIN1 = 0x02, */ 3881/* ARRAY_2D_TILED_THIN1 = 0x04, */ 3882 NUMBER_TYPE_mask = 0x07 << 12, 3883 NUMBER_TYPE_shift = 12, 3884 NUMBER_UNORM = 0x00, 3885 NUMBER_SNORM = 0x01, 3886 NUMBER_UINT = 0x04, 3887 NUMBER_SINT = 0x05, 3888 NUMBER_SRGB = 0x06, 3889 NUMBER_FLOAT = 0x07, 3890 COMP_SWAP_mask = 0x03 << 15, 3891 COMP_SWAP_shift = 15, 3892 SWAP_STD = 0x00, 3893 SWAP_ALT = 0x01, 3894 SWAP_STD_REV = 0x02, 3895 SWAP_ALT_REV = 0x03, 3896 FAST_CLEAR_bit = 1 << 17, 3897 COMPRESSION_bit = 1 << 18, 3898 BLEND_CLAMP_bit = 1 << 19, 3899 BLEND_BYPASS_bit = 1 << 20, 3900 SIMPLE_FLOAT_bit = 1 << 21, 3901 CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22, 3902 TILE_COMPACT_bit = 1 << 23, 3903 SOURCE_FORMAT_mask = 0x03 << 24, 3904 SOURCE_FORMAT_shift = 24, 3905 EXPORT_4C_32BPC = 0x00, 3906 EXPORT_4C_16BPC = 0x01, 3907 EXPORT_2C_32BPC_GR = 0x02, 3908 EXPORT_2C_32BPC_AR = 0x03, 3909 RAT_bit = 1 << 26, 3910 RESOURCE_TYPE_mask = 0x07 << 27, 3911 RESOURCE_TYPE_shift = 27, 3912 BUFFER = 0x00, 3913 TEXTURE1D = 0x01, 3914 TEXTURE1DARRAY = 0x02, 3915 TEXTURE2D = 0x03, 3916 TEXTURE2DARRAY = 0x04, 3917 TEXTURE3D = 0x05, 3918 STRUCTUREDBUFFER = 0x06, 3919 SOURCE_NUMBER_TYPE_mask = 0x03 << 30, 3920 SOURCE_NUMBER_TYPE_shift = 30, 3921 EXPORT_FLOAT = 0x00, 3922 EXPORT_INT = 0x01, 3923 EXPORT_UNORM = 0x02, 3924 EXPORT_SNORM = 0x03, 3925 CB_COLOR0_ATTRIB = 0x00028c74, 3926 CB_COLOR0_ATTRIB_num = 12, 3927 CB_COLOR0_ATTRIB_offset = 51, 3928 IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, 3929 CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4, 3930 CB_COLOR0_ATTRIB__TILE_SPLIT_mask = 0x0f << 5, 3931 CB_COLOR0_ATTRIB__TILE_SPLIT_shift = 5, 3932/* ADDR_SURF_TILE_SPLIT_64B = 0x00, */ 3933/* ADDR_SURF_TILE_SPLIT_128B = 0x01, */ 3934/* ADDR_SURF_TILE_SPLIT_256B = 0x02, */ 3935/* ADDR_SURF_TILE_SPLIT_512B = 0x03, */ 3936/* ADDR_SURF_TILE_SPLIT_1KB = 0x04, */ 3937/* ADDR_SURF_TILE_SPLIT_2KB = 0x05, */ 3938/* ADDR_SURF_TILE_SPLIT_4KB = 0x06, */ 3939 CB_COLOR0_ATTRIB__NUM_BANKS_mask = 0x03 << 10, 3940 CB_COLOR0_ATTRIB__NUM_BANKS_shift = 10, 3941/* ADDR_SURF_2_BANK = 0x00, */ 3942/* ADDR_SURF_4_BANK = 0x01, */ 3943/* ADDR_SURF_8_BANK = 0x02, */ 3944/* ADDR_SURF_16_BANK = 0x03, */ 3945 CB_COLOR0_ATTRIB__BANK_WIDTH_mask = 0x03 << 13, 3946 CB_COLOR0_ATTRIB__BANK_WIDTH_shift = 13, 3947/* ADDR_SURF_BANK_WIDTH_1 = 0x00, */ 3948/* ADDR_SURF_BANK_WIDTH_2 = 0x01, */ 3949/* ADDR_SURF_BANK_WIDTH_4 = 0x02, */ 3950/* ADDR_SURF_BANK_WIDTH_8 = 0x03, */ 3951 CB_COLOR0_ATTRIB__BANK_HEIGHT_mask = 0x03 << 16, 3952 CB_COLOR0_ATTRIB__BANK_HEIGHT_shift = 16, 3953/* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ 3954/* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ 3955/* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ 3956/* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ 3957 CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_mask = 0x03 << 19, 3958 CB_COLOR0_ATTRIB__MACRO_TILE_ASPECT_shift = 19, 3959/* ADDR_SURF_MACRO_ASPECT_1 = 0x00, */ 3960/* ADDR_SURF_MACRO_ASPECT_2 = 0x01, */ 3961/* ADDR_SURF_MACRO_ASPECT_4 = 0x02, */ 3962/* ADDR_SURF_MACRO_ASPECT_8 = 0x03, */ 3963 FMASK_BANK_HEIGHT_mask = 0x03 << 22, 3964 FMASK_BANK_HEIGHT_shift = 22, 3965/* ADDR_SURF_BANK_HEIGHT_1 = 0x00, */ 3966/* ADDR_SURF_BANK_HEIGHT_2 = 0x01, */ 3967/* ADDR_SURF_BANK_HEIGHT_4 = 0x02, */ 3968/* ADDR_SURF_BANK_HEIGHT_8 = 0x03, */ 3969 CB_COLOR0_ATTRIB__NUM_SAMPLES_mask = 0x07 << 24, 3970 CB_COLOR0_ATTRIB__NUM_SAMPLES_shift = 24, 3971 NUM_FRAGMENTS_mask = 0x03 << 27, 3972 NUM_FRAGMENTS_shift = 27, 3973 FORCE_DST_ALPHA_1_bit = 1 << 31, 3974 CB_COLOR0_DIM = 0x00028c78, 3975 CB_COLOR0_DIM_num = 12, 3976 CB_COLOR0_DIM_offset = 51, 3977 WIDTH_MAX_mask = 0xffff << 0, 3978 WIDTH_MAX_shift = 0, 3979 HEIGHT_MAX_mask = 0xffff << 16, 3980 HEIGHT_MAX_shift = 16, 3981 CB_COLOR0_CMASK = 0x00028c7c, 3982 CB_COLOR0_CMASK_num = 8, 3983 CB_COLOR0_CMASK_offset = 60, 3984 CB_COLOR0_CMASK_SLICE = 0x00028c80, 3985 CB_COLOR0_CMASK_SLICE_num = 8, 3986 CB_COLOR0_CMASK_SLICE_offset = 60, 3987 CB_COLOR0_CMASK_SLICE__TILE_MAX_mask = 0x3fff << 0, 3988 CB_COLOR0_CMASK_SLICE__TILE_MAX_shift = 0, 3989 CB_COLOR0_FMASK = 0x00028c84, 3990 CB_COLOR0_FMASK_num = 8, 3991 CB_COLOR0_FMASK_offset = 60, 3992 CB_COLOR0_FMASK_SLICE = 0x00028c88, 3993 CB_COLOR0_FMASK_SLICE_num = 8, 3994 CB_COLOR0_FMASK_SLICE_offset = 60, 3995 CB_COLOR0_FMASK_SLICE__TILE_MAX_mask = 0x3fffff << 0, 3996 CB_COLOR0_FMASK_SLICE__TILE_MAX_shift = 0, 3997 CB_COLOR0_CLEAR_WORD0 = 0x00028c8c, 3998 CB_COLOR0_CLEAR_WORD0_num = 8, 3999 CB_COLOR0_CLEAR_WORD0_offset = 60, 4000 CB_COLOR0_CLEAR_WORD1 = 0x00028c90, 4001 CB_COLOR0_CLEAR_WORD1_num = 8, 4002 CB_COLOR0_CLEAR_WORD1_offset = 60, 4003 CB_COLOR0_CLEAR_WORD2 = 0x00028c94, 4004 CB_COLOR0_CLEAR_WORD2_num = 8, 4005 CB_COLOR0_CLEAR_WORD2_offset = 60, 4006 CB_COLOR0_CLEAR_WORD3 = 0x00028c98, 4007 CB_COLOR0_CLEAR_WORD3_num = 8, 4008 CB_COLOR0_CLEAR_WORD3_offset = 60, 4009 SQ_ALU_CONST_CACHE_HS_0 = 0x00028f00, 4010 SQ_ALU_CONST_CACHE_HS_0_num = 16, 4011 SQ_ALU_CONST_CACHE_LS_0 = 0x00028f40, 4012 SQ_ALU_CONST_CACHE_LS_0_num = 16, 4013 SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x00028f80, 4014 SQ_ALU_CONST_BUFFER_SIZE_HS_0_num = 16, 4015 SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_mask = 0x1ff << 0, 4016 SQ_ALU_CONST_BUFFER_SIZE_HS_0__DATA_shift = 0, 4017 SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x00028fc0, 4018 SQ_ALU_CONST_BUFFER_SIZE_LS_0_num = 16, 4019 SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_mask = 0x1ff << 0, 4020 SQ_ALU_CONST_BUFFER_SIZE_LS_0__DATA_shift = 0, 4021 SQ_VTX_CONSTANT_WORD0_0 = 0x00030000, 4022 SQ_TEX_RESOURCE_WORD0_0 = 0x00030000, 4023 DIM_mask = 0x07 << 0, 4024 DIM_shift = 0, 4025 SQ_TEX_DIM_1D = 0x00, 4026 SQ_TEX_DIM_2D = 0x01, 4027 SQ_TEX_DIM_3D = 0x02, 4028 SQ_TEX_DIM_CUBEMAP = 0x03, 4029 SQ_TEX_DIM_1D_ARRAY = 0x04, 4030 SQ_TEX_DIM_2D_ARRAY = 0x05, 4031 SQ_TEX_DIM_2D_MSAA = 0x06, 4032 SQ_TEX_DIM_2D_ARRAY_MSAA = 0x07, 4033/* IGNORE_SHADER_ENGINE_TILING_bit = 1 << 3, */ 4034 SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_mask= 0x03 << 4, 4035 SQ_TEX_RESOURCE_WORD0_0__NON_DISP_TILING_ORDER_shift= 4, 4036 PITCH_mask = 0xfff << 6, 4037 PITCH_shift = 6, 4038 TEX_WIDTH_mask = 0x3fff << 18, 4039 TEX_WIDTH_shift = 18, 4040 SQ_VTX_CONSTANT_WORD1_0 = 0x00030004, 4041 SQ_TEX_RESOURCE_WORD1_0 = 0x00030004, 4042 TEX_HEIGHT_mask = 0x3fff << 0, 4043 TEX_HEIGHT_shift = 0, 4044 TEX_DEPTH_mask = 0x1fff << 14, 4045 TEX_DEPTH_shift = 14, 4046 SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0x0f << 28, 4047 SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28, 4048 SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, 4049 BASE_ADDRESS_HI_mask = 0xff << 0, 4050 BASE_ADDRESS_HI_shift = 0, 4051 SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask = 0xfff << 8, 4052 SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift = 8, 4053 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 4054 SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift = 20, 4055 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask = 0x03 << 26, 4056 SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift = 26, 4057/* SQ_NUM_FORMAT_NORM = 0x00, */ 4058/* SQ_NUM_FORMAT_INT = 0x01, */ 4059/* SQ_NUM_FORMAT_SCALED = 0x02, */ 4060 SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit = 1 << 28, 4061 SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL_bit = 1 << 29, 4062 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask = 0x03 << 30, 4063 SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift = 30, 4064/* SQ_ENDIAN_NONE = 0x00, */ 4065/* SQ_ENDIAN_8IN16 = 0x01, */ 4066/* SQ_ENDIAN_8IN32 = 0x02, */ 4067 SQ_TEX_RESOURCE_WORD2_0 = 0x00030008, 4068 SQ_VTX_CONSTANT_WORD3_0 = 0x0003000c, 4069 CACHE_SWIZZLE_bit = 1 << 0, 4070 SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2, 4071 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x07 << 3, 4072 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3, 4073/* SQ_SEL_X = 0x00, */ 4074/* SQ_SEL_Y = 0x01, */ 4075/* SQ_SEL_Z = 0x02, */ 4076/* SQ_SEL_W = 0x03, */ 4077/* SQ_SEL_0 = 0x04, */ 4078/* SQ_SEL_1 = 0x05, */ 4079 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x07 << 6, 4080 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6, 4081/* SQ_SEL_X = 0x00, */ 4082/* SQ_SEL_Y = 0x01, */ 4083/* SQ_SEL_Z = 0x02, */ 4084/* SQ_SEL_W = 0x03, */ 4085/* SQ_SEL_0 = 0x04, */ 4086/* SQ_SEL_1 = 0x05, */ 4087 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x07 << 9, 4088 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9, 4089/* SQ_SEL_X = 0x00, */ 4090/* SQ_SEL_Y = 0x01, */ 4091/* SQ_SEL_Z = 0x02, */ 4092/* SQ_SEL_W = 0x03, */ 4093/* SQ_SEL_0 = 0x04, */ 4094/* SQ_SEL_1 = 0x05, */ 4095 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x07 << 12, 4096 SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12, 4097/* SQ_SEL_X = 0x00, */ 4098/* SQ_SEL_Y = 0x01, */ 4099/* SQ_SEL_Z = 0x02, */ 4100/* SQ_SEL_W = 0x03, */ 4101/* SQ_SEL_0 = 0x04, */ 4102/* SQ_SEL_1 = 0x05, */ 4103 SQ_TEX_RESOURCE_WORD3_0 = 0x0003000c, 4104 SQ_TEX_RESOURCE_WORD4_0 = 0x00030010, 4105 FORMAT_COMP_X_mask = 0x03 << 0, 4106 FORMAT_COMP_X_shift = 0, 4107 SQ_FORMAT_COMP_UNSIGNED = 0x00, 4108 SQ_FORMAT_COMP_SIGNED = 0x01, 4109 SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, 4110 FORMAT_COMP_Y_mask = 0x03 << 2, 4111 FORMAT_COMP_Y_shift = 2, 4112/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ 4113/* SQ_FORMAT_COMP_SIGNED = 0x01, */ 4114/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ 4115 FORMAT_COMP_Z_mask = 0x03 << 4, 4116 FORMAT_COMP_Z_shift = 4, 4117/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ 4118/* SQ_FORMAT_COMP_SIGNED = 0x01, */ 4119/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ 4120 FORMAT_COMP_W_mask = 0x03 << 6, 4121 FORMAT_COMP_W_shift = 6, 4122/* SQ_FORMAT_COMP_UNSIGNED = 0x00, */ 4123/* SQ_FORMAT_COMP_SIGNED = 0x01, */ 4124/* SQ_FORMAT_COMP_UNSIGNED_BIASED = 0x02, */ 4125 SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_mask = 0x03 << 8, 4126 SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL_shift = 8, 4127/* SQ_NUM_FORMAT_NORM = 0x00, */ 4128/* SQ_NUM_FORMAT_INT = 0x01, */ 4129/* SQ_NUM_FORMAT_SCALED = 0x02, */ 4130 SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL_bit = 1 << 10, 4131 SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit = 1 << 11, 4132 SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask = 0x03 << 12, 4133 SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift = 12, 4134/* SQ_ENDIAN_NONE = 0x00, */ 4135/* SQ_ENDIAN_8IN16 = 0x01, */ 4136/* SQ_ENDIAN_8IN32 = 0x02, */ 4137 LOG2_NUM_FRAGMENTS_mask = 0x03 << 14, 4138 LOG2_NUM_FRAGMENTS_shift = 14, 4139 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask = 0x07 << 16, 4140 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift = 16, 4141/* SQ_SEL_X = 0x00, */ 4142/* SQ_SEL_Y = 0x01, */ 4143/* SQ_SEL_Z = 0x02, */ 4144/* SQ_SEL_W = 0x03, */ 4145/* SQ_SEL_0 = 0x04, */ 4146/* SQ_SEL_1 = 0x05, */ 4147 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask = 0x07 << 19, 4148 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift = 19, 4149/* SQ_SEL_X = 0x00, */ 4150/* SQ_SEL_Y = 0x01, */ 4151/* SQ_SEL_Z = 0x02, */ 4152/* SQ_SEL_W = 0x03, */ 4153/* SQ_SEL_0 = 0x04, */ 4154/* SQ_SEL_1 = 0x05, */ 4155 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask = 0x07 << 22, 4156 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift = 22, 4157/* SQ_SEL_X = 0x00, */ 4158/* SQ_SEL_Y = 0x01, */ 4159/* SQ_SEL_Z = 0x02, */ 4160/* SQ_SEL_W = 0x03, */ 4161/* SQ_SEL_0 = 0x04, */ 4162/* SQ_SEL_1 = 0x05, */ 4163 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask = 0x07 << 25, 4164 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift = 25, 4165/* SQ_SEL_X = 0x00, */ 4166/* SQ_SEL_Y = 0x01, */ 4167/* SQ_SEL_Z = 0x02, */ 4168/* SQ_SEL_W = 0x03, */ 4169/* SQ_SEL_0 = 0x04, */ 4170/* SQ_SEL_1 = 0x05, */ 4171 BASE_LEVEL_mask = 0x0f << 28, 4172 BASE_LEVEL_shift = 28, 4173 SQ_VTX_CONSTANT_WORD4_0 = 0x00030010, 4174 SQ_TEX_RESOURCE_WORD5_0 = 0x00030014, 4175 LAST_LEVEL_mask = 0x0f << 0, 4176 LAST_LEVEL_shift = 0, 4177 BASE_ARRAY_mask = 0x1fff << 4, 4178 BASE_ARRAY_shift = 4, 4179 LAST_ARRAY_mask = 0x1fff << 17, 4180 LAST_ARRAY_shift = 17, 4181 SQ_TEX_RESOURCE_WORD6_0 = 0x00030018, 4182 PERF_MODULATION_mask = 0x07 << 3, 4183 PERF_MODULATION_shift = 3, 4184 INTERLACED_bit = 1 << 6, 4185 SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8, 4186 SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, 4187 SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x07 << 29, 4188 SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29, 4189 SQ_ADDR_SURF_TILE_SPLIT_64B = 0x00, 4190 SQ_ADDR_SURF_TILE_SPLIT_128B = 0x01, 4191 SQ_ADDR_SURF_TILE_SPLIT_256B = 0x02, 4192 SQ_ADDR_SURF_TILE_SPLIT_512B = 0x03, 4193 SQ_ADDR_SURF_TILE_SPLIT_1KB = 0x04, 4194 SQ_ADDR_SURF_TILE_SPLIT_2KB = 0x05, 4195 SQ_ADDR_SURF_TILE_SPLIT_4KB = 0x06, 4196 SQ_VTX_CONSTANT_WORD7_0 = 0x0003001c, 4197 SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x03 << 30, 4198 SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30, 4199 SQ_TEX_VTX_INVALID_TEXTURE = 0x00, 4200 SQ_TEX_VTX_INVALID_BUFFER = 0x01, 4201 SQ_TEX_VTX_VALID_TEXTURE = 0x02, 4202 SQ_TEX_VTX_VALID_BUFFER = 0x03, 4203 SQ_TEX_RESOURCE_WORD7_0 = 0x0003001c, 4204 SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f << 0, 4205 SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, 4206 SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x03 << 6, 4207 SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, 4208 SQ_ADDR_SURF_MACRO_ASPECT_1 = 0x00, 4209 SQ_ADDR_SURF_MACRO_ASPECT_2 = 0x01, 4210 SQ_ADDR_SURF_MACRO_ASPECT_4 = 0x02, 4211 SQ_ADDR_SURF_MACRO_ASPECT_8 = 0x03, 4212 SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x03 << 8, 4213 SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, 4214 SQ_ADDR_SURF_BANK_WH_1 = 0x00, 4215 SQ_ADDR_SURF_BANK_WH_2 = 0x01, 4216 SQ_ADDR_SURF_BANK_WH_4 = 0x02, 4217 SQ_ADDR_SURF_BANK_WH_8 = 0x03, 4218 SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x03 << 10, 4219 SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10, 4220/* SQ_ADDR_SURF_BANK_WH_1 = 0x00, */ 4221/* SQ_ADDR_SURF_BANK_WH_2 = 0x01, */ 4222/* SQ_ADDR_SURF_BANK_WH_4 = 0x02, */ 4223/* SQ_ADDR_SURF_BANK_WH_8 = 0x03, */ 4224 DEPTH_SAMPLE_ORDER_bit = 1 << 15, 4225 SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x03 << 16, 4226 SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16, 4227 SQ_ADDR_SURF_2_BANK = 0x00, 4228 SQ_ADDR_SURF_4_BANK = 0x01, 4229 SQ_ADDR_SURF_8_BANK = 0x02, 4230 SQ_ADDR_SURF_16_BANK = 0x03, 4231 SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x03 << 30, 4232 SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30, 4233/* SQ_TEX_VTX_INVALID_TEXTURE = 0x00, */ 4234/* SQ_TEX_VTX_INVALID_BUFFER = 0x01, */ 4235/* SQ_TEX_VTX_VALID_TEXTURE = 0x02, */ 4236/* SQ_TEX_VTX_VALID_BUFFER = 0x03, */ 4237 SQ_LOOP_CONST_DX10_0 = 0x0003a200, 4238 SQ_LOOP_CONST_0 = 0x0003a200, 4239 SQ_LOOP_CONST_0__COUNT_mask = 0xfff << 0, 4240 SQ_LOOP_CONST_0__COUNT_shift = 0, 4241 INIT_mask = 0xfff << 12, 4242 INIT_shift = 12, 4243 INC_mask = 0xff << 24, 4244 INC_shift = 24, 4245 SQ_JUMPTABLE_CONST_0 = 0x0003a200, 4246 CONST_A_mask = 0xff << 0, 4247 CONST_A_shift = 0, 4248 CONST_B_mask = 0xff << 8, 4249 CONST_B_shift = 8, 4250 CONST_C_mask = 0xff << 16, 4251 CONST_C_shift = 16, 4252 CONST_D_mask = 0xff << 24, 4253 CONST_D_shift = 24, 4254 SQ_BOOL_CONST_0 = 0x0003a500, 4255 SQ_BOOL_CONST_0_num = 6, 4256 SQ_TEX_SAMPLER_WORD0_0 = 0x0003c000, 4257 CLAMP_X_mask = 0x07 << 0, 4258 CLAMP_X_shift = 0, 4259 SQ_TEX_WRAP = 0x00, 4260 SQ_TEX_MIRROR = 0x01, 4261 SQ_TEX_CLAMP_LAST_TEXEL = 0x02, 4262 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, 4263 SQ_TEX_CLAMP_HALF_BORDER = 0x04, 4264 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, 4265 SQ_TEX_CLAMP_BORDER = 0x06, 4266 SQ_TEX_MIRROR_ONCE_BORDER = 0x07, 4267 CLAMP_Y_mask = 0x07 << 3, 4268 CLAMP_Y_shift = 3, 4269/* SQ_TEX_WRAP = 0x00, */ 4270/* SQ_TEX_MIRROR = 0x01, */ 4271/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ 4272/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ 4273/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ 4274/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ 4275/* SQ_TEX_CLAMP_BORDER = 0x06, */ 4276/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ 4277 CLAMP_Z_mask = 0x07 << 6, 4278 CLAMP_Z_shift = 6, 4279/* SQ_TEX_WRAP = 0x00, */ 4280/* SQ_TEX_MIRROR = 0x01, */ 4281/* SQ_TEX_CLAMP_LAST_TEXEL = 0x02, */ 4282/* SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x03, */ 4283/* SQ_TEX_CLAMP_HALF_BORDER = 0x04, */ 4284/* SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x05, */ 4285/* SQ_TEX_CLAMP_BORDER = 0x06, */ 4286/* SQ_TEX_MIRROR_ONCE_BORDER = 0x07, */ 4287 XY_MAG_FILTER_mask = 0x03 << 9, 4288 XY_MAG_FILTER_shift = 9, 4289 SQ_TEX_XY_FILTER_POINT = 0x00, 4290 SQ_TEX_XY_FILTER_BILINEAR = 0x01, 4291 XY_MIN_FILTER_mask = 0x03 << 11, 4292 XY_MIN_FILTER_shift = 11, 4293/* SQ_TEX_XY_FILTER_POINT = 0x00, */ 4294/* SQ_TEX_XY_FILTER_BILINEAR = 0x01, */ 4295 Z_FILTER_mask = 0x03 << 13, 4296 Z_FILTER_shift = 13, 4297 SQ_TEX_Z_FILTER_NONE = 0x00, 4298 SQ_TEX_Z_FILTER_POINT = 0x01, 4299 SQ_TEX_Z_FILTER_LINEAR = 0x02, 4300 MIP_FILTER_mask = 0x03 << 15, 4301 MIP_FILTER_shift = 15, 4302/* SQ_TEX_Z_FILTER_NONE = 0x00, */ 4303/* SQ_TEX_Z_FILTER_POINT = 0x01, */ 4304/* SQ_TEX_Z_FILTER_LINEAR = 0x02, */ 4305 BORDER_COLOR_TYPE_mask = 0x03 << 20, 4306 BORDER_COLOR_TYPE_shift = 20, 4307 SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00, 4308 SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x01, 4309 SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x02, 4310 SQ_TEX_BORDER_COLOR_REGISTER = 0x03, 4311 DEPTH_COMPARE_FUNCTION_mask = 0x07 << 22, 4312 DEPTH_COMPARE_FUNCTION_shift = 22, 4313 SQ_TEX_DEPTH_COMPARE_NEVER = 0x00, 4314 SQ_TEX_DEPTH_COMPARE_LESS = 0x01, 4315 SQ_TEX_DEPTH_COMPARE_EQUAL = 0x02, 4316 SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x03, 4317 SQ_TEX_DEPTH_COMPARE_GREATER = 0x04, 4318 SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x05, 4319 SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x06, 4320 SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x07, 4321 FORCE_UNNORMALIZED_bit = 1 << 25, 4322 SQ_TEX_SAMPLER_WORD1_0 = 0x0003c004, 4323 SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff << 0, 4324 SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, 4325 MAX_LOD_mask = 0xfff << 12, 4326 MAX_LOD_shift = 12, 4327 PERF_MIP_mask = 0x0f << 24, 4328 PERF_MIP_shift = 24, 4329 PERF_Z_mask = 0x0f << 28, 4330 PERF_Z_shift = 28, 4331 SQ_TEX_SAMPLER_WORD2_0 = 0x0003c008, 4332 SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff << 0, 4333 SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, 4334 LOD_BIAS_SEC_mask = 0x3f << 14, 4335 LOD_BIAS_SEC_shift = 14, 4336 MC_COORD_TRUNCATE_bit = 1 << 20, 4337 SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21, 4338 TRUNCATE_COORD_bit = 1 << 28, 4339 SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29, 4340 SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31, 4341 SQ_VTX_BASE_VTX_LOC = 0x0003cff0, 4342 SQ_VTX_START_INST_LOC = 0x0003cff4, 4343 SQ_TEX_SAMPLER_CLEAR = 0x0003ff00, 4344 SQ_TEX_RESOURCE_CLEAR = 0x0003ff04, 4345 SQ_LOOP_BOOL_CLEAR = 0x0003ff08, 4346 PA_CL_GB_VERT_DISC_ADJ = 0x0028be8c, 4347 4348} ; 4349 4350#endif /* _CAYMAN_REG_AUTO */ 4351 4352