1/* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23/*++ 24 25Module Name: 26 27CD_OPCODEs.h 28 29Abstract: 30 31Defines Command Decoder OPCODEs 32 33Revision History: 34 35NEG:24.09.2002 Initiated. 36--*/ 37#ifndef _CD_OPCODES_H_ 38#define _CD_OPCODES_H_ 39 40typedef enum _OPCODE { 41 Reserved_00= 0, // 0 = 0x00 42 // MOVE_ group 43 MOVE_REG_OPCODE, // 1 = 0x01 44 FirstValidCommand=MOVE_REG_OPCODE, 45 MOVE_PS_OPCODE, // 2 = 0x02 46 MOVE_WS_OPCODE, // 3 = 0x03 47 MOVE_FB_OPCODE, // 4 = 0x04 48 MOVE_PLL_OPCODE, // 5 = 0x05 49 MOVE_MC_OPCODE, // 6 = 0x06 50 // Logic group 51 AND_REG_OPCODE, // 7 = 0x07 52 AND_PS_OPCODE, // 8 = 0x08 53 AND_WS_OPCODE, // 9 = 0x09 54 AND_FB_OPCODE, // 10 = 0x0A 55 AND_PLL_OPCODE, // 11 = 0x0B 56 AND_MC_OPCODE, // 12 = 0x0C 57 OR_REG_OPCODE, // 13 = 0x0D 58 OR_PS_OPCODE, // 14 = 0x0E 59 OR_WS_OPCODE, // 15 = 0x0F 60 OR_FB_OPCODE, // 16 = 0x10 61 OR_PLL_OPCODE, // 17 = 0x11 62 OR_MC_OPCODE, // 18 = 0x12 63 SHIFT_LEFT_REG_OPCODE, // 19 = 0x13 64 SHIFT_LEFT_PS_OPCODE, // 20 = 0x14 65 SHIFT_LEFT_WS_OPCODE, // 21 = 0x15 66 SHIFT_LEFT_FB_OPCODE, // 22 = 0x16 67 SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17 68 SHIFT_LEFT_MC_OPCODE, // 24 = 0x18 69 SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19 70 SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A 71 SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B 72 SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C 73 SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D 74 SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E 75 // Arithmetic group 76 MUL_REG_OPCODE, // 31 = 0x1F 77 MUL_PS_OPCODE, // 32 = 0x20 78 MUL_WS_OPCODE, // 33 = 0x21 79 MUL_FB_OPCODE, // 34 = 0x22 80 MUL_PLL_OPCODE, // 35 = 0x23 81 MUL_MC_OPCODE, // 36 = 0x24 82 DIV_REG_OPCODE, // 37 = 0x25 83 DIV_PS_OPCODE, // 38 = 0x26 84 DIV_WS_OPCODE, // 39 = 0x27 85 DIV_FB_OPCODE, // 40 = 0x28 86 DIV_PLL_OPCODE, // 41 = 0x29 87 DIV_MC_OPCODE, // 42 = 0x2A 88 ADD_REG_OPCODE, // 43 = 0x2B 89 ADD_PS_OPCODE, // 44 = 0x2C 90 ADD_WS_OPCODE, // 45 = 0x2D 91 ADD_FB_OPCODE, // 46 = 0x2E 92 ADD_PLL_OPCODE, // 47 = 0x2F 93 ADD_MC_OPCODE, // 48 = 0x30 94 SUB_REG_OPCODE, // 49 = 0x31 95 SUB_PS_OPCODE, // 50 = 0x32 96 SUB_WS_OPCODE, // 51 = 0x33 97 SUB_FB_OPCODE, // 52 = 0x34 98 SUB_PLL_OPCODE, // 53 = 0x35 99 SUB_MC_OPCODE, // 54 = 0x36 100 // Control grouop 101 SET_ATI_PORT_OPCODE, // 55 = 0x37 102 SET_PCI_PORT_OPCODE, // 56 = 0x38 103 SET_SYS_IO_PORT_OPCODE, // 57 = 0x39 104 SET_REG_BLOCK_OPCODE, // 58 = 0x3A 105 SET_FB_BASE_OPCODE, // 59 = 0x3B 106 COMPARE_REG_OPCODE, // 60 = 0x3C 107 COMPARE_PS_OPCODE, // 61 = 0x3D 108 COMPARE_WS_OPCODE, // 62 = 0x3E 109 COMPARE_FB_OPCODE, // 63 = 0x3F 110 COMPARE_PLL_OPCODE, // 64 = 0x40 111 COMPARE_MC_OPCODE, // 65 = 0x41 112 SWITCH_OPCODE, // 66 = 0x42 113 JUMP__OPCODE, // 67 = 0x43 114 JUMP_EQUAL_OPCODE, // 68 = 0x44 115 JUMP_BELOW_OPCODE, // 69 = 0x45 116 JUMP_ABOVE_OPCODE, // 70 = 0x46 117 JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47 118 JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48 119 JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49 120 TEST_REG_OPCODE, // 74 = 0x4A 121 TEST_PS_OPCODE, // 75 = 0x4B 122 TEST_WS_OPCODE, // 76 = 0x4C 123 TEST_FB_OPCODE, // 77 = 0x4D 124 TEST_PLL_OPCODE, // 78 = 0x4E 125 TEST_MC_OPCODE, // 79 = 0x4F 126 DELAY_MILLISEC_OPCODE, // 80 = 0x50 127 DELAY_MICROSEC_OPCODE, // 81 = 0x51 128 CALL_TABLE_OPCODE, // 82 = 0x52 129 REPEAT_OPCODE, // 83 = 0x53 130 // Miscellaneous group 131 CLEAR_REG_OPCODE, // 84 = 0x54 132 CLEAR_PS_OPCODE, // 85 = 0x55 133 CLEAR_WS_OPCODE, // 86 = 0x56 134 CLEAR_FB_OPCODE, // 87 = 0x57 135 CLEAR_PLL_OPCODE, // 88 = 0x58 136 CLEAR_MC_OPCODE, // 89 = 0x59 137 NOP_OPCODE, // 90 = 0x5A 138 EOT_OPCODE, // 91 = 0x5B 139 MASK_REG_OPCODE, // 92 = 0x5C 140 MASK_PS_OPCODE, // 93 = 0x5D 141 MASK_WS_OPCODE, // 94 = 0x5E 142 MASK_FB_OPCODE, // 95 = 0x5F 143 MASK_PLL_OPCODE, // 96 = 0x60 144 MASK_MC_OPCODE, // 97 = 0x61 145 // BIOS dedicated group 146 POST_CARD_OPCODE, // 98 = 0x62 147 BEEP_OPCODE, // 99 = 0x63 148 SAVE_REG_OPCODE, // 100 = 0x64 149 RESTORE_REG_OPCODE, // 101 = 0x65 150 SET_DATA_BLOCK_OPCODE, // 102 = 0x66 151 152 XOR_REG_OPCODE, // 103 = 0x67 153 XOR_PS_OPCODE, // 104 = 0x68 154 XOR_WS_OPCODE, // 105 = 0x69 155 XOR_FB_OPCODE, // 106 = 0x6a 156 XOR_PLL_OPCODE, // 107 = 0x6b 157 XOR_MC_OPCODE, // 108 = 0x6c 158 159 SHL_REG_OPCODE, // 109 = 0x6d 160 SHL_PS_OPCODE, // 110 = 0x6e 161 SHL_WS_OPCODE, // 111 = 0x6f 162 SHL_FB_OPCODE, // 112 = 0x70 163 SHL_PLL_OPCODE, // 113 = 0x71 164 SHL_MC_OPCODE, // 114 = 0x72 165 166 SHR_REG_OPCODE, // 115 = 0x73 167 SHR_PS_OPCODE, // 116 = 0x74 168 SHR_WS_OPCODE, // 117 = 0x75 169 SHR_FB_OPCODE, // 118 = 0x76 170 SHR_PLL_OPCODE, // 119 = 0x77 171 SHR_MC_OPCODE, // 120 = 0x78 172 173 DEBUG_OPCODE, // 121 = 0x79 174 CTB_DS_OPCODE, // 122 = 0x7A 175 176 LastValidCommand = CTB_DS_OPCODE, 177 // Extension specificaTOR 178 Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well 179 Reserved_FF = 255 // 255 = 0xFF 180}OPCODE; 181#endif // _CD_OPCODES_H_ 182