evergreen_reg.h revision 921a55d8
1/* 2 * Evergeen Register documentation 3 * 4 * Copyright (C) 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef _EVERGREEN_REG_H_ 25#define _EVERGREEN_REG_H_ 26 27/* 28 * Register definitions 29 */ 30 31#include "evergreen_reg_auto.h" 32 33enum { 34 SHADER_TYPE_PS, 35 SHADER_TYPE_VS, 36 SHADER_TYPE_GS, 37 SHADER_TYPE_HS, 38 SHADER_TYPE_LS, 39 SHADER_TYPE_CS, 40 SHADER_TYPE_FS, 41}; 42 43 44/* SET_*_REG offsets + ends */ 45enum { 46 SET_CONFIG_REG_offset = 0x00008000, 47 SET_CONFIG_REG_end = 0x0000ac00, 48 SET_CONTEXT_REG_offset = 0x00028000, 49 SET_CONTEXT_REG_end = 0x00029000, 50 SET_RESOURCE_offset = 0x00030000, 51 SET_RESOURCE_end = 0x00038000, 52 SET_SAMPLER_offset = 0x0003c000, 53 SET_SAMPLER_end = 0x0003c600, 54 SET_CTL_CONST_offset = 0x0003cff0, 55 SET_CTL_CONST_end = 0x0003ff0c, 56 SET_LOOP_CONST_offset = 0x0003a200, 57 SET_LOOP_CONST_end = 0x0003a500, 58 SET_BOOL_CONST_offset = 0x0003a500, 59 SET_BOOL_CONST_end = 0x0003a518, 60}; 61 62/* Packet3 commands */ 63enum { 64 IT_NOP = 0x10, 65 IT_INDIRECT_BUFFER_END = 0x17, 66 IT_SET_PREDICATION = 0x20, 67 IT_COND_EXEC = 0x22, 68 IT_PRED_EXEC = 0x23, 69 IT_DRAW_INDEX_2 = 0x27, 70 IT_CONTEXT_CONTROL = 0x28, 71 IT_DRAW_INDEX_OFFSET = 0x29, 72 IT_INDEX_TYPE = 0x2A, 73 IT_DRAW_INDEX = 0x2B, 74 IT_DRAW_INDEX_AUTO = 0x2D, 75 IT_DRAW_INDEX_IMMD = 0x2E, 76 IT_NUM_INSTANCES = 0x2F, 77 IT_INDIRECT_BUFFER = 0x32, 78 IT_STRMOUT_BUFFER_UPDATE = 0x34, 79 IT_MEM_SEMAPHORE = 0x39, 80 IT_MPEG_INDEX = 0x3A, 81 IT_WAIT_REG_MEM = 0x3C, 82 IT_MEM_WRITE = 0x3D, 83 IT_SURFACE_SYNC = 0x43, 84 IT_ME_INITIALIZE = 0x44, 85 IT_COND_WRITE = 0x45, 86 IT_EVENT_WRITE = 0x46, 87 IT_EVENT_WRITE_EOP = 0x47, 88 IT_EVENT_WRITE_EOS = 0x48, 89 IT_SET_CONFIG_REG = 0x68, 90 IT_SET_CONTEXT_REG = 0x69, 91 IT_SET_ALU_CONST = 0x6A, 92 IT_SET_BOOL_CONST = 0x6B, 93 IT_SET_LOOP_CONST = 0x6C, 94 IT_SET_RESOURCE = 0x6D, 95 IT_SET_SAMPLER = 0x6E, 96 IT_SET_CTL_CONST = 0x6F, 97}; 98 99/* IT_WAIT_REG_MEM operation encoding */ 100 101#define IT_WAIT_ALWAYS (0 << 0) 102#define IT_WAIT_LT (1 << 0) 103#define IT_WAIT_LE (2 << 0) 104#define IT_WAIT_EQ (3 << 0) 105#define IT_WAIT_NE (4 << 0) 106#define IT_WAIT_GE (5 << 0) 107#define IT_WAIT_GT (6 << 0) 108#define IT_WAIT_REG (0 << 4) 109#define IT_WAIT_MEM (1 << 4) 110 111#define IT_WAIT_ADDR(x) ((x) >> 2) 112 113enum { 114 115 SQ_LDS_ALLOC_PS = 0x288ec, 116 SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838, 117 SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8d8c, 118 119 WAIT_UNTIL = 0x8040, 120 WAIT_CP_DMA_IDLE_bit = 1 << 8, 121 WAIT_CMDFIFO_bit = 1 << 10, 122 WAIT_3D_IDLE_bit = 1 << 15, 123 WAIT_3D_IDLECLEAN_bit = 1 << 17, 124 WAIT_EXTERN_SIG_bit = 1 << 19, 125 CMDFIFO_ENTRIES_mask = 0xf << 20, 126 CMDFIFO_ENTRIES_shift = 20, 127 128 CP_COHER_CNTL = 0x85f0, 129 DEST_BASE_0_ENA_bit = 1 << 0, 130 DEST_BASE_1_ENA_bit = 1 << 1, 131 SO0_DEST_BASE_ENA_bit = 1 << 2, 132 SO1_DEST_BASE_ENA_bit = 1 << 3, 133 SO2_DEST_BASE_ENA_bit = 1 << 4, 134 SO3_DEST_BASE_ENA_bit = 1 << 5, 135 CB0_DEST_BASE_ENA_bit = 1 << 6, 136 CB1_DEST_BASE_ENA_bit = 1 << 7, 137 CB2_DEST_BASE_ENA_bit = 1 << 8, 138 CB3_DEST_BASE_ENA_bit = 1 << 9, 139 CB4_DEST_BASE_ENA_bit = 1 << 10, 140 CB5_DEST_BASE_ENA_bit = 1 << 11, 141 CB6_DEST_BASE_ENA_bit = 1 << 12, 142 CB7_DEST_BASE_ENA_bit = 1 << 13, 143 DB_DEST_BASE_ENA_bit = 1 << 14, 144 CB8_DEST_BASE_ENA_bit = 1 << 15, 145 CB9_DEST_BASE_ENA_bit = 1 << 16, 146 CB10_DEST_BASE_ENA_bit = 1 << 17, 147 CB11_DEST_BASE_ENA_bit = 1 << 18, 148 FULL_CACHE_ENA_bit = 1 << 20, 149 TC_ACTION_ENA_bit = 1 << 23, 150 VC_ACTION_ENA_bit = 1 << 24, 151 CB_ACTION_ENA_bit = 1 << 25, 152 DB_ACTION_ENA_bit = 1 << 26, 153 SH_ACTION_ENA_bit = 1 << 27, 154 SX_ACTION_ENA_bit = 1 << 28, 155 CP_COHER_SIZE = 0x85f4, 156 CP_COHER_BASE = 0x85f8, 157 CP_COHER_STATUS = 0x85fc, 158 MATCHING_GFX_CNTX_mask = 0xff << 0, 159 MATCHING_GFX_CNTX_shift = 0, 160 STATUS_bit = 1 << 31, 161 162// SQ_VTX_CONSTANT_WORD2_0 = 0x00030008, 163// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 164 FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, 165 FMT_16=5, FMT_16_FLOAT, FMT_8_8, 166 FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, 167 FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, 168 FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, 169 FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, 170 FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, 171 FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, 172 FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, 173 FMT_1 = 37, FMT_GB_GR=39, 174 FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, 175 FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, 176 FMT_32_32_32_FLOAT=48, 177 178// High level register file lengths 179 SQ_FETCH_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, 180 SQ_FETCH_RESOURCE_ps_num = 176, 181 SQ_FETCH_RESOURCE_vs_num = 160, 182 SQ_FETCH_RESOURCE_gs_num = 160, 183 SQ_FETCH_RESOURCE_hs_num = 160, 184 SQ_FETCH_RESOURCE_ls_num = 160, 185 SQ_FETCH_RESOURCE_cs_num = 176, 186 SQ_FETCH_RESOURCE_fs_num = 32, 187 SQ_FETCH_RESOURCE_all_num = 1024, 188 SQ_FETCH_RESOURCE_offset = 32, 189 SQ_FETCH_RESOURCE_ps = 0, // 0...175 190 SQ_FETCH_RESOURCE_vs = SQ_FETCH_RESOURCE_ps + SQ_FETCH_RESOURCE_ps_num, // 176...335 191 SQ_FETCH_RESOURCE_gs = SQ_FETCH_RESOURCE_vs + SQ_FETCH_RESOURCE_vs_num, // 336...495 192 SQ_FETCH_RESOURCE_hs = SQ_FETCH_RESOURCE_gs + SQ_FETCH_RESOURCE_gs_num, // 496...655 193 SQ_FETCH_RESOURCE_ls = SQ_FETCH_RESOURCE_hs + SQ_FETCH_RESOURCE_hs_num, // 656...815 194 SQ_FETCH_RESOURCE_cs = SQ_FETCH_RESOURCE_ls + SQ_FETCH_RESOURCE_ls_num, // 816...991 195 SQ_FETCH_RESOURCE_fs = SQ_FETCH_RESOURCE_cs + SQ_FETCH_RESOURCE_cs_num, // 992...1023 196 197 SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, 198 SQ_TEX_SAMPLER_WORD_ps_num = 18, 199 SQ_TEX_SAMPLER_WORD_vs_num = 18, 200 SQ_TEX_SAMPLER_WORD_gs_num = 18, 201 SQ_TEX_SAMPLER_WORD_hs_num = 18, 202 SQ_TEX_SAMPLER_WORD_ls_num = 18, 203 SQ_TEX_SAMPLER_WORD_cs_num = 18, 204 SQ_TEX_SAMPLER_WORD_all_num = 108, 205 SQ_TEX_SAMPLER_WORD_offset = 12, 206 SQ_TEX_SAMPLER_WORD_ps = 0, // 0...17 207 SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, // 18...35 208 SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, // 36...53 209 SQ_TEX_SAMPLER_WORD_hs = SQ_TEX_SAMPLER_WORD_gs + SQ_TEX_SAMPLER_WORD_gs_num, // 54...71 210 SQ_TEX_SAMPLER_WORD_ls = SQ_TEX_SAMPLER_WORD_hs + SQ_TEX_SAMPLER_WORD_hs_num, // 72...89 211 SQ_TEX_SAMPLER_WORD_cs = SQ_TEX_SAMPLER_WORD_ls + SQ_TEX_SAMPLER_WORD_ls_num, // 90...107 212 213 SQ_LOOP_CONST = SQ_LOOP_CONST_0, 214 SQ_LOOP_CONST_ps_num = 32, 215 SQ_LOOP_CONST_vs_num = 32, 216 SQ_LOOP_CONST_gs_num = 32, 217 SQ_LOOP_CONST_hs_num = 32, 218 SQ_LOOP_CONST_ls_num = 32, 219 SQ_LOOP_CONST_cs_num = 32, 220 SQ_LOOP_CONST_all_num = 192, 221 SQ_LOOP_CONST_offset = 4, 222 SQ_LOOP_CONST_ps = 0, // 0...31 223 SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, // 32...63 224 SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, // 64...95 225 SQ_LOOP_CONST_hs = SQ_LOOP_CONST_gs + SQ_LOOP_CONST_gs_num, // 96...127 226 SQ_LOOP_CONST_ls = SQ_LOOP_CONST_hs + SQ_LOOP_CONST_hs_num, // 128...159 227 SQ_LOOP_CONST_cs = SQ_LOOP_CONST_ls + SQ_LOOP_CONST_ls_num, // 160...191 228 229 SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits each */ 230 SQ_BOOL_CONST_ps_num = 1, 231 SQ_BOOL_CONST_vs_num = 1, 232 SQ_BOOL_CONST_gs_num = 1, 233 SQ_BOOL_CONST_hs_num = 1, 234 SQ_BOOL_CONST_ls_num = 1, 235 SQ_BOOL_CONST_cs_num = 1, 236 SQ_BOOL_CONST_all_num = 6, 237 SQ_BOOL_CONST_offset = 4, 238 SQ_BOOL_CONST_ps = 0, 239 SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, 240 SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, 241 SQ_BOOL_CONST_hs = SQ_BOOL_CONST_gs + SQ_BOOL_CONST_gs_num, 242 SQ_BOOL_CONST_ls = SQ_BOOL_CONST_hs + SQ_BOOL_CONST_hs_num, 243 SQ_BOOL_CONST_cs = SQ_BOOL_CONST_ls + SQ_BOOL_CONST_ls_num, 244 245}; 246 247#endif 248