1/* 2 * RadeonHD R6xx, R7xx Register documentation 3 * 4 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. 5 * Copyright (C) 2008-2009 Matthias Hopf 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included 15 * in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef _R600_REG_R6xx_H_ 26#define _R600_REG_R6xx_H_ 27 28/* 29 * Registers for R6xx chips that are not documented yet 30 */ 31 32enum { 33 34 MM_INDEX = 0x0000, 35 MM_DATA = 0x0004, 36 37 SRBM_STATUS = 0x0e50, 38 RLC_RQ_PENDING_bit = 1 << 3, 39 RCU_RQ_PENDING_bit = 1 << 4, 40 GRBM_RQ_PENDING_bit = 1 << 5, 41 HI_RQ_PENDING_bit = 1 << 6, 42 IO_EXTERN_SIGNAL_bit = 1 << 7, 43 VMC_BUSY_bit = 1 << 8, 44 MCB_BUSY_bit = 1 << 9, 45 MCDZ_BUSY_bit = 1 << 10, 46 MCDY_BUSY_bit = 1 << 11, 47 MCDX_BUSY_bit = 1 << 12, 48 MCDW_BUSY_bit = 1 << 13, 49 SEM_BUSY_bit = 1 << 14, 50 SRBM_STATUS__RLC_BUSY_bit = 1 << 15, 51 PDMA_BUSY_bit = 1 << 16, 52 IH_BUSY_bit = 1 << 17, 53 CSC_BUSY_bit = 1 << 20, 54 CMC7_BUSY_bit = 1 << 21, 55 CMC6_BUSY_bit = 1 << 22, 56 CMC5_BUSY_bit = 1 << 23, 57 CMC4_BUSY_bit = 1 << 24, 58 CMC3_BUSY_bit = 1 << 25, 59 CMC2_BUSY_bit = 1 << 26, 60 CMC1_BUSY_bit = 1 << 27, 61 CMC0_BUSY_bit = 1 << 28, 62 BIF_BUSY_bit = 1 << 29, 63 IDCT_BUSY_bit = 1 << 30, 64 65 SRBM_READ_ERROR = 0x0e98, 66 READ_ADDRESS_mask = 0xffff << 2, 67 READ_ADDRESS_shift = 2, 68 READ_REQUESTER_HI_bit = 1 << 24, 69 READ_REQUESTER_GRBM_bit = 1 << 25, 70 READ_REQUESTER_RCU_bit = 1 << 26, 71 READ_REQUESTER_RLC_bit = 1 << 27, 72 READ_ERROR_bit = 1 << 31, 73 74 SRBM_INT_STATUS = 0x0ea4, 75 RDERR_INT_STAT_bit = 1 << 0, 76 GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, 77 SRBM_INT_ACK = 0x0ea8, 78 RDERR_INT_ACK_bit = 1 << 0, 79 GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, 80 81 R6XX_MC_VM_FB_LOCATION = 0x2180, 82 83 VENDOR_DEVICE_ID = 0x4000, 84 85 HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480, 86 87 D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, 88 D1GRPH_PITCH = 0x6120, 89 D1GRPH_Y_END = 0x6138, 90 91 GRBM_STATUS = 0x8010, 92 CMDFIFO_AVAIL_mask = 0x1f << 0, 93 CMDFIFO_AVAIL_shift = 0, 94 SRBM_RQ_PENDING_bit = 1 << 5, 95 CP_RQ_PENDING_bit = 1 << 6, 96 CF_RQ_PENDING_bit = 1 << 7, 97 PF_RQ_PENDING_bit = 1 << 8, 98 GRBM_EE_BUSY_bit = 1 << 10, 99 GRBM_STATUS__VC_BUSY_bit = 1 << 11, 100 DB03_CLEAN_bit = 1 << 12, 101 CB03_CLEAN_bit = 1 << 13, 102 VGT_BUSY_NO_DMA_bit = 1 << 16, 103 GRBM_STATUS__VGT_BUSY_bit = 1 << 17, 104 TA03_BUSY_bit = 1 << 18, 105 GRBM_STATUS__TC_BUSY_bit = 1 << 19, 106 SX_BUSY_bit = 1 << 20, 107 SH_BUSY_bit = 1 << 21, 108 SPI03_BUSY_bit = 1 << 22, 109 SMX_BUSY_bit = 1 << 23, 110 SC_BUSY_bit = 1 << 24, 111 PA_BUSY_bit = 1 << 25, 112 DB03_BUSY_bit = 1 << 26, 113 CR_BUSY_bit = 1 << 27, 114 CP_COHERENCY_BUSY_bit = 1 << 28, 115 GRBM_STATUS__CP_BUSY_bit = 1 << 29, 116 CB03_BUSY_bit = 1 << 30, 117 GUI_ACTIVE_bit = 1 << 31, 118 GRBM_STATUS2 = 0x8014, 119 CR_CLEAN_bit = 1 << 0, 120 SMX_CLEAN_bit = 1 << 1, 121 SPI0_BUSY_bit = 1 << 8, 122 SPI1_BUSY_bit = 1 << 9, 123 SPI2_BUSY_bit = 1 << 10, 124 SPI3_BUSY_bit = 1 << 11, 125 TA0_BUSY_bit = 1 << 12, 126 TA1_BUSY_bit = 1 << 13, 127 TA2_BUSY_bit = 1 << 14, 128 TA3_BUSY_bit = 1 << 15, 129 DB0_BUSY_bit = 1 << 16, 130 DB1_BUSY_bit = 1 << 17, 131 DB2_BUSY_bit = 1 << 18, 132 DB3_BUSY_bit = 1 << 19, 133 CB0_BUSY_bit = 1 << 20, 134 CB1_BUSY_bit = 1 << 21, 135 CB2_BUSY_bit = 1 << 22, 136 CB3_BUSY_bit = 1 << 23, 137 GRBM_SOFT_RESET = 0x8020, 138 SOFT_RESET_CP_bit = 1 << 0, 139 SOFT_RESET_CB_bit = 1 << 1, 140 SOFT_RESET_CR_bit = 1 << 2, 141 SOFT_RESET_DB_bit = 1 << 3, 142 SOFT_RESET_PA_bit = 1 << 5, 143 SOFT_RESET_SC_bit = 1 << 6, 144 SOFT_RESET_SMX_bit = 1 << 7, 145 SOFT_RESET_SPI_bit = 1 << 8, 146 SOFT_RESET_SH_bit = 1 << 9, 147 SOFT_RESET_SX_bit = 1 << 10, 148 SOFT_RESET_TC_bit = 1 << 11, 149 SOFT_RESET_TA_bit = 1 << 12, 150 SOFT_RESET_VC_bit = 1 << 13, 151 SOFT_RESET_VGT_bit = 1 << 14, 152 SOFT_RESET_GRBM_GCA_bit = 1 << 15, 153 154 WAIT_UNTIL = 0x8040, 155 WAIT_CP_DMA_IDLE_bit = 1 << 8, 156 WAIT_CMDFIFO_bit = 1 << 10, 157 WAIT_2D_IDLE_bit = 1 << 14, 158 WAIT_3D_IDLE_bit = 1 << 15, 159 WAIT_2D_IDLECLEAN_bit = 1 << 16, 160 WAIT_3D_IDLECLEAN_bit = 1 << 17, 161 WAIT_EXTERN_SIG_bit = 1 << 19, 162 CMDFIFO_ENTRIES_mask = 0x1f << 20, 163 CMDFIFO_ENTRIES_shift = 20, 164 165 GRBM_READ_ERROR = 0x8058, 166/* READ_ADDRESS_mask = 0xffff << 2, */ 167/* READ_ADDRESS_shift = 2, */ 168 READ_REQUESTER_SRBM_bit = 1 << 28, 169 READ_REQUESTER_CP_bit = 1 << 29, 170 READ_REQUESTER_WU_POLL_bit = 1 << 30, 171/* READ_ERROR_bit = 1 << 31, */ 172 173 SCRATCH_REG0 = 0x8500, 174 SCRATCH_REG1 = 0x8504, 175 SCRATCH_REG2 = 0x8508, 176 SCRATCH_REG3 = 0x850c, 177 SCRATCH_REG4 = 0x8510, 178 SCRATCH_REG5 = 0x8514, 179 SCRATCH_REG6 = 0x8518, 180 SCRATCH_REG7 = 0x851c, 181 SCRATCH_UMSK = 0x8540, 182 SCRATCH_ADDR = 0x8544, 183 184 CP_COHER_CNTL = 0x85f0, 185 DEST_BASE_0_ENA_bit = 1 << 0, 186 DEST_BASE_1_ENA_bit = 1 << 1, 187 SO0_DEST_BASE_ENA_bit = 1 << 2, 188 SO1_DEST_BASE_ENA_bit = 1 << 3, 189 SO2_DEST_BASE_ENA_bit = 1 << 4, 190 SO3_DEST_BASE_ENA_bit = 1 << 5, 191 CB0_DEST_BASE_ENA_bit = 1 << 6, 192 CB1_DEST_BASE_ENA_bit = 1 << 7, 193 CB2_DEST_BASE_ENA_bit = 1 << 8, 194 CB3_DEST_BASE_ENA_bit = 1 << 9, 195 CB4_DEST_BASE_ENA_bit = 1 << 10, 196 CB5_DEST_BASE_ENA_bit = 1 << 11, 197 CB6_DEST_BASE_ENA_bit = 1 << 12, 198 CB7_DEST_BASE_ENA_bit = 1 << 13, 199 DB_DEST_BASE_ENA_bit = 1 << 14, 200 CR_DEST_BASE_ENA_bit = 1 << 15, 201 TC_ACTION_ENA_bit = 1 << 23, 202 VC_ACTION_ENA_bit = 1 << 24, 203 CB_ACTION_ENA_bit = 1 << 25, 204 DB_ACTION_ENA_bit = 1 << 26, 205 SH_ACTION_ENA_bit = 1 << 27, 206 SMX_ACTION_ENA_bit = 1 << 28, 207 CR0_ACTION_ENA_bit = 1 << 29, 208 CR1_ACTION_ENA_bit = 1 << 30, 209 CR2_ACTION_ENA_bit = 1 << 31, 210 CP_COHER_SIZE = 0x85f4, 211 CP_COHER_BASE = 0x85f8, 212 CP_COHER_STATUS = 0x85fc, 213 MATCHING_GFX_CNTX_mask = 0xff << 0, 214 MATCHING_GFX_CNTX_shift = 0, 215 MATCHING_CR_CNTX_mask = 0xffff << 8, 216 MATCHING_CR_CNTX_shift = 8, 217 STATUS_bit = 1 << 31, 218 219 CP_STALLED_STAT1 = 0x8674, 220 RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, 221 RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, 222 RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, 223 RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, 224 RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, 225 RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, 226 RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, 227 RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, 228 RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, 229 RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, 230 MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, 231 MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, 232 MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, 233 RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, 234 RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, 235 RCIU_STALLED_ON_ME_READ_bit = 1 << 26, 236 RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, 237 RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, 238 CP_STALLED_STAT2 = 0x8678, 239 PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, 240 PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, 241 PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, 242 PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, 243 MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, 244 ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, 245 ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, 246 CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, 247 GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, 248 ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, 249 ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, 250 ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, 251 ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, 252 RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, 253 RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, 254 EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, 255 EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, 256 EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, 257 EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, 258 SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, 259 SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, 260 PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, 261 SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, 262 SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, 263 CP_BUSY_STAT = 0x867c, 264 REG_BUS_FIFO_BUSY_bit = 1 << 0, 265 RING_FETCHING_DATA_bit = 1 << 1, 266 INDR1_FETCHING_DATA_bit = 1 << 2, 267 INDR2_FETCHING_DATA_bit = 1 << 3, 268 STATE_FETCHING_DATA_bit = 1 << 4, 269 PRED_FETCHING_DATA_bit = 1 << 5, 270 COHER_CNTR_NEQ_ZERO_bit = 1 << 6, 271 PFP_PARSING_PACKETS_bit = 1 << 7, 272 ME_PARSING_PACKETS_bit = 1 << 8, 273 RCIU_PFP_BUSY_bit = 1 << 9, 274 RCIU_ME_BUSY_bit = 1 << 10, 275 OUTSTANDING_READ_TAGS_bit = 1 << 11, 276 SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, 277 SEM_FAILED_AND_HOLDING_bit = 1 << 13, 278 SEM_POLLING_FOR_PASS_bit = 1 << 14, 279 _3D_BUSY_bit = 1 << 15, 280 _2D_BUSY_bit = 1 << 16, 281 CP_STAT = 0x8680, 282 CSF_RING_BUSY_bit = 1 << 0, 283 CSF_WPTR_POLL_BUSY_bit = 1 << 1, 284 CSF_INDIRECT1_BUSY_bit = 1 << 2, 285 CSF_INDIRECT2_BUSY_bit = 1 << 3, 286 CSF_STATE_BUSY_bit = 1 << 4, 287 CSF_PREDICATE_BUSY_bit = 1 << 5, 288 CSF_BUSY_bit = 1 << 6, 289 MIU_RDREQ_BUSY_bit = 1 << 7, 290 MIU_WRREQ_BUSY_bit = 1 << 8, 291 ROQ_RING_BUSY_bit = 1 << 9, 292 ROQ_INDIRECT1_BUSY_bit = 1 << 10, 293 ROQ_INDIRECT2_BUSY_bit = 1 << 11, 294 ROQ_STATE_BUSY_bit = 1 << 12, 295 ROQ_PREDICATE_BUSY_bit = 1 << 13, 296 ROQ_ALIGN_BUSY_bit = 1 << 14, 297 PFP_BUSY_bit = 1 << 15, 298 MEQ_BUSY_bit = 1 << 16, 299 ME_BUSY_bit = 1 << 17, 300 QUERY_BUSY_bit = 1 << 18, 301 SEMAPHORE_BUSY_bit = 1 << 19, 302 INTERRUPT_BUSY_bit = 1 << 20, 303 SURFACE_SYNC_BUSY_bit = 1 << 21, 304 DMA_BUSY_bit = 1 << 22, 305 RCIU_BUSY_bit = 1 << 23, 306 CP_STAT__CP_BUSY_bit = 1 << 31, 307 308 CP_ME_CNTL = 0x86d8, 309 ME_STATMUX_mask = 0xff << 0, 310 ME_STATMUX_shift = 0, 311 ME_HALT_bit = 1 << 28, 312 CP_ME_STATUS = 0x86dc, 313 314 CP_RB_RPTR = 0x8700, 315 RB_RPTR_mask = 0xfffff << 0, 316 RB_RPTR_shift = 0, 317 CP_RB_WPTR_DELAY = 0x8704, 318 PRE_WRITE_TIMER_mask = 0xfffffff << 0, 319 PRE_WRITE_TIMER_shift = 0, 320 PRE_WRITE_LIMIT_mask = 0x0f << 28, 321 PRE_WRITE_LIMIT_shift = 28, 322 323 CP_ROQ_RB_STAT = 0x8780, 324 ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, 325 ROQ_RPTR_PRIMARY_shift = 0, 326 ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, 327 ROQ_WPTR_PRIMARY_shift = 16, 328 CP_ROQ_IB1_STAT = 0x8784, 329 ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, 330 ROQ_RPTR_INDIRECT1_shift = 0, 331 ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, 332 ROQ_WPTR_INDIRECT1_shift = 16, 333 CP_ROQ_IB2_STAT = 0x8788, 334 ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, 335 ROQ_RPTR_INDIRECT2_shift = 0, 336 ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, 337 ROQ_WPTR_INDIRECT2_shift = 16, 338 339 CP_MEQ_STAT = 0x8794, 340 MEQ_RPTR_mask = 0x3ff << 0, 341 MEQ_RPTR_shift = 0, 342 MEQ_WPTR_mask = 0x3ff << 16, 343 MEQ_WPTR_shift = 16, 344 345 CC_GC_SHADER_PIPE_CONFIG = 0x8950, 346 INACTIVE_QD_PIPES_mask = 0xff << 8, 347 INACTIVE_QD_PIPES_shift = 8, 348 R6XX_MAX_QD_PIPES = 8, 349 INACTIVE_SIMDS_mask = 0xff << 16, 350 INACTIVE_SIMDS_shift = 16, 351 R6XX_MAX_SIMDS = 8, 352 GC_USER_SHADER_PIPE_CONFIG = 0x8954, 353 354 VC_ENHANCE = 0x9714, 355 DB_DEBUG = 0x9830, 356 PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, 357 358 DB_WATERMARKS = 0x00009838, 359 DEPTH_FREE_mask = 0x1f << 0, 360 DEPTH_FREE_shift = 0, 361 DEPTH_FLUSH_mask = 0x3f << 5, 362 DEPTH_FLUSH_shift = 5, 363 FORCE_SUMMARIZE_mask = 0x0f << 11, 364 FORCE_SUMMARIZE_shift = 11, 365 DEPTH_PENDING_FREE_mask = 0x1f << 15, 366 DEPTH_PENDING_FREE_shift = 15, 367 DEPTH_CACHELINE_FREE_mask = 0x1f << 20, 368 DEPTH_CACHELINE_FREE_shift = 20, 369 EARLY_Z_PANIC_DISABLE_bit = 1 << 25, 370 LATE_Z_PANIC_DISABLE_bit = 1 << 26, 371 RE_Z_PANIC_DISABLE_bit = 1 << 27, 372 DB_EXTRA_DEBUG_mask = 0x0f << 28, 373 DB_EXTRA_DEBUG_shift = 28, 374 375 CP_RB_BASE = 0xc100, 376 CP_RB_CNTL = 0xc104, 377 RB_BUFSZ_mask = 0x3f << 0, 378 CP_RB_WPTR = 0xc114, 379 RB_WPTR_mask = 0xfffff << 0, 380 RB_WPTR_shift = 0, 381 CP_RB_RPTR_WR = 0xc108, 382 RB_RPTR_WR_mask = 0xfffff << 0, 383 RB_RPTR_WR_shift = 0, 384 385 CP_INT_STATUS = 0xc128, 386 DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, 387 ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, 388 SEM_SIGNAL_INT_STAT_bit = 1 << 18, 389 CNTX_BUSY_INT_STAT_bit = 1 << 19, 390 CNTX_EMPTY_INT_STAT_bit = 1 << 20, 391 WAITMEM_SEM_INT_STAT_bit = 1 << 21, 392 PRIV_INSTR_INT_STAT_bit = 1 << 22, 393 PRIV_REG_INT_STAT_bit = 1 << 23, 394 OPCODE_ERROR_INT_STAT_bit = 1 << 24, 395 SCRATCH_INT_STAT_bit = 1 << 25, 396 TIME_STAMP_INT_STAT_bit = 1 << 26, 397 RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, 398 DMA_INT_STAT_bit = 1 << 28, 399 IB2_INT_STAT_bit = 1 << 29, 400 IB1_INT_STAT_bit = 1 << 30, 401 RB_INT_STAT_bit = 1 << 31, 402 403// SX_ALPHA_TEST_CONTROL = 0x00028410, 404 ALPHA_FUNC__REF_NEVER = 0, 405 ALPHA_FUNC__REF_ALWAYS = 7, 406// DB_SHADER_CONTROL = 0x0002880c, 407 Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, 408// PA_SU_SC_MODE_CNTL = 0x00028814, 409// POLY_MODE_mask = 0x03 << 3, 410 POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, 411// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, 412 POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, 413 PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, 414 DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ 415// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, 416 DB_ALPHA_TO_MASK = 0x00028d44, 417 ALPHA_TO_MASK_ENABLE = 1 << 0, 418 ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, 419 ALPHA_TO_MASK_OFFSET0_shift = 8, 420 ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, 421 ALPHA_TO_MASK_OFFSET1_shift = 10, 422 ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, 423 ALPHA_TO_MASK_OFFSET2_shift = 12, 424 ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, 425 ALPHA_TO_MASK_OFFSET3_shift = 14, 426 427// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, 428// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 429 FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, 430 FMT_16=5, FMT_16_FLOAT, FMT_8_8, 431 FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, 432 FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, 433 FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, 434 FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, 435 FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, 436 FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, 437 FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, 438 FMT_1 = 37, FMT_GB_GR=39, 439 FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, 440 FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, 441 FMT_32_32_32_FLOAT=48, 442 443// High level register file lengths 444 SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ 445 SQ_ALU_CONSTANT_ps_num = 256, 446 SQ_ALU_CONSTANT_vs_num = 256, 447 SQ_ALU_CONSTANT_all_num = 512, 448 SQ_ALU_CONSTANT_offset = 16, 449 SQ_ALU_CONSTANT_ps = 0, 450 SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, 451 SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ 452 SQ_TEX_RESOURCE_ps_num = 160, 453 SQ_TEX_RESOURCE_vs_num = 160, 454 SQ_TEX_RESOURCE_fs_num = 16, 455 SQ_TEX_RESOURCE_gs_num = 160, 456 SQ_TEX_RESOURCE_all_num = 496, 457 SQ_TEX_RESOURCE_offset = 28, 458 SQ_TEX_RESOURCE_ps = 0, 459 SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, 460 SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, 461 SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, 462 SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ 463 SQ_VTX_RESOURCE_ps_num = 160, 464 SQ_VTX_RESOURCE_vs_num = 160, 465 SQ_VTX_RESOURCE_fs_num = 16, 466 SQ_VTX_RESOURCE_gs_num = 160, 467 SQ_VTX_RESOURCE_all_num = 496, 468 SQ_VTX_RESOURCE_offset = 28, 469 SQ_VTX_RESOURCE_ps = 0, 470 SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, 471 SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, 472 SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, 473 SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ 474 SQ_TEX_SAMPLER_WORD_ps_num = 18, 475 SQ_TEX_SAMPLER_WORD_vs_num = 18, 476 SQ_TEX_SAMPLER_WORD_gs_num = 18, 477 SQ_TEX_SAMPLER_WORD_all_num = 54, 478 SQ_TEX_SAMPLER_WORD_offset = 12, 479 SQ_TEX_SAMPLER_WORD_ps = 0, 480 SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, 481 SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, 482 SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ 483 SQ_LOOP_CONST_ps_num = 32, 484 SQ_LOOP_CONST_vs_num = 32, 485 SQ_LOOP_CONST_gs_num = 32, 486 SQ_LOOP_CONST_all_num = 96, 487 SQ_LOOP_CONST_offset = 4, 488 SQ_LOOP_CONST_ps = 0, 489 SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, 490 SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, 491 SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ 492 SQ_BOOL_CONST_ps_num = 1, 493 SQ_BOOL_CONST_vs_num = 1, 494 SQ_BOOL_CONST_gs_num = 1, 495 SQ_BOOL_CONST_all_num = 3, 496 SQ_BOOL_CONST_offset = 4, 497 SQ_BOOL_CONST_ps = 0, 498 SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, 499 SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, 500}; 501 502 503#endif 504