r600_state.h revision 2f39173d 
1#ifndef __R600_STATE_H__
2#define __R600_STATE_H__
3
4
5#include "xf86drm.h"
6
7typedef int bool_t;
8
9#define CLEAR(x) memset (&x, 0, sizeof(x))
10
11/* Sequencer / thread handling */
12typedef struct {
13    int ps_prio;
14    int vs_prio;
15    int gs_prio;
16    int es_prio;
17    int num_ps_gprs;
18    int num_vs_gprs;
19    int num_gs_gprs;
20    int num_es_gprs;
21    int num_temp_gprs;
22    int num_ps_threads;
23    int num_vs_threads;
24    int num_gs_threads;
25    int num_es_threads;
26    int num_ps_stack_entries;
27    int num_vs_stack_entries;
28    int num_gs_stack_entries;
29    int num_es_stack_entries;
30} sq_config_t;
31
32/* Color buffer / render target */
33typedef struct {
34    int id;
35    int w;
36    int h;
37    uint64_t base;
38    int format;
39    int endian;
40    int array_mode;						// tiling
41    int number_type;
42    int read_size;
43    int comp_swap;
44    int tile_mode;
45    int blend_clamp;
46    int clear_color;
47    int blend_bypass;
48    int blend_float32;
49    int simple_float;
50    int round_mode;
51    int tile_compact;
52    int source_format;
53    struct radeon_bo *bo;
54} cb_config_t;
55
56/* Depth buffer */
57typedef struct {
58    int w;
59    int h;
60    uint64_t base;
61    int format;
62    int read_size;
63    int array_mode;						// tiling
64    int tile_surface_en;
65    int tile_compact;
66    int zrange_precision;
67    struct radeon_bo *bo;
68} db_config_t;
69
70/* Shader */
71typedef struct {
72    uint64_t shader_addr;
73    int num_gprs;
74    int stack_size;
75    int dx10_clamp;
76    int prime_cache_pgm_en;
77    int prime_cache_on_draw;
78    int fetch_cache_lines;
79    int prime_cache_en;
80    int prime_cache_on_const;
81    int clamp_consts;
82    int export_mode;
83    int uncached_first_inst;
84    struct radeon_bo *bo;
85} shader_config_t;
86
87/* Vertex buffer / vtx resource */
88typedef struct {
89    int id;
90    uint64_t vb_addr;
91    uint32_t vtx_num_entries;
92    uint32_t vtx_size_dw;
93    int clamp_x;
94    int format;
95    int num_format_all;
96    int format_comp_all;
97    int srf_mode_all;
98    int endian;
99    int mem_req_size;
100    struct radeon_bo *bo;
101} vtx_resource_t;
102
103/* Texture resource */
104typedef struct {
105    int id;
106    int w;
107    int h;
108    int pitch;
109    int depth;
110    int dim;
111    int tile_mode;
112    int tile_type;
113    int format;
114    uint64_t base;
115    uint64_t mip_base;
116    int format_comp_x;
117    int format_comp_y;
118    int format_comp_z;
119    int format_comp_w;
120    int num_format_all;
121    int srf_mode_all;
122    int force_degamma;
123    int endian;
124    int request_size;
125    int dst_sel_x;
126    int dst_sel_y;
127    int dst_sel_z;
128    int dst_sel_w;
129    int base_level;
130    int last_level;
131    int base_array;
132    int last_array;
133    int mpeg_clamp;
134    int perf_modulation;
135    int interlaced;
136    struct radeon_bo *bo;
137    struct radeon_bo *mip_bo;
138} tex_resource_t;
139
140/* Texture sampler */
141typedef struct {
142    int				id;
143    /* Clamping */
144    int				clamp_x, clamp_y, clamp_z;
145    int		       		border_color;
146    /* Filtering */
147    int				xy_mag_filter, xy_min_filter;
148    int				z_filter;
149    int				mip_filter;
150    bool_t			high_precision_filter;	/* ? */
151    int				perf_mip;		/* ? 0-7 */
152    int				perf_z;			/* ? 3 */
153    /* LoD selection */
154    int				min_lod, max_lod;	/* 0-0x3ff */
155    int                         lod_bias;		/* 0-0xfff (signed?) */
156    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
157    bool_t			lod_uses_minor_axis;	/* ? */
158    /* Other stuff */
159    bool_t			point_sampling_clamp;	/* ? */
160    bool_t			tex_array_override;	/* ? */
161    bool_t                      mc_coord_truncate;	/* ? */
162    bool_t			force_degamma;		/* ? */
163    bool_t			fetch_4;		/* ? */
164    bool_t			sample_is_pcf;		/* ? */
165    bool_t			type;			/* ? */
166    int				depth_compare;		/* only depth textures? */
167    int				chroma_key;
168} tex_sampler_t;
169
170/* Draw command */
171typedef struct {
172    uint32_t prim_type;
173    uint32_t vgt_draw_initiator;
174    uint32_t index_type;
175    uint32_t num_instances;
176    uint32_t num_indices;
177} draw_config_t;
178
179#if defined(XF86DRM_MODE)
180#define BEGIN_BATCH(n)				\
181do {					\
182    if (info->cs)			\
183	radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
184} while(0)
185#define END_BATCH()				\
186do {					\
187    if (info->cs)			\
188	radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
189} while(0)
190#define RELOC_BATCH(bo, rd, wd)					\
191do {							\
192    if (info->cs) {							\
193	int _ret;							\
194	_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
195	if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
196    }									\
197} while(0)
198#define E32(ib, dword)                                                  \
199do {                                                                    \
200    if (info->cs)							\
201	radeon_cs_write_dword(info->cs, (dword));			\
202    else {								\
203	uint32_t *ib_head = (pointer)(char*)(ib)->address;		\
204	ib_head[(ib)->used >> 2] = (dword);				\
205	(ib)->used += 4;						\
206    }									\
207} while (0)
208#else
209#define BEGIN_BATCH(n) do {(void)info;} while(0)
210#define END_BATCH() do {} while(0)
211#define RELOC_BATCH(bo, wd, rd) do {} while(0)
212#define E32(ib, dword)                                                  \
213do {                                                                    \
214    uint32_t *ib_head = (pointer)(char*)(ib)->address;			\
215    ib_head[(ib)->used >> 2] = (dword);					\
216    (ib)->used += 4;							\
217} while (0)
218#endif
219
220#define EFLOAT(ib, val)							\
221do {								        \
222    union { float f; uint32_t d; } a;                                   \
223    a.f = (val);								\
224    E32((ib), a.d);							\
225} while (0)
226
227#define PACK3(ib, cmd, num)	       					\
228do {                                                                    \
229    E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
230} while (0)
231
232/* write num registers, start at reg */
233/* If register falls in a special area, special commands are issued */
234#define PACK0(ib, reg, num)                                             \
235do {                                                                    \
236    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
237	PACK3((ib), IT_SET_CONFIG_REG, (num) + 1);			\
238	E32((ib), ((reg) - SET_CONFIG_REG_offset) >> 2);		\
239    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
240	PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1);			\
241	E32((ib), ((reg) - SET_CONTEXT_REG_offset) >> 2);		\
242    } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
243	PACK3((ib), IT_SET_ALU_CONST, (num) + 1);			\
244	E32((ib), ((reg) - SET_ALU_CONST_offset) >> 2);			\
245    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
246	PACK3((ib), IT_SET_RESOURCE, num + 1);				\
247	E32((ib), ((reg) - SET_RESOURCE_offset) >> 2);			\
248    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
249	PACK3((ib), IT_SET_SAMPLER, (num) + 1);				\
250	E32((ib), (reg - SET_SAMPLER_offset) >> 2);			\
251    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
252	PACK3((ib), IT_SET_CTL_CONST, (num) + 1);			\
253	E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2);		\
254    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
255	PACK3((ib), IT_SET_LOOP_CONST, (num) + 1);			\
256	E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2);		\
257    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
258	PACK3((ib), IT_SET_BOOL_CONST, (num) + 1);			\
259	E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2);		\
260    } else {								\
261	E32((ib), CP_PACKET0 ((reg), (num) - 1));			\
262    }									\
263} while (0)
264
265/* write a single register */
266#define EREG(ib, reg, val)                                              \
267do {								        \
268    PACK0((ib), (reg), 1);						\
269    E32((ib), (val));							\
270} while (0)
271
272void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
273void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
274
275uint64_t
276upload (ScrnInfoPtr pScrn, void *shader, int size, int offset);
277void
278wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
279void
280wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
281void
282start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
283void
284set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
285void
286cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr,
287		    struct radeon_bo *bo, uint32_t rdomains, uint32_t wdomain);
288void
289cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
290void
291fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
292void
293vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
294void
295ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
296void
297set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
298void
299set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
300void
301set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res, uint32_t domain);
302void
303set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
304void
305set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
306void
307set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
308void
309set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
310void
311set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
312void
313set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
314void
315set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
316void
317set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
318void
319draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
320void
321draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
322
323Bool
324r600_vb_get(ScrnInfoPtr pScrn);
325void
326r600_vb_discard(ScrnInfoPtr pScrn);
327int
328r600_cp_start(ScrnInfoPtr pScrn);
329void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
330
331Bool
332R600SetAccelState(ScrnInfoPtr pScrn,
333		  struct r600_accel_object *src0,
334		  struct r600_accel_object *src1,
335		  struct r600_accel_object *dst,
336		  uint32_t vs_offset, uint32_t ps_offset,
337		  int rop, Pixel planemask);
338
339extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
340extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
341extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
342extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
343extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
344extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
345
346
347#endif
348