r600_state.h revision 921a55d8 
1#ifndef __R600_STATE_H__
2#define __R600_STATE_H__
3
4
5#include "xf86drm.h"
6
7typedef int bool_t;
8
9#define CLEAR(x) memset (&x, 0, sizeof(x))
10
11/* Sequencer / thread handling */
12typedef struct {
13    int ps_prio;
14    int vs_prio;
15    int gs_prio;
16    int es_prio;
17    int num_ps_gprs;
18    int num_vs_gprs;
19    int num_gs_gprs;
20    int num_es_gprs;
21    int num_temp_gprs;
22    int num_ps_threads;
23    int num_vs_threads;
24    int num_gs_threads;
25    int num_es_threads;
26    int num_ps_stack_entries;
27    int num_vs_stack_entries;
28    int num_gs_stack_entries;
29    int num_es_stack_entries;
30} sq_config_t;
31
32/* Color buffer / render target */
33typedef struct {
34    int id;
35    int w;
36    int h;
37    uint64_t base;
38    int format;
39    int endian;
40    int array_mode;						// tiling
41    int number_type;
42    int read_size;
43    int comp_swap;
44    int tile_mode;
45    int blend_clamp;
46    int clear_color;
47    int blend_bypass;
48    int blend_float32;
49    int simple_float;
50    int round_mode;
51    int tile_compact;
52    int source_format;
53    struct radeon_bo *bo;
54} cb_config_t;
55
56/* Depth buffer */
57typedef struct {
58    int w;
59    int h;
60    uint64_t base;
61    int format;
62    int read_size;
63    int array_mode;						// tiling
64    int tile_surface_en;
65    int tile_compact;
66    int zrange_precision;
67    struct radeon_bo *bo;
68} db_config_t;
69
70/* Shader */
71typedef struct {
72    uint64_t shader_addr;
73    uint32_t shader_size;
74    int num_gprs;
75    int stack_size;
76    int dx10_clamp;
77    int prime_cache_pgm_en;
78    int prime_cache_on_draw;
79    int fetch_cache_lines;
80    int prime_cache_en;
81    int prime_cache_on_const;
82    int clamp_consts;
83    int export_mode;
84    int uncached_first_inst;
85    struct radeon_bo *bo;
86} shader_config_t;
87
88/* Vertex buffer / vtx resource */
89typedef struct {
90    int id;
91    uint64_t vb_addr;
92    uint32_t vtx_num_entries;
93    uint32_t vtx_size_dw;
94    int clamp_x;
95    int format;
96    int num_format_all;
97    int format_comp_all;
98    int srf_mode_all;
99    int endian;
100    int mem_req_size;
101    struct radeon_bo *bo;
102} vtx_resource_t;
103
104/* Texture resource */
105typedef struct {
106    int id;
107    int w;
108    int h;
109    int pitch;
110    int depth;
111    int dim;
112    int tile_mode;
113    int tile_type;
114    int format;
115    uint64_t base;
116    uint64_t mip_base;
117    uint32_t size;
118    int format_comp_x;
119    int format_comp_y;
120    int format_comp_z;
121    int format_comp_w;
122    int num_format_all;
123    int srf_mode_all;
124    int force_degamma;
125    int endian;
126    int request_size;
127    int dst_sel_x;
128    int dst_sel_y;
129    int dst_sel_z;
130    int dst_sel_w;
131    int base_level;
132    int last_level;
133    int base_array;
134    int last_array;
135    int mpeg_clamp;
136    int perf_modulation;
137    int interlaced;
138    struct radeon_bo *bo;
139    struct radeon_bo *mip_bo;
140} tex_resource_t;
141
142/* Texture sampler */
143typedef struct {
144    int				id;
145    /* Clamping */
146    int				clamp_x, clamp_y, clamp_z;
147    int		       		border_color;
148    /* Filtering */
149    int				xy_mag_filter, xy_min_filter;
150    int				z_filter;
151    int				mip_filter;
152    bool_t			high_precision_filter;	/* ? */
153    int				perf_mip;		/* ? 0-7 */
154    int				perf_z;			/* ? 3 */
155    /* LoD selection */
156    int				min_lod, max_lod;	/* 0-0x3ff */
157    int                         lod_bias;		/* 0-0xfff (signed?) */
158    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
159    bool_t			lod_uses_minor_axis;	/* ? */
160    /* Other stuff */
161    bool_t			point_sampling_clamp;	/* ? */
162    bool_t			tex_array_override;	/* ? */
163    bool_t                      mc_coord_truncate;	/* ? */
164    bool_t			force_degamma;		/* ? */
165    bool_t			fetch_4;		/* ? */
166    bool_t			sample_is_pcf;		/* ? */
167    bool_t			type;			/* ? */
168    int				depth_compare;		/* only depth textures? */
169    int				chroma_key;
170} tex_sampler_t;
171
172/* Draw command */
173typedef struct {
174    uint32_t prim_type;
175    uint32_t vgt_draw_initiator;
176    uint32_t index_type;
177    uint32_t num_instances;
178    uint32_t num_indices;
179} draw_config_t;
180
181#if defined(XF86DRM_MODE)
182#define BEGIN_BATCH(n)				\
183do {					\
184    if (info->cs)			\
185	radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
186} while(0)
187#define END_BATCH()				\
188do {					\
189    if (info->cs)			\
190	radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
191} while(0)
192#define RELOC_BATCH(bo, rd, wd)					\
193do {							\
194    if (info->cs) {							\
195	int _ret;							\
196	_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
197	if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
198    }									\
199} while(0)
200#define E32(ib, dword)                                                  \
201do {                                                                    \
202    if (info->cs)							\
203	radeon_cs_write_dword(info->cs, (dword));			\
204    else {								\
205	uint32_t *ib_head = (pointer)(char*)(ib)->address;		\
206	ib_head[(ib)->used >> 2] = (dword);				\
207	(ib)->used += 4;						\
208    }									\
209} while (0)
210#else
211#define BEGIN_BATCH(n) do {(void)info;} while(0)
212#define END_BATCH() do {} while(0)
213#define RELOC_BATCH(bo, wd, rd) do {} while(0)
214#define E32(ib, dword)                                                  \
215do {                                                                    \
216    uint32_t *ib_head = (pointer)(char*)(ib)->address;			\
217    ib_head[(ib)->used >> 2] = (dword);					\
218    (ib)->used += 4;							\
219} while (0)
220#endif
221
222#define EFLOAT(ib, val)							\
223do {								        \
224    union { float f; uint32_t d; } a;                                   \
225    a.f = (val);								\
226    E32((ib), a.d);							\
227} while (0)
228
229#define PACK3(ib, cmd, num)	       					\
230do {                                                                    \
231    E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
232} while (0)
233
234/* write num registers, start at reg */
235/* If register falls in a special area, special commands are issued */
236#define PACK0(ib, reg, num)                                             \
237do {                                                                    \
238    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
239	PACK3((ib), IT_SET_CONFIG_REG, (num) + 1);			\
240	E32((ib), ((reg) - SET_CONFIG_REG_offset) >> 2);		\
241    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
242	PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1);			\
243	E32((ib), ((reg) - SET_CONTEXT_REG_offset) >> 2);		\
244    } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
245	PACK3((ib), IT_SET_ALU_CONST, (num) + 1);			\
246	E32((ib), ((reg) - SET_ALU_CONST_offset) >> 2);			\
247    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
248	PACK3((ib), IT_SET_RESOURCE, num + 1);				\
249	E32((ib), ((reg) - SET_RESOURCE_offset) >> 2);			\
250    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
251	PACK3((ib), IT_SET_SAMPLER, (num) + 1);				\
252	E32((ib), (reg - SET_SAMPLER_offset) >> 2);			\
253    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
254	PACK3((ib), IT_SET_CTL_CONST, (num) + 1);			\
255	E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2);		\
256    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
257	PACK3((ib), IT_SET_LOOP_CONST, (num) + 1);			\
258	E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2);		\
259    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
260	PACK3((ib), IT_SET_BOOL_CONST, (num) + 1);			\
261	E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2);		\
262    } else {								\
263	E32((ib), CP_PACKET0 ((reg), (num) - 1));			\
264    }									\
265} while (0)
266
267/* write a single register */
268#define EREG(ib, reg, val)                                              \
269do {								        \
270    PACK0((ib), (reg), 1);						\
271    E32((ib), (val));							\
272} while (0)
273
274void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
275void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
276
277void
278r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
279void
280r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
281void
282r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
283void
284r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
285void
286r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
287void
288r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
289void
290r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
291void
292r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
293void
294r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
295void
296r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
297void
298r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
299void
300r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
301void
302r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
303void
304r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
305void
306r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
307void
308r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
309void
310r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
311void
312r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
313void
314r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
315void
316r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
317
318void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
319
320Bool
321R600SetAccelState(ScrnInfoPtr pScrn,
322		  struct r600_accel_object *src0,
323		  struct r600_accel_object *src1,
324		  struct r600_accel_object *dst,
325		  uint32_t vs_offset, uint32_t ps_offset,
326		  int rop, Pixel planemask);
327
328extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
329extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
330extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
331extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
332				    int depth, int usage_hint, int bitsPerPixel,
333				    int *new_pitch);
334extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
335extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
336extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
337
338
339#endif
340