r600_state.h revision c503f109 
1#ifndef __R600_STATE_H__
2#define __R600_STATE_H__
3
4
5#include "xf86drm.h"
6
7typedef int bool_t;
8
9#define CLEAR(x) memset (&x, 0, sizeof(x))
10
11/* Sequencer / thread handling */
12typedef struct {
13    int ps_prio;
14    int vs_prio;
15    int gs_prio;
16    int es_prio;
17    int num_ps_gprs;
18    int num_vs_gprs;
19    int num_gs_gprs;
20    int num_es_gprs;
21    int num_temp_gprs;
22    int num_ps_threads;
23    int num_vs_threads;
24    int num_gs_threads;
25    int num_es_threads;
26    int num_ps_stack_entries;
27    int num_vs_stack_entries;
28    int num_gs_stack_entries;
29    int num_es_stack_entries;
30} sq_config_t;
31
32/* Color buffer / render target */
33typedef struct {
34    int id;
35    int w;
36    int h;
37    uint64_t base;
38    int format;
39    int endian;
40    int array_mode;						// tiling
41    int number_type;
42    int read_size;
43    int comp_swap;
44    int tile_mode;
45    int blend_clamp;
46    int clear_color;
47    int blend_bypass;
48    int blend_float32;
49    int simple_float;
50    int round_mode;
51    int tile_compact;
52    int source_format;
53} cb_config_t;
54
55/* Depth buffer */
56typedef struct {
57    int w;
58    int h;
59    uint64_t base;
60    int format;
61    int read_size;
62    int array_mode;						// tiling
63    int tile_surface_en;
64    int tile_compact;
65    int zrange_precision;
66} db_config_t;
67
68/* Shader */
69typedef struct {
70    uint64_t shader_addr;
71    int num_gprs;
72    int stack_size;
73    int dx10_clamp;
74    int prime_cache_pgm_en;
75    int prime_cache_on_draw;
76    int fetch_cache_lines;
77    int prime_cache_en;
78    int prime_cache_on_const;
79    int clamp_consts;
80    int export_mode;
81    int uncached_first_inst;
82} shader_config_t;
83
84/* Vertex buffer / vtx resource */
85typedef struct {
86    int id;
87    uint64_t vb_addr;
88    uint32_t vtx_num_entries;
89    uint32_t vtx_size_dw;
90    int clamp_x;
91    int format;
92    int num_format_all;
93    int format_comp_all;
94    int srf_mode_all;
95    int endian;
96    int mem_req_size;
97} vtx_resource_t;
98
99/* Texture resource */
100typedef struct {
101    int id;
102    int w;
103    int h;
104    int pitch;
105    int depth;
106    int dim;
107    int tile_mode;
108    int tile_type;
109    int format;
110    uint64_t base;
111    uint64_t mip_base;
112    int format_comp_x;
113    int format_comp_y;
114    int format_comp_z;
115    int format_comp_w;
116    int num_format_all;
117    int srf_mode_all;
118    int force_degamma;
119    int endian;
120    int request_size;
121    int dst_sel_x;
122    int dst_sel_y;
123    int dst_sel_z;
124    int dst_sel_w;
125    int base_level;
126    int last_level;
127    int base_array;
128    int last_array;
129    int mpeg_clamp;
130    int perf_modulation;
131    int interlaced;
132} tex_resource_t;
133
134/* Texture sampler */
135typedef struct {
136    int				id;
137    /* Clamping */
138    int				clamp_x, clamp_y, clamp_z;
139    int		       		border_color;
140    /* Filtering */
141    int				xy_mag_filter, xy_min_filter;
142    int				z_filter;
143    int				mip_filter;
144    bool_t			high_precision_filter;	/* ? */
145    int				perf_mip;		/* ? 0-7 */
146    int				perf_z;			/* ? 3 */
147    /* LoD selection */
148    int				min_lod, max_lod;	/* 0-0x3ff */
149    int                         lod_bias;		/* 0-0xfff (signed?) */
150    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
151    bool_t			lod_uses_minor_axis;	/* ? */
152    /* Other stuff */
153    bool_t			point_sampling_clamp;	/* ? */
154    bool_t			tex_array_override;	/* ? */
155    bool_t                      mc_coord_truncate;	/* ? */
156    bool_t			force_degamma;		/* ? */
157    bool_t			fetch_4;		/* ? */
158    bool_t			sample_is_pcf;		/* ? */
159    bool_t			type;			/* ? */
160    int				depth_compare;		/* only depth textures? */
161    int				chroma_key;
162} tex_sampler_t;
163
164/* Draw command */
165typedef struct {
166    uint32_t prim_type;
167    uint32_t vgt_draw_initiator;
168    uint32_t index_type;
169    uint32_t num_instances;
170    uint32_t num_indices;
171} draw_config_t;
172
173#define E32(ib, dword)                                                  \
174do {                                                                    \
175    uint32_t *ib_head = (pointer)(char*)(ib)->address;			\
176    ib_head[(ib)->used >> 2] = (dword);					\
177    (ib)->used += 4;							\
178} while (0)
179
180#define EFLOAT(ib, val)							\
181do {								        \
182    union { float f; uint32_t d; } a;                                   \
183    a.f = (val);								\
184    E32((ib), a.d);							\
185} while (0)
186
187#define PACK3(ib, cmd, num)	       					\
188do {                                                                    \
189    E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
190} while (0)
191
192/* write num registers, start at reg */
193/* If register falls in a special area, special commands are issued */
194#define PACK0(ib, reg, num)                                             \
195do {                                                                    \
196    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
197	PACK3((ib), IT_SET_CONFIG_REG, (num) + 1);			\
198	E32(ib, ((reg) - SET_CONFIG_REG_offset) >> 2);                  \
199    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
200	PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1);			\
201	E32(ib, ((reg) - SET_CONTEXT_REG_offset) >> 2);			\
202    } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
203	PACK3((ib), IT_SET_ALU_CONST, (num) + 1);			\
204	E32(ib, ((reg) - SET_ALU_CONST_offset) >> 2);			\
205    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
206	PACK3((ib), IT_SET_RESOURCE, num + 1);				\
207	E32((ib), ((reg) - SET_RESOURCE_offset) >> 2);			\
208    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
209	PACK3((ib), IT_SET_SAMPLER, (num) + 1);				\
210	E32((ib), (reg - SET_SAMPLER_offset) >> 2);			\
211    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
212	PACK3((ib), IT_SET_CTL_CONST, (num) + 1);			\
213	E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2);		\
214    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
215	PACK3((ib), IT_SET_LOOP_CONST, (num) + 1);			\
216	E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2);		\
217    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
218	PACK3((ib), IT_SET_BOOL_CONST, (num) + 1);			\
219	E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2);		\
220    } else {								\
221	E32((ib), CP_PACKET0 ((reg), (num) - 1));			\
222    }									\
223} while (0)
224
225/* write a single register */
226#define EREG(ib, reg, val)                                              \
227do {								        \
228    PACK0((ib), (reg), 1);						\
229    E32((ib), (val));							\
230} while (0)
231
232void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
233void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
234
235uint64_t
236upload (ScrnInfoPtr pScrn, void *shader, int size, int offset);
237void
238wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
239void
240wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
241void
242start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
243void
244set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf);
245void
246cp_set_surface_sync(ScrnInfoPtr pScrn, drmBufPtr ib, uint32_t sync_type, uint32_t size, uint64_t mc_addr);
247void
248cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, int crtc, int start, int stop);
249void
250fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf);
251void
252vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf);
253void
254ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf);
255void
256set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
257void
258set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
259void
260set_vtx_resource(ScrnInfoPtr pScrn, drmBufPtr ib, vtx_resource_t *res);
261void
262set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res);
263void
264set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
265void
266set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
267void
268set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
269void
270set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
271void
272set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
273void
274set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
275void
276set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
277void
278draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
279void
280draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
281
282#endif
283