radeon_kms.c revision 40732134 
1/*
2 * Copyright © 2009 Red Hat, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Dave Airlie <airlied@redhat.com>
25 *
26 */
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <errno.h>
32#include <sys/ioctl.h>
33/* Driver data structures */
34#include "radeon.h"
35#include "radeon_reg.h"
36#include "radeon_probe.h"
37#include "micmap.h"
38
39#include "shadow.h"
40
41#include "atipciids.h"
42
43
44#ifdef XF86DRM_MODE
45
46#include "radeon_chipset_gen.h"
47#include "radeon_chipinfo_gen.h"
48
49#define CURSOR_WIDTH	64
50#define CURSOR_HEIGHT	64
51
52#include "radeon_bo_gem.h"
53#include "radeon_cs_gem.h"
54#include "radeon_vbo.h"
55
56static Bool radeon_setup_kernel_mem(ScreenPtr pScreen);
57
58const OptionInfoRec RADEONOptions_KMS[] = {
59    { OPTION_NOACCEL,        "NoAccel",          OPTV_BOOLEAN, {0}, FALSE },
60    { OPTION_SW_CURSOR,      "SWcursor",         OPTV_BOOLEAN, {0}, FALSE },
61    { OPTION_PAGE_FLIP,      "EnablePageFlip",   OPTV_BOOLEAN, {0}, FALSE },
62    { OPTION_ACCEL_DFS,      "AccelDFS",         OPTV_BOOLEAN, {0}, FALSE },
63    { OPTION_IGNORE_EDID,    "IgnoreEDID",       OPTV_BOOLEAN, {0}, FALSE },
64    { OPTION_COLOR_TILING,   "ColorTiling",      OPTV_BOOLEAN, {0}, FALSE },
65    { OPTION_COLOR_TILING_2D,"ColorTiling2D",    OPTV_BOOLEAN, {0}, FALSE },
66    { OPTION_RENDER_ACCEL,   "RenderAccel",      OPTV_BOOLEAN, {0}, FALSE },
67    { OPTION_SUBPIXEL_ORDER, "SubPixelOrder",    OPTV_ANYSTR,  {0}, FALSE },
68    { OPTION_ACCELMETHOD,    "AccelMethod",      OPTV_STRING,  {0}, FALSE },
69    { OPTION_DRI,            "DRI",       	 OPTV_BOOLEAN, {0}, FALSE },
70    { OPTION_TVSTD,          "TVStandard",       OPTV_STRING,  {0}, FALSE },
71    { OPTION_EXA_VSYNC,      "EXAVSync",         OPTV_BOOLEAN, {0}, FALSE },
72    { OPTION_EXA_PIXMAPS,    "EXAPixmaps",	 OPTV_BOOLEAN,   {0}, FALSE },
73    { OPTION_ZAPHOD_HEADS,   "ZaphodHeads",      OPTV_STRING,  {0}, FALSE },
74    { OPTION_PAGE_FLIP,      "EnablePageFlip",   OPTV_BOOLEAN, {0}, FALSE },
75    { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE },
76    { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
77};
78
79void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
80{
81    RADEONInfoPtr  info = RADEONPTR(pScrn);
82    struct radeon_accel_state *accel_state = info->accel_state;
83    int ret;
84
85    if (!info->cs->cdw)
86	return;
87
88    /* release the current VBO so we don't block on mapping it later */
89    if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) {
90        radeon_vbo_put(pScrn, &info->accel_state->vbo);
91        info->accel_state->vbo.vb_start_op = -1;
92    }
93
94    /* release the current VBO so we don't block on mapping it later */
95    if (info->accel_state->cbuf.vb_bo) {
96        radeon_vbo_put(pScrn, &info->accel_state->cbuf);
97        info->accel_state->cbuf.vb_start_op = -1;
98    }
99
100    radeon_cs_emit(info->cs);
101    radeon_cs_erase(info->cs);
102
103    if (accel_state->use_vbos)
104        radeon_vbo_flush_bos(pScrn);
105
106    ret = radeon_cs_space_check_with_bo(info->cs,
107					accel_state->vbo.vb_bo,
108					RADEON_GEM_DOMAIN_GTT, 0);
109    if (ret)
110      ErrorF("space check failed in flush\n");
111
112    if (info->reemit_current2d && info->state_2d.op)
113        info->reemit_current2d(pScrn, info->state_2d.op);
114
115    if (info->dri2.enabled) {
116        info->accel_state->XInited3D = FALSE;
117        info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
118    }
119
120}
121
122void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
123			 int n, const char *file,
124			 const char *func, int line)
125{
126    RADEONInfoPtr  info = RADEONPTR(pScrn);
127
128    if (info->cs->cdw + n > info->cs->ndw) {
129	radeon_cs_flush_indirect(pScrn);
130
131    }
132    radeon_cs_begin(info->cs, n, file, func, line);
133}
134
135
136extern _X_EXPORT int gRADEONEntityIndex;
137
138static int getRADEONEntityIndex(void)
139{
140    return gRADEONEntityIndex;
141}
142
143static void *
144radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
145		   CARD32 *size, void *closure)
146{
147    ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
148    RADEONInfoPtr  info   = RADEONPTR(pScrn);
149    int stride;
150
151    stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
152    *size = stride;
153
154    return ((uint8_t *)info->front_bo->ptr + row * stride + offset);
155}
156
157static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
158{
159    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
160    RADEONInfoPtr  info   = RADEONPTR(pScrn);
161    PixmapPtr pixmap;
162    struct radeon_surface *surface;
163
164    pScreen->CreateScreenResources = info->CreateScreenResources;
165    if (!(*pScreen->CreateScreenResources)(pScreen))
166	return FALSE;
167    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
168
169    if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
170	return FALSE;
171
172    drmmode_uevent_init(pScrn, &info->drmmode);
173
174    if (info->r600_shadow_fb) {
175	pixmap = pScreen->GetScreenPixmap(pScreen);
176
177	if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
178		       radeonShadowWindow, 0, NULL))
179	    return FALSE;
180    }
181
182    if (info->dri2.enabled) {
183	if (info->front_bo) {
184	    PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
185	    radeon_set_pixmap_bo(pPix, info->front_bo);
186	    surface = radeon_get_pixmap_surface(pPix);
187	    if (surface) {
188		*surface = info->front_surface;
189	    }
190	}
191    }
192    return TRUE;
193}
194
195static void RADEONBlockHandler_KMS(int i, pointer blockData,
196				   pointer pTimeout, pointer pReadmask)
197{
198    ScreenPtr      pScreen = screenInfo.screens[i];
199    ScrnInfoPtr    pScrn   = xf86Screens[i];
200    RADEONInfoPtr  info    = RADEONPTR(pScrn);
201
202    pScreen->BlockHandler = info->BlockHandler;
203    (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
204    pScreen->BlockHandler = RADEONBlockHandler_KMS;
205
206    if (info->VideoTimerCallback)
207	(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
208    radeon_cs_flush_indirect(pScrn);
209}
210
211static void
212radeon_flush_callback(CallbackListPtr *list,
213		      pointer user_data, pointer call_data)
214{
215    ScrnInfoPtr pScrn = user_data;
216
217    if (pScrn->vtSema) {
218        radeon_cs_flush_indirect(pScrn);
219    }
220}
221
222static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn)
223{
224    RADEONInfoPtr info = RADEONPTR(pScrn);
225    struct drm_radeon_info ginfo;
226    int r;
227    uint32_t tmp;
228
229#ifndef RADEON_INFO_FUSION_GART_WORKING
230#define RADEON_INFO_FUSION_GART_WORKING 0x0c
231#endif
232    memset(&ginfo, 0, sizeof(ginfo));
233    ginfo.request = RADEON_INFO_FUSION_GART_WORKING;
234    ginfo.value = (uintptr_t)&tmp;
235    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
236    if (r) {
237	return FALSE;
238    }
239    if (tmp == 1)
240	return TRUE;
241    return FALSE;
242}
243
244static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
245{
246    RADEONInfoPtr info = RADEONPTR(pScrn);
247    struct drm_radeon_info ginfo;
248    int r;
249    uint32_t tmp;
250
251#ifndef RADEON_INFO_ACCEL_WORKING
252#define RADEON_INFO_ACCEL_WORKING 0x03
253#endif
254#ifndef RADEON_INFO_ACCEL_WORKING2
255#define RADEON_INFO_ACCEL_WORKING2 0x05
256#endif
257
258    memset(&ginfo, 0, sizeof(ginfo));
259    if (info->dri->pKernelDRMVersion->version_minor >= 5)
260	ginfo.request = RADEON_INFO_ACCEL_WORKING2;
261    else
262	ginfo.request = RADEON_INFO_ACCEL_WORKING;
263    ginfo.value = (uintptr_t)&tmp;
264    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
265    if (r) {
266        /* If kernel is too old before 2.6.32 than assume accel is working */
267        if (r == -EINVAL) {
268            xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel "
269                       "information, assuming accel is working\n");
270            return TRUE;
271        }
272        return FALSE;
273    }
274    if (tmp)
275        return TRUE;
276    return FALSE;
277}
278
279static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
280{
281    RADEONInfoPtr  info = RADEONPTR(pScrn);
282
283    if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
284	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
285	return FALSE;
286    }
287
288    if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
289	(!RADEONIsAccelWorking(pScrn))) {
290	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
291		   "GPU accel disabled or not working, using shadowfb for KMS\n");
292	info->r600_shadow_fb = TRUE;
293	if (!xf86LoadSubModule(pScrn, "shadow"))
294	    info->r600_shadow_fb = FALSE;
295	return TRUE;
296    }
297
298    if (info->ChipFamily == CHIP_FAMILY_PALM) {
299	info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn);
300    } else
301	info->accel_state->allowHWDFS = TRUE;
302
303    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
304	(info->ChipFamily == CHIP_FAMILY_RS200) ||
305	(info->ChipFamily == CHIP_FAMILY_RS300) ||
306	(info->ChipFamily == CHIP_FAMILY_RS400) ||
307	(info->ChipFamily == CHIP_FAMILY_RS480) ||
308	(info->ChipFamily == CHIP_FAMILY_RS600) ||
309	(info->ChipFamily == CHIP_FAMILY_RS690) ||
310	(info->ChipFamily == CHIP_FAMILY_RS740))
311	info->accel_state->has_tcl = FALSE;
312    else {
313	info->accel_state->has_tcl = TRUE;
314    }
315
316    info->useEXA = TRUE;
317
318    if (info->useEXA) {
319	int errmaj = 0, errmin = 0;
320	info->exaReq.majorversion = EXA_VERSION_MAJOR;
321	info->exaReq.minorversion = EXA_VERSION_MINOR;
322	if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL,
323			   &info->exaReq, &errmaj, &errmin)) {
324	    LoaderErrorMsg(NULL, "exa", errmaj, errmin);
325	    return FALSE;
326	}
327    }
328
329    return TRUE;
330}
331
332static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
333{
334    RADEONInfoPtr  info   = RADEONPTR(pScrn);
335    uint32_t cmd_stat;
336    int i;
337
338    info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
339    pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset);
340    if (!pScrn->chipset) {
341	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
342		   "ChipID 0x%04x is not recognized\n", info->Chipset);
343	return FALSE;
344    }
345
346    if (info->Chipset < 0) {
347	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
348		   "Chipset \"%s\" is not recognized\n", pScrn->chipset);
349	return FALSE;
350    }
351    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
352	       "Chipset: \"%s\" (ChipID = 0x%04x)\n",
353	       pScrn->chipset,
354	       info->Chipset);
355
356    for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
357	if (info->Chipset == RADEONCards[i].pci_device_id) {
358	    RADEONCardInfo *card = &RADEONCards[i];
359	    info->ChipFamily = card->chip_family;
360	    info->IsMobility = card->mobility;
361	    info->IsIGP = card->igp;
362	    break;
363	}
364    }
365
366    info->cardType = CARD_PCI;
367
368    PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG);
369    if (cmd_stat & RADEON_CAP_LIST) {
370	uint32_t cap_ptr, cap_id;
371
372	PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
373	cap_ptr &= RADEON_CAP_PTR_MASK;
374
375	while(cap_ptr != RADEON_CAP_ID_NULL) {
376	    PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr);
377	    if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
378		info->cardType = CARD_AGP;
379		break;
380	    }
381	    if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
382		info->cardType = CARD_PCIE;
383		break;
384	    }
385	    cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
386	}
387    }
388
389
390    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n",
391	       (info->cardType==CARD_PCI) ? "PCI" :
392		(info->cardType==CARD_PCIE) ? "PCIE" : "AGP");
393
394    /* treat PCIE IGP cards as PCI */
395    if (info->cardType == CARD_PCIE && info->IsIGP)
396	info->cardType = CARD_PCI;
397
398    if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP)
399	info->cardType = CARD_PCIE;
400
401    /* not sure about gart table requirements */
402    if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP)
403	info->cardType = CARD_PCIE;
404
405#ifdef RENDER
406    info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL,
407					     info->Chipset != PCI_CHIP_RN50_515E &&
408					     info->Chipset != PCI_CHIP_RN50_5969);
409#endif
410    return TRUE;
411}
412
413static Bool radeon_alloc_dri(ScrnInfoPtr pScrn)
414{
415    RADEONInfoPtr  info   = RADEONPTR(pScrn);
416    if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) {
417	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
418	return FALSE;
419    }
420
421    if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) {
422	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
423	return FALSE;
424    }
425    return TRUE;
426}
427
428static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
429{
430    RADEONInfoPtr  info   = RADEONPTR(pScrn);
431    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
432    struct pci_device *dev = info->PciInfo;
433    char *busid;
434    drmSetVersion sv;
435    int err;
436
437    if (pRADEONEnt->fd) {
438	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
439		   " reusing fd for second head\n");
440
441	info->dri2.drm_fd = pRADEONEnt->fd;
442	goto out;
443    }
444
445#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
446    XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d",
447                dev->domain, dev->bus, dev->dev, dev->func);
448#else
449    busid = XNFprintf("pci:%04x:%02x:%02x.%d",
450		      dev->domain, dev->bus, dev->dev, dev->func);
451#endif
452
453    info->dri2.drm_fd = drmOpen("radeon", busid);
454    if (info->dri2.drm_fd == -1) {
455
456	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
457		   "[drm] Failed to open DRM device for %s: %s\n",
458		   busid, strerror(errno));
459	free(busid);
460	return FALSE;
461    }
462    free(busid);
463
464    /* Check that what we opened was a master or a master-capable FD,
465     * by setting the version of the interface we'll use to talk to it.
466     * (see DRIOpenDRMMaster() in DRI1)
467     */
468    sv.drm_di_major = 1;
469    sv.drm_di_minor = 1;
470    sv.drm_dd_major = -1;
471    sv.drm_dd_minor = -1;
472    err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv);
473    if (err != 0) {
474	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
475		   "[drm] failed to set drm interface version.\n");
476	drmClose(info->dri2.drm_fd);
477	info->dri2.drm_fd = -1;
478
479	return FALSE;
480    }
481
482    pRADEONEnt->fd = info->dri2.drm_fd;
483 out:
484    info->drmmode.fd = info->dri2.drm_fd;
485    info->dri->drmFD = info->dri2.drm_fd;
486    return TRUE;
487}
488
489#ifdef EXA_MIXED_PIXMAPS
490
491static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
492{
493    RADEONInfoPtr  info   = RADEONPTR(pScrn);
494    struct drm_radeon_info ginfo;
495    int r;
496    uint32_t tmp;
497
498    if (info->ChipFamily < CHIP_FAMILY_R600)
499	return FALSE;
500
501#ifndef RADEON_INFO_TILING_CONFIG
502#define RADEON_INFO_TILING_CONFIG 0x6
503#endif
504
505    memset(&ginfo, 0, sizeof(ginfo));
506    ginfo.request = RADEON_INFO_TILING_CONFIG;
507    ginfo.value = (uintptr_t)&tmp;
508    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
509    if (r)
510	return FALSE;
511
512    info->tile_config = tmp;
513    info->r7xx_bank_op = 0;
514    if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
515	if (info->dri->pKernelDRMVersion->version_minor >= 7) {
516	    switch (info->tile_config & 0xf) {
517	    case 0:
518                info->num_channels = 1;
519                break;
520	    case 1:
521                info->num_channels = 2;
522                break;
523	    case 2:
524                info->num_channels = 4;
525                break;
526	    case 3:
527                info->num_channels = 8;
528                break;
529	    default:
530                return FALSE;
531	    }
532
533	    switch((info->tile_config & 0xf0) >> 4) {
534	    case 0:
535		info->num_banks = 4;
536		break;
537	    case 1:
538		info->num_banks = 8;
539		break;
540	    case 2:
541		info->num_banks = 16;
542		break;
543	    default:
544		return FALSE;
545	    }
546
547	    switch ((info->tile_config & 0xf00) >> 8) {
548	    case 0:
549                info->group_bytes = 256;
550                break;
551	    case 1:
552                info->group_bytes = 512;
553                break;
554	    default:
555                return FALSE;
556	    }
557	} else
558	    return FALSE;
559    } else {
560	switch((info->tile_config & 0xe) >> 1) {
561	case 0:
562	    info->num_channels = 1;
563	    break;
564	case 1:
565	    info->num_channels = 2;
566	    break;
567	case 2:
568	    info->num_channels = 4;
569	    break;
570	case 3:
571	    info->num_channels = 8;
572	    break;
573	default:
574	    return FALSE;
575	}
576	switch((info->tile_config & 0x30) >> 4) {
577	case 0:
578	    info->num_banks = 4;
579	    break;
580	case 1:
581	    info->num_banks = 8;
582	    break;
583	default:
584	    return FALSE;
585	}
586	switch((info->tile_config & 0xc0) >> 6) {
587	case 0:
588	    info->group_bytes = 256;
589	    break;
590	case 1:
591	    info->group_bytes = 512;
592	    break;
593	default:
594	    return FALSE;
595	}
596    }
597
598    info->have_tiling_info = TRUE;
599    return TRUE;
600}
601
602#endif /* EXA_MIXED_PIXMAPS */
603
604Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
605{
606    RADEONInfoPtr     info;
607    RADEONEntPtr pRADEONEnt;
608    DevUnion* pPriv;
609    Gamma  zeros = { 0.0, 0.0, 0.0 };
610    uint32_t tiling = 0;
611    int cpp;
612
613    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
614		   "RADEONPreInit_KMS\n");
615    if (pScrn->numEntities != 1) return FALSE;
616    if (!RADEONGetRec(pScrn)) return FALSE;
617
618    info               = RADEONPTR(pScrn);
619    info->MMIO         = NULL;
620    info->IsSecondary  = FALSE;
621    info->IsPrimary = FALSE;
622    info->kms_enabled = TRUE;
623    info->pEnt         = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
624    if (info->pEnt->location.type != BUS_PCI) goto fail;
625
626    pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
627				 getRADEONEntityIndex());
628    pRADEONEnt = pPriv->ptr;
629
630    if(xf86IsEntityShared(pScrn->entityList[0]))
631    {
632        if(xf86IsPrimInitDone(pScrn->entityList[0]))
633        {
634            info->IsSecondary = TRUE;
635            pRADEONEnt->pSecondaryScrn = pScrn;
636        }
637        else
638        {
639	    info->IsPrimary = TRUE;
640            xf86SetPrimInitDone(pScrn->entityList[0]);
641            pRADEONEnt->pPrimaryScrn = pScrn;
642            pRADEONEnt->HasSecondary = FALSE;
643        }
644    }
645
646    info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
647    pScrn->monitor     = pScrn->confScreen->monitor;
648
649    if (!RADEONPreInitVisual(pScrn))
650	goto fail;
651
652    xf86CollectOptions(pScrn, NULL);
653    if (!(info->Options = malloc(sizeof(RADEONOptions_KMS))))
654	goto fail;
655
656    memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS));
657    xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
658
659    if (!RADEONPreInitWeight(pScrn))
660	goto fail;
661
662    if (!RADEONPreInitChipType_KMS(pScrn))
663        goto fail;
664
665    if (!radeon_alloc_dri(pScrn))
666	return FALSE;
667
668    if (radeon_open_drm_master(pScrn) == FALSE) {
669	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
670	goto fail;
671    }
672
673    info->dri2.enabled = FALSE;
674    info->dri->pKernelDRMVersion = drmGetVersion(info->dri->drmFD);
675    if (info->dri->pKernelDRMVersion == NULL) {
676	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
677		   "RADEONDRIGetVersion failed to get the DRM version\n");
678	goto fail;
679    }
680
681    if (!RADEONPreInitAccel_KMS(pScrn))              goto fail;
682
683    info->allowColorTiling2D = FALSE;
684
685#ifdef EXA_MIXED_PIXMAPS
686    /* don't enable tiling if accel is not enabled */
687    if (!info->r600_shadow_fb) {
688	Bool colorTilingDefault =
689	    xorgGetVersion() >= XORG_VERSION_NUMERIC(1,9,4,901,0) &&
690	    info->ChipFamily >= CHIP_FAMILY_R300 &&
691	    info->ChipFamily <= CHIP_FAMILY_ARUBA;
692
693	/* 2D color tiling */
694	if (info->ChipFamily >= CHIP_FAMILY_R600) {
695		info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, FALSE);
696	}
697
698	if (info->ChipFamily >= CHIP_FAMILY_R600) {
699	    /* set default group bytes, overridden by kernel info below */
700	    info->group_bytes = 256;
701	    info->have_tiling_info = FALSE;
702	    if (info->dri->pKernelDRMVersion->version_minor >= 6) {
703		if (r600_get_tile_config(pScrn)) {
704		    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
705								  OPTION_COLOR_TILING, colorTilingDefault);
706		    /* need working DFS for tiling */
707		    if ((info->ChipFamily == CHIP_FAMILY_PALM) &&
708			(!info->accel_state->allowHWDFS))
709			info->allowColorTiling = FALSE;
710		} else
711		    info->allowColorTiling = FALSE;
712	    } else
713		xf86DrvMsg(pScrn->scrnIndex, X_INFO,
714			   "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
715	} else
716	    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
717							  OPTION_COLOR_TILING, colorTilingDefault);
718    } else
719#else
720    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
721	       "KMS Color Tiling requires xserver which supports EXA_MIXED_PIXMAPS\n");
722#endif
723	info->allowColorTiling = FALSE;
724
725    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
726	 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
727
728    if (info->dri->pKernelDRMVersion->version_minor >= 8) {
729	info->allowPageFlip = xf86ReturnOptValBool(info->Options,
730						   OPTION_PAGE_FLIP, TRUE);
731	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
732		   "KMS Pageflipping: %sabled\n", info->allowPageFlip ? "en" : "dis");
733    }
734
735    info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
736						 OPTION_SWAPBUFFERS_WAIT, TRUE);
737    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
738	       "SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait ? "en" : "dis");
739
740    if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
741	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
742	goto fail;
743    }
744
745    if (info->drmmode.mode_res->count_crtcs == 1)
746        pRADEONEnt->HasCRTC2 = FALSE;
747    else
748        pRADEONEnt->HasCRTC2 = TRUE;
749
750
751    /* fix up cloning on rn50 cards
752     * since they only have one crtc sometimes the xserver doesn't assign
753     * a crtc to one of the outputs even though both outputs have common modes
754     * which results in only one monitor being enabled.  Assign a crtc here so
755     * that both outputs light up.
756     */
757    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
758	xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
759	int i;
760
761	for (i = 0; i < xf86_config->num_output; i++) {
762	    xf86OutputPtr output = xf86_config->output[i];
763
764	    /* XXX: double check crtc mode */
765	    if ((output->probed_modes != NULL) && (output->crtc == NULL))
766		output->crtc = xf86_config->crtc[0];
767	}
768    }
769
770    {
771	struct drm_radeon_gem_info mminfo;
772
773	if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
774	{
775	    info->vram_size = mminfo.vram_visible;
776	    info->gart_size = mminfo.gart_size;
777	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
778		       "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n",
779		       (unsigned long long)mminfo.gart_size,
780		       (unsigned long long)mminfo.vram_size,
781		       (unsigned long long)mminfo.vram_visible);
782	}
783    }
784
785    info->exa_pixmaps = xf86ReturnOptValBool(info->Options,
786                                             OPTION_EXA_PIXMAPS,
787					     ((info->vram_size > (32 * 1024 * 1024) &&
788					      info->RenderAccel)));
789    if (info->exa_pixmaps)
790    	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
791		"EXA: Driver will allow EXA pixmaps in VRAM\n");
792    else
793    	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
794		"EXA: Driver will not allow EXA pixmaps in VRAM\n");
795
796    /* no tiled scanout on r6xx+ yet */
797    if (info->allowColorTiling) {
798	if (info->ChipFamily >= CHIP_FAMILY_R600)
799	    tiling |= RADEON_TILING_MICRO;
800	else
801	    tiling |= RADEON_TILING_MACRO;
802    }
803    cpp = pScrn->bitsPerPixel / 8;
804    pScrn->displayWidth =
805	RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling));
806    info->CurrentLayout.displayWidth = pScrn->displayWidth;
807
808    /* Set display resolution */
809    xf86SetDpi(pScrn, 0, 0);
810
811	/* Get ScreenInit function */
812    if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
813
814    if (!xf86SetGamma(pScrn, zeros)) return FALSE;
815
816    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
817	if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
818    }
819
820    if (pScrn->modes == NULL) {
821      xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
822      goto fail;
823   }
824
825    return TRUE;
826 fail:
827    RADEONFreeRec(pScrn);
828    return FALSE;
829
830}
831
832static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
833{
834    return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
835			      (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
836			       HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
837			       HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
838			       HARDWARE_CURSOR_UPDATE_UNHIDDEN |
839			       HARDWARE_CURSOR_ARGB));
840}
841
842static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode)
843{
844    ScrnInfoPtr  pScrn = xf86Screens[pScreen->myNum];
845    Bool         unblank;
846
847    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
848		   "RADEONSaveScreen(%d)\n", mode);
849
850    unblank = xf86IsUnblank(mode);
851    if (unblank) SetTimeSinceLastInputEvent();
852
853    if ((pScrn != NULL) && pScrn->vtSema) {
854	if (unblank)
855	    RADEONUnblank(pScrn);
856	else
857	    RADEONBlank(pScrn);
858    }
859    return TRUE;
860}
861
862/* Called at the end of each server generation.  Restore the original
863 * text mode, unmap video memory, and unwrap and call the saved
864 * CloseScreen function.
865 */
866static Bool RADEONCloseScreen_KMS(int scrnIndex, ScreenPtr pScreen)
867{
868    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
869    RADEONInfoPtr  info  = RADEONPTR(pScrn);
870
871    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
872		   "RADEONCloseScreen\n");
873
874    drmmode_uevent_fini(pScrn, &info->drmmode);
875    if (info->cs)
876      radeon_cs_flush_indirect(pScrn);
877
878    DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
879
880    if (info->accel_state->exa) {
881	exaDriverFini(pScreen);
882	free(info->accel_state->exa);
883	info->accel_state->exa = NULL;
884    }
885
886    if (info->accel_state->use_vbos)
887        radeon_vbo_free_lists(pScrn);
888
889    drmDropMaster(info->dri->drmFD);
890
891    if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
892    info->cursor = NULL;
893
894    if (info->dri2.enabled)
895	radeon_dri2_close_screen(pScreen);
896
897    pScrn->vtSema = FALSE;
898    xf86ClearPrimInitDone(info->pEnt->index);
899    pScreen->BlockHandler = info->BlockHandler;
900    pScreen->CloseScreen = info->CloseScreen;
901    return (*pScreen->CloseScreen)(scrnIndex, pScreen);
902}
903
904
905void RADEONFreeScreen_KMS(int scrnIndex, int flags)
906{
907    ScrnInfoPtr  pScrn = xf86Screens[scrnIndex];
908    RADEONInfoPtr  info  = RADEONPTR(pScrn);
909
910    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
911		   "RADEONFreeScreen\n");
912
913    /* when server quits at PreInit, we don't need do this anymore*/
914    if (!info) return;
915
916    RADEONFreeRec(pScrn);
917}
918
919Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
920			  int argc, char **argv)
921{
922    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
923    RADEONInfoPtr  info  = RADEONPTR(pScrn);
924    int            subPixelOrder = SubPixelUnknown;
925    char*          s;
926    void *front_ptr;
927    int ret;
928
929    pScrn->fbOffset = 0;
930
931    miClearVisualTypes();
932    if (!miSetVisualTypes(pScrn->depth,
933			  miGetDefaultVisualMask(pScrn->depth),
934			  pScrn->rgbBits,
935			  pScrn->defaultVisual)) return FALSE;
936    miSetPixmapDepths ();
937
938    ret = drmSetMaster(info->dri->drmFD);
939    if (ret) {
940        ErrorF("Unable to retrieve master\n");
941        return FALSE;
942    }
943    info->directRenderingEnabled = FALSE;
944    if (info->r600_shadow_fb == FALSE)
945        info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
946
947    front_ptr = info->FB;
948
949    info->surf_man = radeon_surface_manager_new(info->dri->drmFD);
950    if (!info->bufmgr)
951        info->bufmgr = radeon_bo_manager_gem_ctor(info->dri->drmFD);
952    if (!info->bufmgr) {
953	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
954		   "failed to initialise GEM buffer manager");
955	return FALSE;
956    }
957    drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr);
958
959    if (!info->csm)
960        info->csm = radeon_cs_manager_gem_ctor(info->dri->drmFD);
961    if (!info->csm) {
962	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
963		   "failed to initialise command submission manager");
964	return FALSE;
965    }
966
967    if (!info->cs)
968        info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4);
969    if (!info->cs) {
970	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
971		   "failed to initialise command submission buffer");
972	return FALSE;
973    }
974
975    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size);
976    radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn);
977
978    radeon_setup_kernel_mem(pScreen);
979    front_ptr = info->front_bo->ptr;
980
981    if (info->r600_shadow_fb) {
982	info->fb_shadow = calloc(1,
983				 pScrn->displayWidth * pScrn->virtualY *
984				 ((pScrn->bitsPerPixel + 7) >> 3));
985	if (info->fb_shadow == NULL) {
986	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
987                       "Failed to allocate shadow framebuffer\n");
988	    info->r600_shadow_fb = FALSE;
989	} else {
990	    if (!fbScreenInit(pScreen, info->fb_shadow,
991			      pScrn->virtualX, pScrn->virtualY,
992			      pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
993			      pScrn->bitsPerPixel))
994		return FALSE;
995	}
996    }
997
998    if (info->r600_shadow_fb == FALSE) {
999	/* Init fb layer */
1000	if (!fbScreenInit(pScreen, front_ptr,
1001			  pScrn->virtualX, pScrn->virtualY,
1002			  pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
1003			  pScrn->bitsPerPixel))
1004	    return FALSE;
1005    }
1006
1007    xf86SetBlackWhitePixels(pScreen);
1008
1009    if (pScrn->bitsPerPixel > 8) {
1010	VisualPtr  visual;
1011
1012	visual = pScreen->visuals + pScreen->numVisuals;
1013	while (--visual >= pScreen->visuals) {
1014	    if ((visual->class | DynamicClass) == DirectColor) {
1015		visual->offsetRed   = pScrn->offset.red;
1016		visual->offsetGreen = pScrn->offset.green;
1017		visual->offsetBlue  = pScrn->offset.blue;
1018		visual->redMask     = pScrn->mask.red;
1019		visual->greenMask   = pScrn->mask.green;
1020		visual->blueMask    = pScrn->mask.blue;
1021	    }
1022	}
1023    }
1024
1025    /* Must be after RGB order fixed */
1026    fbPictureInit (pScreen, 0, 0);
1027
1028#ifdef RENDER
1029    if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) {
1030	if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB;
1031	else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
1032	else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
1033	PictureSetSubpixelOrder (pScreen, subPixelOrder);
1034    }
1035#endif
1036
1037    pScrn->vtSema = TRUE;
1038    /* Backing store setup */
1039    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1040		   "Initializing backing store\n");
1041    miInitializeBackingStore(pScreen);
1042    xf86SetBackingStore(pScreen);
1043
1044
1045    if (info->directRenderingEnabled) {
1046	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
1047    } else {
1048	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
1049		   "Direct rendering disabled\n");
1050    }
1051
1052    if (info->r600_shadow_fb) {
1053	xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
1054	info->accelOn = FALSE;
1055    } else {
1056	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1057		       "Initializing Acceleration\n");
1058	if (RADEONAccelInit(pScreen)) {
1059	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
1060	    info->accelOn = TRUE;
1061	} else {
1062	    xf86DrvMsg(scrnIndex, X_ERROR,
1063		       "Acceleration initialization failed\n");
1064	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
1065	    info->accelOn = FALSE;
1066	}
1067    }
1068
1069    /* Init DPMS */
1070    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1071		   "Initializing DPMS\n");
1072    xf86DPMSInit(pScreen, xf86DPMSSet, 0);
1073
1074    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1075		   "Initializing Cursor\n");
1076
1077    /* Set Silken Mouse */
1078    xf86SetSilkenMouse(pScreen);
1079
1080    /* Cursor setup */
1081    miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
1082
1083    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
1084	if (RADEONCursorInit_KMS(pScreen)) {
1085	}
1086    }
1087
1088    /* DGA setup */
1089#ifdef XFreeXDGA
1090    /* DGA is dangerous on kms as the base and framebuffer location may change:
1091     * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html
1092     */
1093    /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
1094#endif
1095    if (info->r600_shadow_fb == FALSE) {
1096        /* Init Xv */
1097        xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1098                       "Initializing Xv\n");
1099        RADEONInitVideo(pScreen);
1100    }
1101
1102    if (info->r600_shadow_fb == TRUE) {
1103        if (!shadowSetup(pScreen)) {
1104	    xf86DrvMsg(scrnIndex, X_ERROR,
1105		       "Shadowfb initialization failed\n");
1106            return FALSE;
1107        }
1108    }
1109    pScrn->pScreen = pScreen;
1110
1111    /* Provide SaveScreen & wrap BlockHandler and CloseScreen */
1112    /* Wrap CloseScreen */
1113    info->CloseScreen    = pScreen->CloseScreen;
1114    pScreen->CloseScreen = RADEONCloseScreen_KMS;
1115    pScreen->SaveScreen  = RADEONSaveScreen_KMS;
1116    info->BlockHandler = pScreen->BlockHandler;
1117    pScreen->BlockHandler = RADEONBlockHandler_KMS;
1118
1119    if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn))
1120        return FALSE;
1121
1122    info->CreateScreenResources = pScreen->CreateScreenResources;
1123    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
1124
1125   if (!xf86CrtcScreenInit (pScreen))
1126       return FALSE;
1127
1128   /* Wrap pointer motion to flip touch screen around */
1129//    info->PointerMoved = pScrn->PointerMoved;
1130//    pScrn->PointerMoved = RADEONPointerMoved;
1131
1132    if (!drmmode_setup_colormap(pScreen, pScrn))
1133	return FALSE;
1134
1135   /* Note unused options */
1136    if (serverGeneration == 1)
1137	xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
1138
1139    drmmode_init(pScrn, &info->drmmode);
1140
1141    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1142		   "RADEONScreenInit finished\n");
1143
1144    info->accel_state->XInited3D = FALSE;
1145    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1146
1147    return TRUE;
1148}
1149
1150Bool RADEONEnterVT_KMS(int scrnIndex, int flags)
1151{
1152    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
1153    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1154    int ret;
1155
1156    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1157		   "RADEONEnterVT_KMS\n");
1158
1159
1160    ret = drmSetMaster(info->dri->drmFD);
1161    if (ret)
1162	ErrorF("Unable to retrieve master\n");
1163    info->accel_state->XInited3D = FALSE;
1164    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1165
1166    pScrn->vtSema = TRUE;
1167
1168    if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
1169	return FALSE;
1170
1171    if (info->adaptor)
1172	RADEONResetVideo(pScrn);
1173
1174    return TRUE;
1175}
1176
1177
1178void RADEONLeaveVT_KMS(int scrnIndex, int flags)
1179{
1180    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
1181    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1182
1183    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1184		   "RADEONLeaveVT_KMS\n");
1185
1186    drmDropMaster(info->dri->drmFD);
1187
1188#ifdef HAVE_FREE_SHADOW
1189    xf86RotateFreeShadow(pScrn);
1190#endif
1191
1192    xf86_hide_cursors (pScrn);
1193    info->accel_state->XInited3D = FALSE;
1194    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1195
1196    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1197		   "Ok, leaving now...\n");
1198}
1199
1200
1201Bool RADEONSwitchMode_KMS(int scrnIndex, DisplayModePtr mode, int flags)
1202{
1203    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
1204    Bool ret;
1205    ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
1206    return ret;
1207
1208}
1209
1210void RADEONAdjustFrame_KMS(int scrnIndex, int x, int y, int flags)
1211{
1212    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
1213    RADEONInfoPtr  info        = RADEONPTR(pScrn);
1214    drmmode_adjust_frame(pScrn, &info->drmmode, x, y, flags);
1215    return;
1216}
1217
1218static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
1219{
1220    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
1221    RADEONInfoPtr info = RADEONPTR(pScrn);
1222    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1223    int cpp = info->CurrentLayout.pixel_bytes;
1224    int screen_size;
1225    int pitch, base_align;
1226    int total_size_bytes = 0;
1227    uint32_t tiling_flags = 0;
1228    struct radeon_surface surface;
1229
1230    if (info->accel_state->exa != NULL) {
1231	xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
1232	return FALSE;
1233    }
1234    if (info->r600_shadow_fb == FALSE) {
1235        info->accel_state->exa = exaDriverAlloc();
1236        if (info->accel_state->exa == NULL)
1237	    return FALSE;
1238    }
1239
1240    if (info->allowColorTiling) {
1241	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1242		if (info->allowColorTiling2D) {
1243			tiling_flags |= RADEON_TILING_MACRO;
1244		} else {
1245			tiling_flags |= RADEON_TILING_MICRO;
1246		}
1247	} else
1248	    tiling_flags |= RADEON_TILING_MACRO;
1249    }
1250    pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
1251    screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
1252    base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
1253	if (info->ChipFamily >= CHIP_FAMILY_R600) {
1254		memset(&surface, 0, sizeof(struct radeon_surface));
1255		surface.npix_x = pScrn->displayWidth;
1256		surface.npix_y = pScrn->virtualY;
1257		surface.npix_z = 1;
1258		surface.blk_w = 1;
1259		surface.blk_h = 1;
1260		surface.blk_d = 1;
1261		surface.array_size = 1;
1262		surface.last_level = 0;
1263		surface.bpe = cpp;
1264		surface.nsamples = 1;
1265		surface.flags = RADEON_SURF_SCANOUT;
1266		surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
1267		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
1268		if (tiling_flags & RADEON_TILING_MICRO) {
1269			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
1270			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1271		}
1272		if (tiling_flags & RADEON_TILING_MACRO) {
1273			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
1274			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
1275		}
1276		if (radeon_surface_best(info->surf_man, &surface)) {
1277			return FALSE;
1278		}
1279		if (radeon_surface_init(info->surf_man, &surface)) {
1280			return FALSE;
1281		}
1282		pitch = surface.level[0].pitch_bytes;
1283		screen_size = surface.bo_size;
1284		base_align = surface.bo_alignment;
1285		tiling_flags = 0;
1286		switch (surface.level[0].mode) {
1287		case RADEON_SURF_MODE_2D:
1288			tiling_flags |= RADEON_TILING_MACRO;
1289			tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
1290			tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
1291			tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
1292			tiling_flags |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
1293			break;
1294		case RADEON_SURF_MODE_1D:
1295			tiling_flags |= RADEON_TILING_MICRO;
1296			break;
1297		default:
1298			break;
1299		}
1300		info->front_surface = surface;
1301	}
1302    {
1303	int cursor_size = 64 * 4 * 64;
1304	int c;
1305
1306	cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
1307	for (c = 0; c < xf86_config->num_crtc; c++) {
1308	    /* cursor objects */
1309            if (info->cursor_bo[c] == NULL) {
1310                info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0,
1311                                                    cursor_size, 0,
1312                                                    RADEON_GEM_DOMAIN_VRAM, 0);
1313                if (!info->cursor_bo[c]) {
1314                    return FALSE;
1315                }
1316
1317                if (radeon_bo_map(info->cursor_bo[c], 1)) {
1318                    ErrorF("Failed to map cursor buffer memory\n");
1319                }
1320
1321                drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]);
1322                total_size_bytes += cursor_size;
1323            }
1324        }
1325    }
1326
1327    screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
1328    /* keep area front front buffer - but don't allocate it yet */
1329    total_size_bytes += screen_size;
1330
1331    info->dri->textureSize = 0;
1332
1333    if (info->front_bo == NULL) {
1334        info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
1335                                        base_align, RADEON_GEM_DOMAIN_VRAM, 0);
1336        if (info->r600_shadow_fb == TRUE) {
1337            if (radeon_bo_map(info->front_bo, 1)) {
1338                ErrorF("Failed to map cursor buffer memory\n");
1339            }
1340        }
1341#if X_BYTE_ORDER == X_BIG_ENDIAN
1342	switch (cpp) {
1343	case 4:
1344	    tiling_flags |= RADEON_TILING_SWAP_32BIT;
1345	    break;
1346	case 2:
1347	    tiling_flags |= RADEON_TILING_SWAP_16BIT;
1348	    break;
1349	}
1350#endif
1351	if (tiling_flags)
1352            radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
1353    }
1354
1355    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024);
1356    radeon_kms_update_vram_limit(pScrn, screen_size);
1357    return TRUE;
1358}
1359
1360void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
1361{
1362    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1363    RADEONInfoPtr info = RADEONPTR(pScrn);
1364    int remain_size_bytes;
1365    int total_size_bytes;
1366    int c;
1367
1368    for (c = 0; c < xf86_config->num_crtc; c++) {
1369	if (info->cursor_bo[c] != NULL) {
1370	    total_size_bytes += (64 * 4 * 64);
1371	}
1372    }
1373
1374    total_size_bytes += new_fb_size;
1375    remain_size_bytes = info->vram_size - new_fb_size;
1376    remain_size_bytes = (remain_size_bytes / 10) * 9;
1377    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes);
1378
1379    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024);
1380}
1381
1382
1383#endif
1384