radeon_kms.c revision b13dfe66 
1/*
2 * Copyright © 2009 Red Hat, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 *    Dave Airlie <airlied@redhat.com>
25 *
26 */
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <errno.h>
32#include <sys/ioctl.h>
33/* Driver data structures */
34#include "radeon.h"
35#include "radeon_reg.h"
36#include "radeon_probe.h"
37#include "micmap.h"
38
39#include "shadow.h"
40
41#include "atipciids.h"
42
43
44#ifdef XF86DRM_MODE
45
46#include "radeon_chipset_gen.h"
47#include "radeon_chipinfo_gen.h"
48
49#define CURSOR_WIDTH	64
50#define CURSOR_HEIGHT	64
51
52#include "radeon_bo_gem.h"
53#include "radeon_cs_gem.h"
54#include "radeon_vbo.h"
55
56static Bool radeon_setup_kernel_mem(ScreenPtr pScreen);
57
58const OptionInfoRec RADEONOptions_KMS[] = {
59    { OPTION_NOACCEL,        "NoAccel",          OPTV_BOOLEAN, {0}, FALSE },
60    { OPTION_SW_CURSOR,      "SWcursor",         OPTV_BOOLEAN, {0}, FALSE },
61    { OPTION_PAGE_FLIP,      "EnablePageFlip",   OPTV_BOOLEAN, {0}, FALSE },
62    { OPTION_ACCEL_DFS,      "AccelDFS",         OPTV_BOOLEAN, {0}, FALSE },
63    { OPTION_IGNORE_EDID,    "IgnoreEDID",       OPTV_BOOLEAN, {0}, FALSE },
64    { OPTION_COLOR_TILING,   "ColorTiling",      OPTV_BOOLEAN, {0}, FALSE },
65    { OPTION_RENDER_ACCEL,   "RenderAccel",      OPTV_BOOLEAN, {0}, FALSE },
66    { OPTION_SUBPIXEL_ORDER, "SubPixelOrder",    OPTV_ANYSTR,  {0}, FALSE },
67    { OPTION_ACCELMETHOD,    "AccelMethod",      OPTV_STRING,  {0}, FALSE },
68    { OPTION_DRI,            "DRI",       	 OPTV_BOOLEAN, {0}, FALSE },
69    { OPTION_TVSTD,          "TVStandard",       OPTV_STRING,  {0}, FALSE },
70    { OPTION_EXA_VSYNC,      "EXAVSync",         OPTV_BOOLEAN, {0}, FALSE },
71    { OPTION_EXA_PIXMAPS,    "EXAPixmaps",	 OPTV_BOOLEAN,   {0}, FALSE },
72    { OPTION_ZAPHOD_HEADS,   "ZaphodHeads",      OPTV_STRING,  {0}, FALSE },
73    { OPTION_PAGE_FLIP,      "EnablePageFlip",   OPTV_BOOLEAN, {0}, FALSE },
74    { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE },
75    { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
76};
77
78void radeon_cs_flush_indirect(ScrnInfoPtr pScrn)
79{
80    RADEONInfoPtr  info = RADEONPTR(pScrn);
81    struct radeon_accel_state *accel_state = info->accel_state;
82    int ret;
83
84    if (!info->cs->cdw)
85	return;
86
87    /* release the current VBO so we don't block on mapping it later */
88    if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) {
89        radeon_vbo_put(pScrn, &info->accel_state->vbo);
90        info->accel_state->vbo.vb_start_op = -1;
91    }
92
93    /* release the current VBO so we don't block on mapping it later */
94    if (info->accel_state->cbuf.vb_bo) {
95        radeon_vbo_put(pScrn, &info->accel_state->cbuf);
96        info->accel_state->cbuf.vb_start_op = -1;
97    }
98
99    radeon_cs_emit(info->cs);
100    radeon_cs_erase(info->cs);
101
102    if (accel_state->use_vbos)
103        radeon_vbo_flush_bos(pScrn);
104
105    ret = radeon_cs_space_check_with_bo(info->cs,
106					accel_state->vbo.vb_bo,
107					RADEON_GEM_DOMAIN_GTT, 0);
108    if (ret)
109      ErrorF("space check failed in flush\n");
110
111    if (info->reemit_current2d && info->state_2d.op)
112        info->reemit_current2d(pScrn, info->state_2d.op);
113
114    if (info->dri2.enabled) {
115        info->accel_state->XInited3D = FALSE;
116        info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
117    }
118
119}
120
121void radeon_ddx_cs_start(ScrnInfoPtr pScrn,
122			 int n, const char *file,
123			 const char *func, int line)
124{
125    RADEONInfoPtr  info = RADEONPTR(pScrn);
126
127    if (info->cs->cdw + n > info->cs->ndw) {
128	radeon_cs_flush_indirect(pScrn);
129
130    }
131    radeon_cs_begin(info->cs, n, file, func, line);
132}
133
134
135extern _X_EXPORT int gRADEONEntityIndex;
136
137static int getRADEONEntityIndex(void)
138{
139    return gRADEONEntityIndex;
140}
141
142static void *
143radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
144		   CARD32 *size, void *closure)
145{
146    ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
147    RADEONInfoPtr  info   = RADEONPTR(pScrn);
148    int stride;
149
150    stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
151    *size = stride;
152
153    return ((uint8_t *)info->front_bo->ptr + row * stride + offset);
154}
155
156static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen)
157{
158    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
159    RADEONInfoPtr  info   = RADEONPTR(pScrn);
160    PixmapPtr pixmap;
161
162    pScreen->CreateScreenResources = info->CreateScreenResources;
163    if (!(*pScreen->CreateScreenResources)(pScreen))
164	return FALSE;
165    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
166
167    if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
168	return FALSE;
169
170    drmmode_uevent_init(pScrn, &info->drmmode);
171
172    if (info->r600_shadow_fb) {
173	pixmap = pScreen->GetScreenPixmap(pScreen);
174
175	if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
176		       radeonShadowWindow, 0, NULL))
177	    return FALSE;
178    }
179
180    if (info->dri2.enabled) {
181	if (info->front_bo) {
182	    PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
183	    radeon_set_pixmap_bo(pPix, info->front_bo);
184	}
185    }
186    return TRUE;
187}
188
189static void RADEONBlockHandler_KMS(int i, pointer blockData,
190				   pointer pTimeout, pointer pReadmask)
191{
192    ScreenPtr      pScreen = screenInfo.screens[i];
193    ScrnInfoPtr    pScrn   = xf86Screens[i];
194    RADEONInfoPtr  info    = RADEONPTR(pScrn);
195
196    pScreen->BlockHandler = info->BlockHandler;
197    (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
198    pScreen->BlockHandler = RADEONBlockHandler_KMS;
199
200    if (info->VideoTimerCallback)
201	(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
202    radeon_cs_flush_indirect(pScrn);
203}
204
205static void
206radeon_flush_callback(CallbackListPtr *list,
207		      pointer user_data, pointer call_data)
208{
209    ScrnInfoPtr pScrn = user_data;
210
211    if (pScrn->vtSema) {
212        radeon_cs_flush_indirect(pScrn);
213    }
214}
215
216static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn)
217{
218    RADEONInfoPtr info = RADEONPTR(pScrn);
219    struct drm_radeon_info ginfo;
220    int r;
221    uint32_t tmp;
222
223#ifndef RADEON_INFO_ACCEL_WORKING
224#define RADEON_INFO_ACCEL_WORKING 0x03
225#endif
226#ifndef RADEON_INFO_ACCEL_WORKING2
227#define RADEON_INFO_ACCEL_WORKING2 0x05
228#endif
229
230    memset(&ginfo, 0, sizeof(ginfo));
231    if (info->dri->pKernelDRMVersion->version_minor >= 5)
232	ginfo.request = RADEON_INFO_ACCEL_WORKING2;
233    else
234	ginfo.request = RADEON_INFO_ACCEL_WORKING;
235    ginfo.value = (uintptr_t)&tmp;
236    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
237    if (r) {
238        /* If kernel is too old before 2.6.32 than assume accel is working */
239        if (r == -EINVAL) {
240            xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel "
241                       "information, assuming accel is working\n");
242            return TRUE;
243        }
244        return FALSE;
245    }
246    if (tmp)
247        return TRUE;
248    return FALSE;
249}
250
251static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
252{
253    RADEONInfoPtr  info = RADEONPTR(pScrn);
254
255    if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) {
256	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n");
257	return FALSE;
258    }
259
260    if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
261	(info->ChipFamily >= CHIP_FAMILY_CAYMAN) ||
262	(!RADEONIsAccelWorking(pScrn))) {
263	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
264		   "GPU accel disabled or not working, using shadowfb for KMS\n");
265	info->r600_shadow_fb = TRUE;
266	if (!xf86LoadSubModule(pScrn, "shadow"))
267	    info->r600_shadow_fb = FALSE;
268	return TRUE;
269    }
270
271    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
272	(info->ChipFamily == CHIP_FAMILY_RS200) ||
273	(info->ChipFamily == CHIP_FAMILY_RS300) ||
274	(info->ChipFamily == CHIP_FAMILY_RS400) ||
275	(info->ChipFamily == CHIP_FAMILY_RS480) ||
276	(info->ChipFamily == CHIP_FAMILY_RS600) ||
277	(info->ChipFamily == CHIP_FAMILY_RS690) ||
278	(info->ChipFamily == CHIP_FAMILY_RS740))
279	info->accel_state->has_tcl = FALSE;
280    else {
281	info->accel_state->has_tcl = TRUE;
282    }
283
284    info->useEXA = TRUE;
285
286    if (info->useEXA) {
287	int errmaj = 0, errmin = 0;
288	info->exaReq.majorversion = EXA_VERSION_MAJOR;
289	info->exaReq.minorversion = EXA_VERSION_MINOR;
290	if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL,
291			   &info->exaReq, &errmaj, &errmin)) {
292	    LoaderErrorMsg(NULL, "exa", errmaj, errmin);
293	    return FALSE;
294	}
295    }
296
297    return TRUE;
298}
299
300static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn)
301{
302    RADEONInfoPtr  info   = RADEONPTR(pScrn);
303    uint32_t cmd_stat;
304    int i;
305
306    info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo);
307    pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset);
308    if (!pScrn->chipset) {
309	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
310		   "ChipID 0x%04x is not recognized\n", info->Chipset);
311	return FALSE;
312    }
313
314    if (info->Chipset < 0) {
315	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
316		   "Chipset \"%s\" is not recognized\n", pScrn->chipset);
317	return FALSE;
318    }
319    xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
320	       "Chipset: \"%s\" (ChipID = 0x%04x)\n",
321	       pScrn->chipset,
322	       info->Chipset);
323
324    for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
325	if (info->Chipset == RADEONCards[i].pci_device_id) {
326	    RADEONCardInfo *card = &RADEONCards[i];
327	    info->ChipFamily = card->chip_family;
328	    info->IsMobility = card->mobility;
329	    info->IsIGP = card->igp;
330	    break;
331	}
332    }
333
334    info->cardType = CARD_PCI;
335
336    PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG);
337    if (cmd_stat & RADEON_CAP_LIST) {
338	uint32_t cap_ptr, cap_id;
339
340	PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
341	cap_ptr &= RADEON_CAP_PTR_MASK;
342
343	while(cap_ptr != RADEON_CAP_ID_NULL) {
344	    PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr);
345	    if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
346		info->cardType = CARD_AGP;
347		break;
348	    }
349	    if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
350		info->cardType = CARD_PCIE;
351		break;
352	    }
353	    cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
354	}
355    }
356
357
358    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n",
359	       (info->cardType==CARD_PCI) ? "PCI" :
360		(info->cardType==CARD_PCIE) ? "PCIE" : "AGP");
361
362    /* treat PCIE IGP cards as PCI */
363    if (info->cardType == CARD_PCIE && info->IsIGP)
364	info->cardType = CARD_PCI;
365
366    if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP)
367	info->cardType = CARD_PCIE;
368
369    /* not sure about gart table requirements */
370    if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP)
371	info->cardType = CARD_PCIE;
372
373#ifdef RENDER
374    info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL,
375					     info->Chipset != PCI_CHIP_RN50_515E &&
376					     info->Chipset != PCI_CHIP_RN50_5969);
377#endif
378    return TRUE;
379}
380
381static Bool radeon_alloc_dri(ScrnInfoPtr pScrn)
382{
383    RADEONInfoPtr  info   = RADEONPTR(pScrn);
384    if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) {
385	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n");
386	return FALSE;
387    }
388
389    if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) {
390	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n");
391	return FALSE;
392    }
393    return TRUE;
394}
395
396static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
397{
398    RADEONInfoPtr  info   = RADEONPTR(pScrn);
399    RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
400    struct pci_device *dev = info->PciInfo;
401    char *busid;
402    drmSetVersion sv;
403    int err;
404
405    if (pRADEONEnt->fd) {
406	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
407		   " reusing fd for second head\n");
408
409	info->dri2.drm_fd = pRADEONEnt->fd;
410	goto out;
411    }
412
413#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
414    XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d",
415                dev->domain, dev->bus, dev->dev, dev->func);
416#else
417    busid = XNFprintf("pci:%04x:%02x:%02x.%d",
418		      dev->domain, dev->bus, dev->dev, dev->func);
419#endif
420
421    info->dri2.drm_fd = drmOpen("radeon", busid);
422    if (info->dri2.drm_fd == -1) {
423
424	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
425		   "[drm] Failed to open DRM device for %s: %s\n",
426		   busid, strerror(errno));
427	free(busid);
428	return FALSE;
429    }
430    free(busid);
431
432    /* Check that what we opened was a master or a master-capable FD,
433     * by setting the version of the interface we'll use to talk to it.
434     * (see DRIOpenDRMMaster() in DRI1)
435     */
436    sv.drm_di_major = 1;
437    sv.drm_di_minor = 1;
438    sv.drm_dd_major = -1;
439    sv.drm_dd_minor = -1;
440    err = drmSetInterfaceVersion(info->dri2.drm_fd, &sv);
441    if (err != 0) {
442	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
443		   "[drm] failed to set drm interface version.\n");
444	drmClose(info->dri2.drm_fd);
445	info->dri2.drm_fd = -1;
446
447	return FALSE;
448    }
449
450    pRADEONEnt->fd = info->dri2.drm_fd;
451 out:
452    info->drmmode.fd = info->dri2.drm_fd;
453    info->dri->drmFD = info->dri2.drm_fd;
454    return TRUE;
455}
456
457static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
458{
459    RADEONInfoPtr  info   = RADEONPTR(pScrn);
460    struct drm_radeon_info ginfo;
461    int r;
462    uint32_t tmp;
463
464    if (info->ChipFamily < CHIP_FAMILY_R600)
465	return FALSE;
466
467#ifndef RADEON_INFO_TILING_CONFIG
468#define RADEON_INFO_TILING_CONFIG 0x6
469#endif
470
471    memset(&ginfo, 0, sizeof(ginfo));
472    ginfo.request = RADEON_INFO_TILING_CONFIG;
473    ginfo.value = (uintptr_t)&tmp;
474    r = drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_INFO, &ginfo, sizeof(ginfo));
475    if (r)
476	return FALSE;
477
478    info->tile_config = tmp;
479    info->r7xx_bank_op = 0;
480    if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
481	if (info->dri->pKernelDRMVersion->version_minor >= 7) {
482	    switch (info->tile_config & 0xf) {
483	    case 0:
484                info->num_channels = 1;
485                break;
486	    case 1:
487                info->num_channels = 2;
488                break;
489	    case 2:
490                info->num_channels = 4;
491                break;
492	    case 3:
493                info->num_channels = 8;
494                break;
495	    default:
496                return FALSE;
497	    }
498
499	    info->num_banks = (info->tile_config & 0xf0) >> 4;
500
501	    switch ((info->tile_config & 0xf00) >> 8) {
502	    case 0:
503                info->group_bytes = 256;
504                break;
505	    case 1:
506                info->group_bytes = 512;
507                break;
508	    default:
509                return FALSE;
510	    }
511	} else
512	    return FALSE;
513    } else {
514	switch((info->tile_config & 0xe) >> 1) {
515	case 0:
516	    info->num_channels = 1;
517	    break;
518	case 1:
519	    info->num_channels = 2;
520	    break;
521	case 2:
522	    info->num_channels = 4;
523	    break;
524	case 3:
525	    info->num_channels = 8;
526	    break;
527	default:
528	    return FALSE;
529	}
530	switch((info->tile_config & 0x30) >> 4) {
531	case 0:
532	    info->num_banks = 4;
533	    break;
534	case 1:
535	    info->num_banks = 8;
536	    break;
537	default:
538	    return FALSE;
539	}
540	switch((info->tile_config & 0xc0) >> 6) {
541	case 0:
542	    info->group_bytes = 256;
543	    break;
544	case 1:
545	    info->group_bytes = 512;
546	    break;
547	default:
548	    return FALSE;
549	}
550    }
551
552    info->have_tiling_info = TRUE;
553    return TRUE;
554}
555
556Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
557{
558    RADEONInfoPtr     info;
559    RADEONEntPtr pRADEONEnt;
560    DevUnion* pPriv;
561    Gamma  zeros = { 0.0, 0.0, 0.0 };
562    Bool colorTilingDefault;
563    uint32_t tiling = 0;
564    int cpp;
565
566    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
567		   "RADEONPreInit_KMS\n");
568    if (pScrn->numEntities != 1) return FALSE;
569    if (!RADEONGetRec(pScrn)) return FALSE;
570
571    info               = RADEONPTR(pScrn);
572    info->MMIO         = NULL;
573    info->IsSecondary  = FALSE;
574    info->IsPrimary = FALSE;
575    info->kms_enabled = TRUE;
576    info->pEnt         = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]);
577    if (info->pEnt->location.type != BUS_PCI) goto fail;
578
579    pPriv = xf86GetEntityPrivate(pScrn->entityList[0],
580				 getRADEONEntityIndex());
581    pRADEONEnt = pPriv->ptr;
582
583    if(xf86IsEntityShared(pScrn->entityList[0]))
584    {
585        if(xf86IsPrimInitDone(pScrn->entityList[0]))
586        {
587            info->IsSecondary = TRUE;
588            pRADEONEnt->pSecondaryScrn = pScrn;
589        }
590        else
591        {
592	    info->IsPrimary = TRUE;
593            xf86SetPrimInitDone(pScrn->entityList[0]);
594            pRADEONEnt->pPrimaryScrn = pScrn;
595            pRADEONEnt->HasSecondary = FALSE;
596        }
597    }
598
599    info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
600    pScrn->monitor     = pScrn->confScreen->monitor;
601
602    if (!RADEONPreInitVisual(pScrn))
603	goto fail;
604
605    xf86CollectOptions(pScrn, NULL);
606    if (!(info->Options = malloc(sizeof(RADEONOptions_KMS))))
607	goto fail;
608
609    memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS));
610    xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
611
612    if (!RADEONPreInitWeight(pScrn))
613	goto fail;
614
615    if (!RADEONPreInitChipType_KMS(pScrn))
616        goto fail;
617
618    if (!radeon_alloc_dri(pScrn))
619	return FALSE;
620
621    if (radeon_open_drm_master(pScrn) == FALSE) {
622	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
623	goto fail;
624    }
625
626    info->dri2.enabled = FALSE;
627    info->dri->pKernelDRMVersion = drmGetVersion(info->dri->drmFD);
628    if (info->dri->pKernelDRMVersion == NULL) {
629	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
630		   "RADEONDRIGetVersion failed to get the DRM version\n");
631	goto fail;
632    }
633
634    if (!RADEONPreInitAccel_KMS(pScrn))              goto fail;
635
636    /* don't enable tiling if accel is not enabled */
637    if (!info->r600_shadow_fb) {
638	colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
639	    info->ChipFamily <= CHIP_FAMILY_RS740;
640
641	if (info->ChipFamily >= CHIP_FAMILY_R600) {
642	    /* set default group bytes, overridden by kernel info below */
643	    info->group_bytes = 256;
644	    info->have_tiling_info = FALSE;
645	    if (info->dri->pKernelDRMVersion->version_minor >= 6) {
646		if (r600_get_tile_config(pScrn))
647		    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
648								  OPTION_COLOR_TILING, colorTilingDefault);
649		else
650		    info->allowColorTiling = FALSE;
651	    } else
652		xf86DrvMsg(pScrn->scrnIndex, X_INFO,
653			   "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n");
654
655	    /* don't support tiling on APUs yet */
656	    if (info->ChipFamily == CHIP_FAMILY_PALM)
657		info->allowColorTiling = FALSE;
658	} else
659	    info->allowColorTiling = xf86ReturnOptValBool(info->Options,
660							  OPTION_COLOR_TILING, colorTilingDefault);
661    } else
662	info->allowColorTiling = FALSE;
663
664    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
665	 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
666
667    if (info->dri->pKernelDRMVersion->version_minor >= 8) {
668	info->allowPageFlip = xf86ReturnOptValBool(info->Options,
669						   OPTION_PAGE_FLIP, TRUE);
670	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
671		   "KMS Pageflipping: %sabled\n", info->allowPageFlip ? "en" : "dis");
672    }
673
674    info->swapBuffersWait = xf86ReturnOptValBool(info->Options,
675						 OPTION_SWAPBUFFERS_WAIT, TRUE);
676    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
677	       "SwapBuffers wait for vsync: %sabled\n", info->swapBuffersWait ? "en" : "dis");
678
679    if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) {
680	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n");
681	goto fail;
682    }
683
684    if (info->drmmode.mode_res->count_crtcs == 1)
685        pRADEONEnt->HasCRTC2 = FALSE;
686    else
687        pRADEONEnt->HasCRTC2 = TRUE;
688
689
690    /* fix up cloning on rn50 cards
691     * since they only have one crtc sometimes the xserver doesn't assign
692     * a crtc to one of the outputs even though both outputs have common modes
693     * which results in only one monitor being enabled.  Assign a crtc here so
694     * that both outputs light up.
695     */
696    if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
697	xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
698	int i;
699
700	for (i = 0; i < xf86_config->num_output; i++) {
701	    xf86OutputPtr output = xf86_config->output[i];
702
703	    /* XXX: double check crtc mode */
704	    if ((output->probed_modes != NULL) && (output->crtc == NULL))
705		output->crtc = xf86_config->crtc[0];
706	}
707    }
708
709    {
710	struct drm_radeon_gem_info mminfo;
711
712	if (!drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
713	{
714	    info->vram_size = mminfo.vram_visible;
715	    info->gart_size = mminfo.gart_size;
716	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
717		       "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n",
718		       (unsigned long long)mminfo.gart_size,
719		       (unsigned long long)mminfo.vram_size,
720		       (unsigned long long)mminfo.vram_visible);
721	}
722    }
723
724    info->exa_pixmaps = xf86ReturnOptValBool(info->Options,
725                                             OPTION_EXA_PIXMAPS,
726					     ((info->vram_size > (32 * 1024 * 1024) &&
727					      info->RenderAccel)));
728    if (info->exa_pixmaps)
729    	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
730		"EXA: Driver will allow EXA pixmaps in VRAM\n");
731    else
732    	xf86DrvMsg(pScrn->scrnIndex, X_INFO,
733		"EXA: Driver will not allow EXA pixmaps in VRAM\n");
734
735    /* no tiled scanout on r6xx+ yet */
736    if (info->allowColorTiling) {
737	if (info->ChipFamily >= CHIP_FAMILY_R600)
738	    tiling |= RADEON_TILING_MICRO;
739	else
740	    tiling |= RADEON_TILING_MACRO;
741    }
742    cpp = pScrn->bitsPerPixel / 8;
743    pScrn->displayWidth =
744	RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling));
745    info->CurrentLayout.displayWidth = pScrn->displayWidth;
746
747    /* Set display resolution */
748    xf86SetDpi(pScrn, 0, 0);
749
750	/* Get ScreenInit function */
751    if (!xf86LoadSubModule(pScrn, "fb")) return FALSE;
752
753    if (!xf86SetGamma(pScrn, zeros)) return FALSE;
754
755    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
756	if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
757    }
758
759    if (pScrn->modes == NULL) {
760      xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
761      goto fail;
762   }
763
764    return TRUE;
765 fail:
766    RADEONFreeRec(pScrn);
767    return FALSE;
768
769}
770
771static Bool RADEONCursorInit_KMS(ScreenPtr pScreen)
772{
773    return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
774			      (HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
775			       HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
776			       HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
777			       HARDWARE_CURSOR_UPDATE_UNHIDDEN |
778			       HARDWARE_CURSOR_ARGB));
779}
780
781static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode)
782{
783    ScrnInfoPtr  pScrn = xf86Screens[pScreen->myNum];
784    Bool         unblank;
785
786    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
787		   "RADEONSaveScreen(%d)\n", mode);
788
789    unblank = xf86IsUnblank(mode);
790    if (unblank) SetTimeSinceLastInputEvent();
791
792    if ((pScrn != NULL) && pScrn->vtSema) {
793	if (unblank)
794	    RADEONUnblank(pScrn);
795	else
796	    RADEONBlank(pScrn);
797    }
798    return TRUE;
799}
800
801/* Called at the end of each server generation.  Restore the original
802 * text mode, unmap video memory, and unwrap and call the saved
803 * CloseScreen function.
804 */
805static Bool RADEONCloseScreen_KMS(int scrnIndex, ScreenPtr pScreen)
806{
807    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
808    RADEONInfoPtr  info  = RADEONPTR(pScrn);
809
810    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
811		   "RADEONCloseScreen\n");
812
813    drmmode_uevent_fini(pScrn, &info->drmmode);
814    if (info->cs)
815      radeon_cs_flush_indirect(pScrn);
816
817    DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn);
818
819    if (info->accel_state->exa) {
820	exaDriverFini(pScreen);
821	free(info->accel_state->exa);
822	info->accel_state->exa = NULL;
823    }
824
825    if (info->accel_state->use_vbos)
826        radeon_vbo_free_lists(pScrn);
827
828    drmDropMaster(info->dri->drmFD);
829
830    if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
831    info->cursor = NULL;
832
833    radeon_dri2_close_screen(pScreen);
834
835    pScrn->vtSema = FALSE;
836    xf86ClearPrimInitDone(info->pEnt->index);
837    pScreen->BlockHandler = info->BlockHandler;
838    pScreen->CloseScreen = info->CloseScreen;
839    return (*pScreen->CloseScreen)(scrnIndex, pScreen);
840}
841
842
843void RADEONFreeScreen_KMS(int scrnIndex, int flags)
844{
845    ScrnInfoPtr  pScrn = xf86Screens[scrnIndex];
846    RADEONInfoPtr  info  = RADEONPTR(pScrn);
847
848    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
849		   "RADEONFreeScreen\n");
850
851    /* when server quits at PreInit, we don't need do this anymore*/
852    if (!info) return;
853
854    RADEONFreeRec(pScrn);
855}
856
857Bool RADEONScreenInit_KMS(int scrnIndex, ScreenPtr pScreen,
858			  int argc, char **argv)
859{
860    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
861    RADEONInfoPtr  info  = RADEONPTR(pScrn);
862    int            subPixelOrder = SubPixelUnknown;
863    char*          s;
864    void *front_ptr;
865    int ret;
866
867    pScrn->fbOffset = 0;
868
869    miClearVisualTypes();
870    if (!miSetVisualTypes(pScrn->depth,
871			  miGetDefaultVisualMask(pScrn->depth),
872			  pScrn->rgbBits,
873			  pScrn->defaultVisual)) return FALSE;
874    miSetPixmapDepths ();
875
876    ret = drmSetMaster(info->dri->drmFD);
877    if (ret) {
878        ErrorF("Unable to retrieve master\n");
879        return FALSE;
880    }
881    info->directRenderingEnabled = FALSE;
882    if (info->r600_shadow_fb == FALSE)
883        info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
884
885    front_ptr = info->FB;
886
887    if (!info->bufmgr)
888        info->bufmgr = radeon_bo_manager_gem_ctor(info->dri->drmFD);
889    if (!info->bufmgr) {
890	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
891		   "failed to initialise GEM buffer manager");
892	return FALSE;
893    }
894    drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr);
895
896    if (!info->csm)
897        info->csm = radeon_cs_manager_gem_ctor(info->dri->drmFD);
898    if (!info->csm) {
899	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
900		   "failed to initialise command submission manager");
901	return FALSE;
902    }
903
904    if (!info->cs)
905        info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4);
906    if (!info->cs) {
907	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
908		   "failed to initialise command submission buffer");
909	return FALSE;
910    }
911
912    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size);
913    radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn);
914
915    radeon_setup_kernel_mem(pScreen);
916    front_ptr = info->front_bo->ptr;
917
918    if (info->r600_shadow_fb) {
919	info->fb_shadow = calloc(1,
920				 pScrn->displayWidth * pScrn->virtualY *
921				 ((pScrn->bitsPerPixel + 7) >> 3));
922	if (info->fb_shadow == NULL) {
923	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
924                       "Failed to allocate shadow framebuffer\n");
925	    info->r600_shadow_fb = FALSE;
926	} else {
927	    if (!fbScreenInit(pScreen, info->fb_shadow,
928			      pScrn->virtualX, pScrn->virtualY,
929			      pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
930			      pScrn->bitsPerPixel))
931		return FALSE;
932	}
933    }
934
935    if (info->r600_shadow_fb == FALSE) {
936	/* Init fb layer */
937	if (!fbScreenInit(pScreen, front_ptr,
938			  pScrn->virtualX, pScrn->virtualY,
939			  pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth,
940			  pScrn->bitsPerPixel))
941	    return FALSE;
942    }
943
944    xf86SetBlackWhitePixels(pScreen);
945
946    if (pScrn->bitsPerPixel > 8) {
947	VisualPtr  visual;
948
949	visual = pScreen->visuals + pScreen->numVisuals;
950	while (--visual >= pScreen->visuals) {
951	    if ((visual->class | DynamicClass) == DirectColor) {
952		visual->offsetRed   = pScrn->offset.red;
953		visual->offsetGreen = pScrn->offset.green;
954		visual->offsetBlue  = pScrn->offset.blue;
955		visual->redMask     = pScrn->mask.red;
956		visual->greenMask   = pScrn->mask.green;
957		visual->blueMask    = pScrn->mask.blue;
958	    }
959	}
960    }
961
962    /* Must be after RGB order fixed */
963    fbPictureInit (pScreen, 0, 0);
964
965#ifdef RENDER
966    if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) {
967	if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB;
968	else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
969	else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
970	PictureSetSubpixelOrder (pScreen, subPixelOrder);
971    }
972#endif
973
974    pScrn->vtSema = TRUE;
975    /* Backing store setup */
976    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
977		   "Initializing backing store\n");
978    miInitializeBackingStore(pScreen);
979    xf86SetBackingStore(pScreen);
980
981
982    if (info->directRenderingEnabled) {
983	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
984    } else {
985	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
986		   "Direct rendering disabled\n");
987    }
988
989    if (info->r600_shadow_fb) {
990	xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
991	info->accelOn = FALSE;
992    } else {
993	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
994		       "Initializing Acceleration\n");
995	if (RADEONAccelInit(pScreen)) {
996	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
997	    info->accelOn = TRUE;
998	} else {
999	    xf86DrvMsg(scrnIndex, X_ERROR,
1000		       "Acceleration initialization failed\n");
1001	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
1002	    info->accelOn = FALSE;
1003	}
1004    }
1005
1006    /* Init DPMS */
1007    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1008		   "Initializing DPMS\n");
1009    xf86DPMSInit(pScreen, xf86DPMSSet, 0);
1010
1011    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1012		   "Initializing Cursor\n");
1013
1014    /* Set Silken Mouse */
1015    xf86SetSilkenMouse(pScreen);
1016
1017    /* Cursor setup */
1018    miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
1019
1020    if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
1021	if (RADEONCursorInit_KMS(pScreen)) {
1022	}
1023    }
1024
1025    /* DGA setup */
1026#ifdef XFreeXDGA
1027    /* DGA is dangerous on kms as the base and framebuffer location may change:
1028     * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html
1029     */
1030    /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */
1031#endif
1032    if (info->r600_shadow_fb == FALSE) {
1033        /* Init Xv */
1034        xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1035                       "Initializing Xv\n");
1036        RADEONInitVideo(pScreen);
1037    }
1038
1039    if (info->r600_shadow_fb == TRUE) {
1040        if (!shadowSetup(pScreen)) {
1041	    xf86DrvMsg(scrnIndex, X_ERROR,
1042		       "Shadowfb initialization failed\n");
1043            return FALSE;
1044        }
1045    }
1046    pScrn->pScreen = pScreen;
1047
1048    /* Provide SaveScreen & wrap BlockHandler and CloseScreen */
1049    /* Wrap CloseScreen */
1050    info->CloseScreen    = pScreen->CloseScreen;
1051    pScreen->CloseScreen = RADEONCloseScreen_KMS;
1052    pScreen->SaveScreen  = RADEONSaveScreen_KMS;
1053    info->BlockHandler = pScreen->BlockHandler;
1054    pScreen->BlockHandler = RADEONBlockHandler_KMS;
1055
1056    if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn))
1057        return FALSE;
1058
1059    info->CreateScreenResources = pScreen->CreateScreenResources;
1060    pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS;
1061
1062   if (!xf86CrtcScreenInit (pScreen))
1063       return FALSE;
1064
1065   /* Wrap pointer motion to flip touch screen around */
1066//    info->PointerMoved = pScrn->PointerMoved;
1067//    pScrn->PointerMoved = RADEONPointerMoved;
1068
1069    if (!drmmode_setup_colormap(pScreen, pScrn))
1070	return FALSE;
1071
1072   /* Note unused options */
1073    if (serverGeneration == 1)
1074	xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options);
1075
1076    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1077		   "RADEONScreenInit finished\n");
1078
1079    info->accel_state->XInited3D = FALSE;
1080    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1081
1082    return TRUE;
1083}
1084
1085Bool RADEONEnterVT_KMS(int scrnIndex, int flags)
1086{
1087    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
1088    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1089    int ret;
1090
1091    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1092		   "RADEONEnterVT_KMS\n");
1093
1094
1095    ret = drmSetMaster(info->dri->drmFD);
1096    if (ret)
1097	ErrorF("Unable to retrieve master\n");
1098    info->accel_state->XInited3D = FALSE;
1099    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1100
1101    pScrn->vtSema = TRUE;
1102
1103    if (!drmmode_set_desired_modes(pScrn, &info->drmmode))
1104	return FALSE;
1105
1106    if (info->adaptor)
1107	RADEONResetVideo(pScrn);
1108
1109    return TRUE;
1110}
1111
1112
1113void RADEONLeaveVT_KMS(int scrnIndex, int flags)
1114{
1115    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
1116    RADEONInfoPtr  info  = RADEONPTR(pScrn);
1117
1118    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1119		   "RADEONLeaveVT_KMS\n");
1120
1121    drmDropMaster(info->dri->drmFD);
1122
1123#ifdef HAVE_FREE_SHADOW
1124    xf86RotateFreeShadow(pScrn);
1125#endif
1126
1127    xf86_hide_cursors (pScrn);
1128    info->accel_state->XInited3D = FALSE;
1129    info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
1130
1131    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
1132		   "Ok, leaving now...\n");
1133}
1134
1135
1136Bool RADEONSwitchMode_KMS(int scrnIndex, DisplayModePtr mode, int flags)
1137{
1138    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
1139    Bool ret;
1140    ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
1141    return ret;
1142
1143}
1144
1145void RADEONAdjustFrame_KMS(int scrnIndex, int x, int y, int flags)
1146{
1147    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
1148    RADEONInfoPtr  info        = RADEONPTR(pScrn);
1149    drmmode_adjust_frame(pScrn, &info->drmmode, x, y, flags);
1150    return;
1151}
1152
1153static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
1154{
1155    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
1156    RADEONInfoPtr info = RADEONPTR(pScrn);
1157    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1158    int cpp = info->CurrentLayout.pixel_bytes;
1159    int screen_size;
1160    int pitch, base_align;
1161    int total_size_bytes = 0, remain_size_bytes;
1162    uint32_t tiling_flags = 0;
1163
1164    if (info->accel_state->exa != NULL) {
1165	xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n");
1166	return FALSE;
1167    }
1168    if (info->r600_shadow_fb == FALSE) {
1169        info->accel_state->exa = exaDriverAlloc();
1170        if (info->accel_state->exa == NULL)
1171	    return FALSE;
1172    }
1173
1174    if (info->allowColorTiling) {
1175	if (info->ChipFamily >= CHIP_FAMILY_R600)
1176	    tiling_flags |= RADEON_TILING_MICRO;
1177	else
1178	    tiling_flags |= RADEON_TILING_MACRO;
1179    }
1180    pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
1181    screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
1182    base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
1183    {
1184	int cursor_size = 64 * 4 * 64;
1185	int c;
1186
1187	cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE);
1188	for (c = 0; c < xf86_config->num_crtc; c++) {
1189	    /* cursor objects */
1190            if (info->cursor_bo[c] == NULL) {
1191                info->cursor_bo[c] = radeon_bo_open(info->bufmgr, 0,
1192                                                    cursor_size, 0,
1193                                                    RADEON_GEM_DOMAIN_VRAM, 0);
1194                if (!info->cursor_bo[c]) {
1195                    return FALSE;
1196                }
1197
1198                if (radeon_bo_map(info->cursor_bo[c], 1)) {
1199                    ErrorF("Failed to map cursor buffer memory\n");
1200                }
1201
1202                drmmode_set_cursor(pScrn, &info->drmmode, c, info->cursor_bo[c]);
1203                total_size_bytes += cursor_size;
1204            }
1205        }
1206    }
1207
1208    screen_size = RADEON_ALIGN(screen_size, RADEON_GPU_PAGE_SIZE);
1209    /* keep area front front buffer - but don't allocate it yet */
1210    total_size_bytes += screen_size;
1211
1212    /* work out from the mm size what the exa / tex sizes need to be */
1213    remain_size_bytes = info->vram_size - total_size_bytes;
1214
1215    info->dri->textureSize = 0;
1216
1217    if (info->front_bo == NULL) {
1218        info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size,
1219                                        base_align, RADEON_GEM_DOMAIN_VRAM, 0);
1220        if (info->r600_shadow_fb == TRUE) {
1221            if (radeon_bo_map(info->front_bo, 1)) {
1222                ErrorF("Failed to map cursor buffer memory\n");
1223            }
1224        }
1225#if X_BYTE_ORDER == X_BIG_ENDIAN
1226	switch (cpp) {
1227	case 4:
1228	    tiling_flags |= RADEON_TILING_SWAP_32BIT;
1229	    break;
1230	case 2:
1231	    tiling_flags |= RADEON_TILING_SWAP_16BIT;
1232	    break;
1233	}
1234#endif
1235	if (tiling_flags)
1236            radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
1237    }
1238
1239    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", info->front_bo->size/1024);
1240    radeon_kms_update_vram_limit(pScrn, screen_size);
1241    return TRUE;
1242}
1243
1244void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size)
1245{
1246    xf86CrtcConfigPtr   xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
1247    RADEONInfoPtr info = RADEONPTR(pScrn);
1248    int remain_size_bytes;
1249    int total_size_bytes;
1250    int c;
1251
1252    for (c = 0; c < xf86_config->num_crtc; c++) {
1253	if (info->cursor_bo[c] != NULL) {
1254	    total_size_bytes += (64 * 4 * 64);
1255	}
1256    }
1257
1258    total_size_bytes += new_fb_size;
1259    remain_size_bytes = info->vram_size - new_fb_size;
1260    remain_size_bytes = (remain_size_bytes / 10) * 9;
1261    radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, remain_size_bytes);
1262
1263    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %dK\n", remain_size_bytes / 1024);
1264}
1265
1266
1267#endif
1268