1#ifdef HAVE_CONFIG_H 2#include "config.h" 3#endif 4 5#include <unistd.h> 6#include "xf86.h" 7#include "generic_bus.h" 8#include "theatre.h" 9#include "theatre_reg.h" 10 11#undef read 12#undef write 13#undef ioctl 14 15static Bool theatre_read(TheatrePtr t,uint32_t reg, uint32_t *data) 16{ 17 if(t->theatre_num<0)return FALSE; 18 return t->VIP->read(t->VIP, ((t->theatre_num & 0x3)<<14) | reg,4, (uint8_t *) data); 19} 20 21static Bool theatre_write(TheatrePtr t,uint32_t reg, uint32_t data) 22{ 23 if(t->theatre_num<0)return FALSE; 24 return t->VIP->write(t->VIP,((t->theatre_num & 0x03)<<14) | reg,4, (uint8_t *) &data); 25} 26 27#define RT_regr(reg,data) theatre_read(t,(reg),(data)) 28#define RT_regw(reg,data) theatre_write(t,(reg),(data)) 29#define VIP_TYPE "ATI VIP BUS" 30 31static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard); 32static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector); 33 34#if 0 35TheatrePtr DetectTheatre(GENERIC_BUS_Ptr b) 36{ 37 TheatrePtr t; 38 uint32_t i; 39 uint32_t val; 40 char s[20]; 41 42 b->ioctl(b,GB_IOCTL_GET_TYPE,20,s); 43 if(strcmp(VIP_TYPE, s)){ 44 xf86DrvMsg(b->scrnIndex, X_ERROR, "DetectTheatre must be called with bus of type \"%s\", not \"%s\"\n", 45 VIP_TYPE, s); 46 return NULL; 47 } 48 49 t = calloc(1,sizeof(TheatreRec)); 50 t->VIP = b; 51 t->theatre_num = -1; 52 t->mode=MODE_UNINITIALIZED; 53 54 b->read(b, VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val); 55 for(i=0;i<4;i++) 56 { 57 if(b->read(b, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (uint8_t *)&val)) 58 { 59 if(val)xf86DrvMsg(b->scrnIndex, X_INFO, "Device %d on VIP bus ids as 0x%08x\n",i,val); 60 if(t->theatre_num>=0)continue; /* already found one instance */ 61 switch(val){ 62 case RT100_ATI_ID: 63 t->theatre_num=i; 64 t->theatre_id=RT100_ATI_ID; 65 break; 66 case RT200_ATI_ID: 67 t->theatre_num=i; 68 t->theatre_id=RT200_ATI_ID; 69 break; 70 } 71 } else { 72 xf86DrvMsg(b->scrnIndex, X_INFO, "No response from device %d on VIP bus\n",i); 73 } 74 } 75 if(t->theatre_num>=0)xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre as device %d on VIP bus with id 0x%08x\n",t->theatre_num,t->theatre_id); 76 77 if(t->theatre_id==RT200_ATI_ID){ 78 xf86DrvMsg(b->scrnIndex, X_INFO, "Rage Theatre 200 is not supported yet\n"); 79 t->theatre_num=-1; 80 } 81 82 if(t->theatre_num < 0) 83 { 84 free(t); 85 return NULL; 86 } 87 88 RT_regr(VIP_VIP_REVISION_ID, &val); 89 xf86DrvMsg(b->scrnIndex, X_INFO, "Detected Rage Theatre revision %8.8X\n", val); 90 91#if 0 92DumpRageTheatreRegsByName(t); 93#endif 94 return t; 95} 96#endif 97 98enum 99{ 100fld_tmpReg1=0, 101fld_tmpReg2, 102fld_tmpReg3, 103fld_LP_CONTRAST, 104fld_LP_BRIGHTNESS, 105fld_CP_HUE_CNTL, 106fld_LUMA_FILTER, 107fld_H_SCALE_RATIO, 108fld_H_SHARPNESS, 109fld_V_SCALE_RATIO, 110fld_V_DEINTERLACE_ON, 111fld_V_BYPSS, 112fld_V_DITHER_ON, 113fld_EVENF_OFFSET, 114fld_ODDF_OFFSET, 115fld_INTERLACE_DETECTED, 116fld_VS_LINE_COUNT, 117fld_VS_DETECTED_LINES, 118fld_VS_ITU656_VB, 119fld_VBI_CC_DATA, 120fld_VBI_CC_WT, 121fld_VBI_CC_WT_ACK, 122fld_VBI_CC_HOLD, 123fld_VBI_DECODE_EN, 124fld_VBI_CC_DTO_P, 125fld_VBI_20BIT_DTO_P, 126fld_VBI_CC_LEVEL, 127fld_VBI_20BIT_LEVEL, 128fld_VBI_CLK_RUNIN_GAIN, 129fld_H_VBI_WIND_START, 130fld_H_VBI_WIND_END, 131fld_V_VBI_WIND_START, 132fld_V_VBI_WIND_END, 133fld_VBI_20BIT_DATA0, 134fld_VBI_20BIT_DATA1, 135fld_VBI_20BIT_WT, 136fld_VBI_20BIT_WT_ACK, 137fld_VBI_20BIT_HOLD, 138fld_VBI_CAPTURE_ENABLE, 139fld_VBI_EDS_DATA, 140fld_VBI_EDS_WT, 141fld_VBI_EDS_WT_ACK, 142fld_VBI_EDS_HOLD, 143fld_VBI_SCALING_RATIO, 144fld_VBI_ALIGNER_ENABLE, 145fld_H_ACTIVE_START, 146fld_H_ACTIVE_END, 147fld_V_ACTIVE_START, 148fld_V_ACTIVE_END, 149fld_CH_HEIGHT, 150fld_CH_KILL_LEVEL, 151fld_CH_AGC_ERROR_LIM, 152fld_CH_AGC_FILTER_EN, 153fld_CH_AGC_LOOP_SPEED, 154fld_HUE_ADJ, 155fld_STANDARD_SEL, 156fld_STANDARD_YC, 157fld_ADC_PDWN, 158fld_INPUT_SELECT, 159fld_ADC_PREFLO, 160fld_H_SYNC_PULSE_WIDTH, 161fld_HS_GENLOCKED, 162fld_HS_SYNC_IN_WIN, 163fld_VIN_ASYNC_RST, 164fld_DVS_ASYNC_RST, 165fld_VIP_VENDOR_ID, 166fld_VIP_DEVICE_ID, 167fld_VIP_REVISION_ID, 168fld_BLACK_INT_START, 169fld_BLACK_INT_LENGTH, 170fld_UV_INT_START, 171fld_U_INT_LENGTH, 172fld_V_INT_LENGTH, 173fld_CRDR_ACTIVE_GAIN, 174fld_CBDB_ACTIVE_GAIN, 175fld_DVS_DIRECTION, 176fld_DVS_VBI_UINT8_SWAP, 177fld_DVS_CLK_SELECT, 178fld_CONTINUOUS_STREAM, 179fld_DVSOUT_CLK_DRV, 180fld_DVSOUT_DATA_DRV, 181fld_COMB_CNTL0, 182fld_COMB_CNTL1, 183fld_COMB_CNTL2, 184fld_COMB_LENGTH, 185fld_SYNCTIP_REF0, 186fld_SYNCTIP_REF1, 187fld_CLAMP_REF, 188fld_AGC_PEAKWHITE, 189fld_VBI_PEAKWHITE, 190fld_WPA_THRESHOLD, 191fld_WPA_TRIGGER_LO, 192fld_WPA_TRIGGER_HIGH, 193fld_LOCKOUT_START, 194fld_LOCKOUT_END, 195fld_CH_DTO_INC, 196fld_PLL_SGAIN, 197fld_PLL_FGAIN, 198fld_CR_BURST_GAIN, 199fld_CB_BURST_GAIN, 200fld_VERT_LOCKOUT_START, 201fld_VERT_LOCKOUT_END, 202fld_H_IN_WIND_START, 203fld_V_IN_WIND_START, 204fld_H_OUT_WIND_WIDTH, 205fld_V_OUT_WIND_WIDTH, 206fld_HS_LINE_TOTAL, 207fld_MIN_PULSE_WIDTH, 208fld_MAX_PULSE_WIDTH, 209fld_WIN_CLOSE_LIMIT, 210fld_WIN_OPEN_LIMIT, 211fld_VSYNC_INT_TRIGGER, 212fld_VSYNC_INT_HOLD, 213fld_VIN_M0, 214fld_VIN_N0, 215fld_MNFLIP_EN, 216fld_VIN_P, 217fld_REG_CLK_SEL, 218fld_VIN_M1, 219fld_VIN_N1, 220fld_VIN_DRIVER_SEL, 221fld_VIN_MNFLIP_REQ, 222fld_VIN_MNFLIP_DONE, 223fld_TV_LOCK_TO_VIN, 224fld_TV_P_FOR_WINCLK, 225fld_VINRST, 226fld_VIN_CLK_SEL, 227fld_VS_FIELD_BLANK_START, 228fld_VS_FIELD_BLANK_END, 229fld_VS_FIELD_IDLOCATION, 230fld_VS_FRAME_TOTAL, 231fld_SYNC_TIP_START, 232fld_SYNC_TIP_LENGTH, 233fld_GAIN_FORCE_DATA, 234fld_GAIN_FORCE_EN, 235fld_I_CLAMP_SEL, 236fld_I_AGC_SEL, 237fld_EXT_CLAMP_CAP, 238fld_EXT_AGC_CAP, 239fld_DECI_DITHER_EN, 240fld_ADC_PREFHI, 241fld_ADC_CH_GAIN_SEL, 242fld_HS_PLL_SGAIN, 243fld_NREn, 244fld_NRGainCntl, 245fld_NRBWTresh, 246fld_NRGCTresh, 247fld_NRCoefDespeclMode, 248fld_GPIO_5_OE, 249fld_GPIO_6_OE, 250fld_GPIO_5_OUT, 251fld_GPIO_6_OUT, 252 253regRT_MAX_REGS 254} a; 255 256 257typedef struct { 258 uint8_t size; 259 uint32_t fld_id; 260 uint32_t dwRegAddrLSBs; 261 uint32_t dwFldOffsetLSBs; 262 uint32_t dwMaskLSBs; 263 uint32_t addr2; 264 uint32_t offs2; 265 uint32_t mask2; 266 uint32_t dwCurrValue; 267 uint32_t rw; 268} RTREGMAP; 269 270#define READONLY 1 271#define WRITEONLY 2 272#define READWRITE 3 273 274/* Rage Theatre's Register Mappings, including the default values: */ 275RTREGMAP RT_RegMap[regRT_MAX_REGS]={ 276/* 277{size, fidname, AddrOfst, Ofst, Mask, Addr, Ofst, Mask, Cur, R/W 278*/ 279{32 , fld_tmpReg1 ,0x151 , 0, 0x0, 0, 0,0, 0,READWRITE }, 280{1 , fld_tmpReg2 ,VIP_VIP_SUB_VENDOR_DEVICE_ID , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, 281{1 , fld_tmpReg3 ,VIP_VIP_COMMAND_STATUS , 3, 0xFFFFFFFF, 0, 0,0, 0,READWRITE }, 282{8 , fld_LP_CONTRAST ,VIP_LP_CONTRAST , 0, 0xFFFFFF00, 0, 0,0, fld_LP_CONTRAST_def ,READWRITE }, 283{14 , fld_LP_BRIGHTNESS ,VIP_LP_BRIGHTNESS , 0, 0xFFFFC000, 0, 0,0, fld_LP_BRIGHTNESS_def ,READWRITE }, 284{8 , fld_CP_HUE_CNTL ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CP_HUE_CNTL_def ,READWRITE }, 285{1 , fld_LUMA_FILTER ,VIP_LP_BRIGHTNESS , 15, 0xFFFF7FFF, 0, 0,0, fld_LUMA_FILTER_def ,READWRITE }, 286{21 , fld_H_SCALE_RATIO ,VIP_H_SCALER_CONTROL , 0, 0xFFE00000, 0, 0,0, fld_H_SCALE_RATIO_def ,READWRITE }, 287{4 , fld_H_SHARPNESS ,VIP_H_SCALER_CONTROL , 25, 0xE1FFFFFF, 0, 0,0, fld_H_SHARPNESS_def ,READWRITE }, 288{12 , fld_V_SCALE_RATIO ,VIP_V_SCALER_CONTROL , 0, 0xFFFFF000, 0, 0,0, fld_V_SCALE_RATIO_def ,READWRITE }, 289{1 , fld_V_DEINTERLACE_ON,VIP_V_SCALER_CONTROL , 12, 0xFFFFEFFF, 0, 0,0, fld_V_DEINTERLACE_ON_def ,READWRITE }, 290{1 , fld_V_BYPSS ,VIP_V_SCALER_CONTROL , 14, 0xFFFFBFFF, 0, 0,0, fld_V_BYPSS_def ,READWRITE }, 291{1 , fld_V_DITHER_ON ,VIP_V_SCALER_CONTROL , 15, 0xFFFF7FFF, 0, 0,0, fld_V_DITHER_ON_def ,READWRITE }, 292{11 , fld_EVENF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 0, 0xFFFFF800, 0, 0,0, fld_EVENF_OFFSET_def ,READWRITE }, 293{11 , fld_ODDF_OFFSET ,VIP_V_DEINTERLACE_CONTROL , 11, 0xFFC007FF, 0, 0,0, fld_ODDF_OFFSET_def ,READWRITE }, 294{1 , fld_INTERLACE_DETECTED ,VIP_VS_LINE_COUNT , 15, 0xFFFF7FFF, 0, 0,0, fld_INTERLACE_DETECTED_def,READONLY }, 295{10 , fld_VS_LINE_COUNT ,VIP_VS_LINE_COUNT , 0, 0xFFFFFC00, 0, 0,0, fld_VS_LINE_COUNT_def ,READONLY }, 296{10 , fld_VS_DETECTED_LINES ,VIP_VS_LINE_COUNT , 16, 0xFC00FFFF, 0, 0,0, fld_VS_DETECTED_LINES_def ,READONLY }, 297{1 , fld_VS_ITU656_VB ,VIP_VS_LINE_COUNT , 13, 0xFFFFDFFF, 0, 0,0, fld_VS_ITU656_VB_def ,READONLY }, 298{16 , fld_VBI_CC_DATA ,VIP_VBI_CC_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DATA_def ,READWRITE }, 299{1 , fld_VBI_CC_WT ,VIP_VBI_CC_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_CC_WT_def ,READWRITE }, 300{1 , fld_VBI_CC_WT_ACK ,VIP_VBI_CC_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_CC_WT_ACK_def ,READONLY }, 301{1 , fld_VBI_CC_HOLD ,VIP_VBI_CC_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_CC_HOLD_def ,READWRITE }, 302{1 , fld_VBI_DECODE_EN ,VIP_VBI_CC_CNTL , 31, 0x7FFFFFFF, 0, 0,0, fld_VBI_DECODE_EN_def ,READWRITE }, 303{16 , fld_VBI_CC_DTO_P ,VIP_VBI_DTO_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_CC_DTO_P_def ,READWRITE }, 304{16 ,fld_VBI_20BIT_DTO_P,VIP_VBI_DTO_CNTL , 16, 0x0000FFFF, 0, 0,0, fld_VBI_20BIT_DTO_P_def ,READWRITE }, 305{7 ,fld_VBI_CC_LEVEL ,VIP_VBI_LEVEL_CNTL , 0, 0xFFFFFF80, 0, 0,0, fld_VBI_CC_LEVEL_def ,READWRITE }, 306{7 ,fld_VBI_20BIT_LEVEL,VIP_VBI_LEVEL_CNTL , 8, 0xFFFF80FF, 0, 0,0, fld_VBI_20BIT_LEVEL_def ,READWRITE }, 307{9 ,fld_VBI_CLK_RUNIN_GAIN,VIP_VBI_LEVEL_CNTL , 16, 0xFE00FFFF, 0, 0,0, fld_VBI_CLK_RUNIN_GAIN_def,READWRITE }, 308{11 ,fld_H_VBI_WIND_START,VIP_H_VBI_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_VBI_WIND_START_def ,READWRITE }, 309{11 ,fld_H_VBI_WIND_END,VIP_H_VBI_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_VBI_WIND_END_def ,READWRITE }, 310{10 ,fld_V_VBI_WIND_START,VIP_V_VBI_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_VBI_WIND_START_def ,READWRITE }, 311{10 ,fld_V_VBI_WIND_END,VIP_V_VBI_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_VBI_WIND_END_def ,READWRITE }, /* CHK */ 312{16 ,fld_VBI_20BIT_DATA0,VIP_VBI_20BIT_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_20BIT_DATA0_def ,READWRITE }, 313{4 ,fld_VBI_20BIT_DATA1,VIP_VBI_20BIT_CNTL , 16, 0xFFF0FFFF, 0, 0,0, fld_VBI_20BIT_DATA1_def ,READWRITE }, 314{1 ,fld_VBI_20BIT_WT ,VIP_VBI_20BIT_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_def ,READWRITE }, 315{1 ,fld_VBI_20BIT_WT_ACK ,VIP_VBI_20BIT_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_20BIT_WT_ACK_def ,READONLY }, 316{1 ,fld_VBI_20BIT_HOLD ,VIP_VBI_20BIT_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_20BIT_HOLD_def ,READWRITE }, 317{2 ,fld_VBI_CAPTURE_ENABLE ,VIP_VBI_CONTROL , 0, 0xFFFFFFFC, 0, 0,0, fld_VBI_CAPTURE_ENABLE_def,READWRITE }, 318{16 ,fld_VBI_EDS_DATA ,VIP_VBI_EDS_CNTL , 0, 0xFFFF0000, 0, 0,0, fld_VBI_EDS_DATA_def ,READWRITE }, 319{1 ,fld_VBI_EDS_WT ,VIP_VBI_EDS_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VBI_EDS_WT_def ,READWRITE }, 320{1 ,fld_VBI_EDS_WT_ACK ,VIP_VBI_EDS_CNTL , 25, 0xFDFFFFFF, 0, 0,0, fld_VBI_EDS_WT_ACK_def ,READONLY }, 321{1 ,fld_VBI_EDS_HOLD ,VIP_VBI_EDS_CNTL , 26, 0xFBFFFFFF, 0, 0,0, fld_VBI_EDS_HOLD_def ,READWRITE }, 322{17 ,fld_VBI_SCALING_RATIO ,VIP_VBI_SCALER_CONTROL , 0, 0xFFFE0000, 0, 0,0, fld_VBI_SCALING_RATIO_def ,READWRITE }, 323{1 ,fld_VBI_ALIGNER_ENABLE ,VIP_VBI_SCALER_CONTROL , 17, 0xFFFDFFFF, 0, 0,0, fld_VBI_ALIGNER_ENABLE_def,READWRITE }, 324{11 ,fld_H_ACTIVE_START ,VIP_H_ACTIVE_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_ACTIVE_START_def ,READWRITE }, 325{11 ,fld_H_ACTIVE_END ,VIP_H_ACTIVE_WINDOW , 16, 0xF800FFFF, 0, 0,0, fld_H_ACTIVE_END_def ,READWRITE }, 326{10 ,fld_V_ACTIVE_START ,VIP_V_ACTIVE_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_V_ACTIVE_START_def ,READWRITE }, 327{10 ,fld_V_ACTIVE_END ,VIP_V_ACTIVE_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_ACTIVE_END_def ,READWRITE }, 328{8 ,fld_CH_HEIGHT ,VIP_CP_AGC_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_CH_HEIGHT_def ,READWRITE }, 329{8 ,fld_CH_KILL_LEVEL ,VIP_CP_AGC_CNTL , 8, 0xFFFF00FF, 0, 0,0, fld_CH_KILL_LEVEL_def ,READWRITE }, 330{2 ,fld_CH_AGC_ERROR_LIM ,VIP_CP_AGC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_CH_AGC_ERROR_LIM_def ,READWRITE }, 331{1 ,fld_CH_AGC_FILTER_EN ,VIP_CP_AGC_CNTL , 18, 0xFFFBFFFF, 0, 0,0, fld_CH_AGC_FILTER_EN_def ,READWRITE }, 332{1 ,fld_CH_AGC_LOOP_SPEED ,VIP_CP_AGC_CNTL , 19, 0xFFF7FFFF, 0, 0,0, fld_CH_AGC_LOOP_SPEED_def ,READWRITE }, 333{8 ,fld_HUE_ADJ ,VIP_CP_HUE_CNTL , 0, 0xFFFFFF00, 0, 0,0, fld_HUE_ADJ_def ,READWRITE }, 334{2 ,fld_STANDARD_SEL ,VIP_STANDARD_SELECT , 0, 0xFFFFFFFC, 0, 0,0, fld_STANDARD_SEL_def ,READWRITE }, 335{1 ,fld_STANDARD_YC ,VIP_STANDARD_SELECT , 2, 0xFFFFFFFB, 0, 0,0, fld_STANDARD_YC_def ,READWRITE }, 336{1 ,fld_ADC_PDWN ,VIP_ADC_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_ADC_PDWN_def ,READWRITE }, 337{3 ,fld_INPUT_SELECT ,VIP_ADC_CNTL , 0, 0xFFFFFFF8, 0, 0,0, fld_INPUT_SELECT_def ,READWRITE }, 338{2 ,fld_ADC_PREFLO ,VIP_ADC_CNTL , 24, 0xFCFFFFFF, 0, 0,0, fld_ADC_PREFLO_def ,READWRITE }, 339{8 ,fld_H_SYNC_PULSE_WIDTH ,VIP_HS_PULSE_WIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_H_SYNC_PULSE_WIDTH_def,READONLY }, 340{1 ,fld_HS_GENLOCKED ,VIP_HS_PULSE_WIDTH , 8, 0xFFFFFEFF, 0, 0,0, fld_HS_GENLOCKED_def ,READONLY }, 341{1 ,fld_HS_SYNC_IN_WIN ,VIP_HS_PULSE_WIDTH , 9, 0xFFFFFDFF, 0, 0,0, fld_HS_SYNC_IN_WIN_def ,READONLY }, 342{1 ,fld_VIN_ASYNC_RST ,VIP_MASTER_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_VIN_ASYNC_RST_def ,READWRITE }, 343{1 ,fld_DVS_ASYNC_RST ,VIP_MASTER_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_DVS_ASYNC_RST_def ,READWRITE }, 344{16 ,fld_VIP_VENDOR_ID ,VIP_VIP_VENDOR_DEVICE_ID, 0, 0xFFFF0000, 0, 0,0, fld_VIP_VENDOR_ID_def ,READONLY }, 345{16 ,fld_VIP_DEVICE_ID ,VIP_VIP_VENDOR_DEVICE_ID,16, 0x0000FFFF, 0, 0,0, fld_VIP_DEVICE_ID_def ,READONLY }, 346{16 ,fld_VIP_REVISION_ID ,VIP_VIP_REVISION_ID , 0, 0xFFFF0000, 0, 0,0, fld_VIP_REVISION_ID_def ,READONLY }, 347{8 ,fld_BLACK_INT_START ,VIP_SG_BLACK_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_BLACK_INT_START_def ,READWRITE }, 348{4 ,fld_BLACK_INT_LENGTH ,VIP_SG_BLACK_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_BLACK_INT_LENGTH_def ,READWRITE }, 349{8 ,fld_UV_INT_START ,VIP_SG_UVGATE_GATE , 0, 0xFFFFFF00, 0, 0,0, fld_UV_INT_START_def ,READWRITE }, 350{4 ,fld_U_INT_LENGTH ,VIP_SG_UVGATE_GATE , 8, 0xFFFFF0FF, 0, 0,0, fld_U_INT_LENGTH_def ,READWRITE }, 351{4 ,fld_V_INT_LENGTH ,VIP_SG_UVGATE_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_V_INT_LENGTH_def ,READWRITE }, 352{10 ,fld_CRDR_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 0, 0xFFFFFC00, 0, 0,0, fld_CRDR_ACTIVE_GAIN_def ,READWRITE }, 353{10 ,fld_CBDB_ACTIVE_GAIN ,VIP_CP_ACTIVE_GAIN , 16, 0xFC00FFFF, 0, 0,0, fld_CBDB_ACTIVE_GAIN_def ,READWRITE }, 354{1 ,fld_DVS_DIRECTION ,VIP_DVS_PORT_CTRL , 0, 0xFFFFFFFE, 0, 0,0, fld_DVS_DIRECTION_def ,READWRITE }, 355{1 ,fld_DVS_VBI_UINT8_SWAP ,VIP_DVS_PORT_CTRL , 1, 0xFFFFFFFD, 0, 0,0, fld_DVS_VBI_UINT8_SWAP_def ,READWRITE }, 356{1 ,fld_DVS_CLK_SELECT ,VIP_DVS_PORT_CTRL , 2, 0xFFFFFFFB, 0, 0,0, fld_DVS_CLK_SELECT_def ,READWRITE }, 357{1 ,fld_CONTINUOUS_STREAM ,VIP_DVS_PORT_CTRL , 3, 0xFFFFFFF7, 0, 0,0, fld_CONTINUOUS_STREAM_def ,READWRITE }, 358{1 ,fld_DVSOUT_CLK_DRV ,VIP_DVS_PORT_CTRL , 4, 0xFFFFFFEF, 0, 0,0, fld_DVSOUT_CLK_DRV_def ,READWRITE }, 359{1 ,fld_DVSOUT_DATA_DRV ,VIP_DVS_PORT_CTRL , 5, 0xFFFFFFDF, 0, 0,0, fld_DVSOUT_DATA_DRV_def ,READWRITE }, 360{32 ,fld_COMB_CNTL0 ,VIP_COMB_CNTL0 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL0_def ,READWRITE }, 361{32 ,fld_COMB_CNTL1 ,VIP_COMB_CNTL1 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL1_def ,READWRITE }, 362{32 ,fld_COMB_CNTL2 ,VIP_COMB_CNTL2 , 0, 0x00000000, 0, 0,0, fld_COMB_CNTL2_def ,READWRITE }, 363{32 ,fld_COMB_LENGTH ,VIP_COMB_LINE_LENGTH , 0, 0x00000000, 0, 0,0, fld_COMB_LENGTH_def ,READWRITE }, 364{8 ,fld_SYNCTIP_REF0 ,VIP_LP_AGC_CLAMP_CNTL0 , 0, 0xFFFFFF00, 0, 0,0, fld_SYNCTIP_REF0_def ,READWRITE }, 365{8 ,fld_SYNCTIP_REF1 ,VIP_LP_AGC_CLAMP_CNTL0 , 8, 0xFFFF00FF, 0, 0,0, fld_SYNCTIP_REF1_def ,READWRITE }, 366{8 ,fld_CLAMP_REF ,VIP_LP_AGC_CLAMP_CNTL0 , 16, 0xFF00FFFF, 0, 0,0, fld_CLAMP_REF_def ,READWRITE }, 367{8 ,fld_AGC_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL0 , 24, 0x00FFFFFF, 0, 0,0, fld_AGC_PEAKWHITE_def ,READWRITE }, 368{8 ,fld_VBI_PEAKWHITE ,VIP_LP_AGC_CLAMP_CNTL1 , 0, 0xFFFFFF00, 0, 0,0, fld_VBI_PEAKWHITE_def ,READWRITE }, 369{11 ,fld_WPA_THRESHOLD ,VIP_LP_WPA_CNTL0 , 0, 0xFFFFF800, 0, 0,0, fld_WPA_THRESHOLD_def ,READWRITE }, 370{10 ,fld_WPA_TRIGGER_LO ,VIP_LP_WPA_CNTL1 , 0, 0xFFFFFC00, 0, 0,0, fld_WPA_TRIGGER_LO_def ,READWRITE }, 371{10 ,fld_WPA_TRIGGER_HIGH ,VIP_LP_WPA_CNTL1 , 16, 0xFC00FFFF, 0, 0,0, fld_WPA_TRIGGER_HIGH_def ,READWRITE }, 372{10 ,fld_LOCKOUT_START ,VIP_LP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_LOCKOUT_START_def ,READWRITE }, 373{10 ,fld_LOCKOUT_END ,VIP_LP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_LOCKOUT_END_def ,READWRITE }, 374{24 ,fld_CH_DTO_INC ,VIP_CP_PLL_CNTL0 , 0, 0xFF000000, 0, 0,0, fld_CH_DTO_INC_def ,READWRITE }, 375{4 ,fld_PLL_SGAIN ,VIP_CP_PLL_CNTL0 , 24, 0xF0FFFFFF, 0, 0,0, fld_PLL_SGAIN_def ,READWRITE }, 376{4 ,fld_PLL_FGAIN ,VIP_CP_PLL_CNTL0 , 28, 0x0FFFFFFF, 0, 0,0, fld_PLL_FGAIN_def ,READWRITE }, 377{9 ,fld_CR_BURST_GAIN ,VIP_CP_BURST_GAIN , 0, 0xFFFFFE00, 0, 0,0, fld_CR_BURST_GAIN_def ,READWRITE }, 378{9 ,fld_CB_BURST_GAIN ,VIP_CP_BURST_GAIN , 16, 0xFE00FFFF, 0, 0,0, fld_CB_BURST_GAIN_def ,READWRITE }, 379{10 ,fld_VERT_LOCKOUT_START ,VIP_CP_VERT_LOCKOUT , 0, 0xFFFFFC00, 0, 0,0, fld_VERT_LOCKOUT_START_def,READWRITE }, 380{10 ,fld_VERT_LOCKOUT_END ,VIP_CP_VERT_LOCKOUT , 16, 0xFC00FFFF, 0, 0,0, fld_VERT_LOCKOUT_END_def ,READWRITE }, 381{11 ,fld_H_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 0, 0xFFFFF800, 0, 0,0, fld_H_IN_WIND_START_def ,READWRITE }, 382{10 ,fld_V_IN_WIND_START ,VIP_SCALER_IN_WINDOW , 16, 0xFC00FFFF, 0, 0,0, fld_V_IN_WIND_START_def ,READWRITE }, 383{10 ,fld_H_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 0, 0xFFFFFC00, 0, 0,0, fld_H_OUT_WIND_WIDTH_def ,READWRITE }, 384{9 ,fld_V_OUT_WIND_WIDTH ,VIP_SCALER_OUT_WINDOW , 16, 0xFE00FFFF, 0, 0,0, fld_V_OUT_WIND_WIDTH_def ,READWRITE }, 385{11 ,fld_HS_LINE_TOTAL ,VIP_HS_PLINE , 0, 0xFFFFF800, 0, 0,0, fld_HS_LINE_TOTAL_def ,READWRITE }, 386{8 ,fld_MIN_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 0, 0xFFFFFF00, 0, 0,0, fld_MIN_PULSE_WIDTH_def ,READWRITE }, 387{8 ,fld_MAX_PULSE_WIDTH ,VIP_HS_MINMAXWIDTH , 8, 0xFFFF00FF, 0, 0,0, fld_MAX_PULSE_WIDTH_def ,READWRITE }, 388{11 ,fld_WIN_CLOSE_LIMIT ,VIP_HS_WINDOW_LIMIT , 0, 0xFFFFF800, 0, 0,0, fld_WIN_CLOSE_LIMIT_def ,READWRITE }, 389{11 ,fld_WIN_OPEN_LIMIT ,VIP_HS_WINDOW_LIMIT , 16, 0xF800FFFF, 0, 0,0, fld_WIN_OPEN_LIMIT_def ,READWRITE }, 390{11 ,fld_VSYNC_INT_TRIGGER ,VIP_VS_DETECTOR_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VSYNC_INT_TRIGGER_def ,READWRITE }, 391{11 ,fld_VSYNC_INT_HOLD ,VIP_VS_DETECTOR_CNTL , 16, 0xF800FFFF, 0, 0,0, fld_VSYNC_INT_HOLD_def ,READWRITE }, 392{11 ,fld_VIN_M0 ,VIP_VIN_PLL_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M0_def ,READWRITE }, 393{11 ,fld_VIN_N0 ,VIP_VIN_PLL_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N0_def ,READWRITE }, 394{1 ,fld_MNFLIP_EN ,VIP_VIN_PLL_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_MNFLIP_EN_def ,READWRITE }, 395{4 ,fld_VIN_P ,VIP_VIN_PLL_CNTL , 24, 0xF0FFFFFF, 0, 0,0, fld_VIN_P_def ,READWRITE }, 396{2 ,fld_REG_CLK_SEL ,VIP_VIN_PLL_CNTL , 30, 0x3FFFFFFF, 0, 0,0, fld_REG_CLK_SEL_def ,READWRITE }, 397{11 ,fld_VIN_M1 ,VIP_VIN_PLL_FINE_CNTL , 0, 0xFFFFF800, 0, 0,0, fld_VIN_M1_def ,READWRITE }, 398{11 ,fld_VIN_N1 ,VIP_VIN_PLL_FINE_CNTL , 11, 0xFFC007FF, 0, 0,0, fld_VIN_N1_def ,READWRITE }, 399{1 ,fld_VIN_DRIVER_SEL ,VIP_VIN_PLL_FINE_CNTL , 22, 0xFFBFFFFF, 0, 0,0, fld_VIN_DRIVER_SEL_def ,READWRITE }, 400{1 ,fld_VIN_MNFLIP_REQ ,VIP_VIN_PLL_FINE_CNTL , 23, 0xFF7FFFFF, 0, 0,0, fld_VIN_MNFLIP_REQ_def ,READWRITE }, 401{1 ,fld_VIN_MNFLIP_DONE ,VIP_VIN_PLL_FINE_CNTL , 24, 0xFEFFFFFF, 0, 0,0, fld_VIN_MNFLIP_DONE_def ,READONLY }, 402{1 ,fld_TV_LOCK_TO_VIN ,VIP_VIN_PLL_FINE_CNTL , 27, 0xF7FFFFFF, 0, 0,0, fld_TV_LOCK_TO_VIN_def ,READWRITE }, 403{4 ,fld_TV_P_FOR_WINCLK ,VIP_VIN_PLL_FINE_CNTL , 28, 0x0FFFFFFF, 0, 0,0, fld_TV_P_FOR_WINCLK_def ,READWRITE }, 404{1 ,fld_VINRST ,VIP_PLL_CNTL1 , 1, 0xFFFFFFFD, 0, 0,0, fld_VINRST_def ,READWRITE }, 405{1 ,fld_VIN_CLK_SEL ,VIP_CLOCK_SEL_CNTL , 7, 0xFFFFFF7F, 0, 0,0, fld_VIN_CLK_SEL_def ,READWRITE }, 406{10 ,fld_VS_FIELD_BLANK_START,VIP_VS_BLANKING_CNTL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FIELD_BLANK_START_def ,READWRITE }, 407{10 ,fld_VS_FIELD_BLANK_END,VIP_VS_BLANKING_CNTL , 16, 0xFC00FFFF, 0, 0,0, fld_VS_FIELD_BLANK_END_def ,READWRITE }, 408{9 ,fld_VS_FIELD_IDLOCATION,VIP_VS_FIELD_ID_CNTL , 0, 0xFFFFFE00, 0, 0,0, fld_VS_FIELD_IDLOCATION_def ,READWRITE }, 409{10 ,fld_VS_FRAME_TOTAL ,VIP_VS_FRAME_TOTAL , 0, 0xFFFFFC00, 0, 0,0, fld_VS_FRAME_TOTAL_def ,READWRITE }, 410{11 ,fld_SYNC_TIP_START ,VIP_SG_SYNCTIP_GATE , 0, 0xFFFFF800, 0, 0,0, fld_SYNC_TIP_START_def ,READWRITE }, 411{4 ,fld_SYNC_TIP_LENGTH ,VIP_SG_SYNCTIP_GATE , 12, 0xFFFF0FFF, 0, 0,0, fld_SYNC_TIP_LENGTH_def ,READWRITE }, 412{12 ,fld_GAIN_FORCE_DATA ,VIP_CP_DEBUG_FORCE , 0, 0xFFFFF000, 0, 0,0, fld_GAIN_FORCE_DATA_def ,READWRITE }, 413{1 ,fld_GAIN_FORCE_EN ,VIP_CP_DEBUG_FORCE , 12, 0xFFFFEFFF, 0, 0,0, fld_GAIN_FORCE_EN_def ,READWRITE }, 414{2 ,fld_I_CLAMP_SEL ,VIP_ADC_CNTL , 3, 0xFFFFFFE7, 0, 0,0, fld_I_CLAMP_SEL_def ,READWRITE }, 415{2 ,fld_I_AGC_SEL ,VIP_ADC_CNTL , 5, 0xFFFFFF9F, 0, 0,0, fld_I_AGC_SEL_def ,READWRITE }, 416{1 ,fld_EXT_CLAMP_CAP ,VIP_ADC_CNTL , 8, 0xFFFFFEFF, 0, 0,0, fld_EXT_CLAMP_CAP_def ,READWRITE }, 417{1 ,fld_EXT_AGC_CAP ,VIP_ADC_CNTL , 9, 0xFFFFFDFF, 0, 0,0, fld_EXT_AGC_CAP_def ,READWRITE }, 418{1 ,fld_DECI_DITHER_EN ,VIP_ADC_CNTL , 12, 0xFFFFEFFF, 0, 0,0, fld_DECI_DITHER_EN_def ,READWRITE }, 419{2 ,fld_ADC_PREFHI ,VIP_ADC_CNTL , 22, 0xFF3FFFFF, 0, 0,0, fld_ADC_PREFHI_def ,READWRITE }, 420{2 ,fld_ADC_CH_GAIN_SEL ,VIP_ADC_CNTL , 16, 0xFFFCFFFF, 0, 0,0, fld_ADC_CH_GAIN_SEL_def ,READWRITE }, 421{4 ,fld_HS_PLL_SGAIN ,VIP_HS_PLLGAIN , 0, 0xFFFFFFF0, 0, 0,0, fld_HS_PLL_SGAIN_def ,READWRITE }, 422{1 ,fld_NREn ,VIP_NOISE_CNTL0 , 0, 0xFFFFFFFE, 0, 0,0, fld_NREn_def ,READWRITE }, 423{3 ,fld_NRGainCntl ,VIP_NOISE_CNTL0 , 1, 0xFFFFFFF1, 0, 0,0, fld_NRGainCntl_def ,READWRITE }, 424{6 ,fld_NRBWTresh ,VIP_NOISE_CNTL0 , 4, 0xFFFFFC0F, 0, 0,0, fld_NRBWTresh_def ,READWRITE }, 425{5 ,fld_NRGCTresh ,VIP_NOISE_CNTL0 , 10, 0xFFFF83FF, 0, 0,0, fld_NRGCTresh_def ,READWRITE }, 426{1 ,fld_NRCoefDespeclMode ,VIP_NOISE_CNTL0 , 15, 0xFFFF7FFF, 0, 0,0, fld_NRCoefDespeclMode_def ,READWRITE }, 427{1 ,fld_GPIO_5_OE ,VIP_GPIO_CNTL , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OE_def ,READWRITE }, 428{1 ,fld_GPIO_6_OE ,VIP_GPIO_CNTL , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OE_def ,READWRITE }, 429{1 ,fld_GPIO_5_OUT ,VIP_GPIO_INOUT , 5, 0xFFFFFFDF, 0, 0,0, fld_GPIO_5_OUT_def ,READWRITE }, 430{1 ,fld_GPIO_6_OUT ,VIP_GPIO_INOUT , 6, 0xFFFFFFBF, 0, 0,0, fld_GPIO_6_OUT_def ,READWRITE }, 431}; 432 433/* Rage Theatre's register fields default values: */ 434uint32_t RT_RegDef[regRT_MAX_REGS]= 435{ 436fld_tmpReg1_def, 437fld_tmpReg2_def, 438fld_tmpReg3_def, 439fld_LP_CONTRAST_def, 440fld_LP_BRIGHTNESS_def, 441fld_CP_HUE_CNTL_def, 442fld_LUMA_FILTER_def, 443fld_H_SCALE_RATIO_def, 444fld_H_SHARPNESS_def, 445fld_V_SCALE_RATIO_def, 446fld_V_DEINTERLACE_ON_def, 447fld_V_BYPSS_def, 448fld_V_DITHER_ON_def, 449fld_EVENF_OFFSET_def, 450fld_ODDF_OFFSET_def, 451fld_INTERLACE_DETECTED_def, 452fld_VS_LINE_COUNT_def, 453fld_VS_DETECTED_LINES_def, 454fld_VS_ITU656_VB_def, 455fld_VBI_CC_DATA_def, 456fld_VBI_CC_WT_def, 457fld_VBI_CC_WT_ACK_def, 458fld_VBI_CC_HOLD_def, 459fld_VBI_DECODE_EN_def, 460fld_VBI_CC_DTO_P_def, 461fld_VBI_20BIT_DTO_P_def, 462fld_VBI_CC_LEVEL_def, 463fld_VBI_20BIT_LEVEL_def, 464fld_VBI_CLK_RUNIN_GAIN_def, 465fld_H_VBI_WIND_START_def, 466fld_H_VBI_WIND_END_def, 467fld_V_VBI_WIND_START_def, 468fld_V_VBI_WIND_END_def, 469fld_VBI_20BIT_DATA0_def, 470fld_VBI_20BIT_DATA1_def, 471fld_VBI_20BIT_WT_def, 472fld_VBI_20BIT_WT_ACK_def, 473fld_VBI_20BIT_HOLD_def, 474fld_VBI_CAPTURE_ENABLE_def, 475fld_VBI_EDS_DATA_def, 476fld_VBI_EDS_WT_def, 477fld_VBI_EDS_WT_ACK_def, 478fld_VBI_EDS_HOLD_def, 479fld_VBI_SCALING_RATIO_def, 480fld_VBI_ALIGNER_ENABLE_def, 481fld_H_ACTIVE_START_def, 482fld_H_ACTIVE_END_def, 483fld_V_ACTIVE_START_def, 484fld_V_ACTIVE_END_def, 485fld_CH_HEIGHT_def, 486fld_CH_KILL_LEVEL_def, 487fld_CH_AGC_ERROR_LIM_def, 488fld_CH_AGC_FILTER_EN_def, 489fld_CH_AGC_LOOP_SPEED_def, 490fld_HUE_ADJ_def, 491fld_STANDARD_SEL_def, 492fld_STANDARD_YC_def, 493fld_ADC_PDWN_def, 494fld_INPUT_SELECT_def, 495fld_ADC_PREFLO_def, 496fld_H_SYNC_PULSE_WIDTH_def, 497fld_HS_GENLOCKED_def, 498fld_HS_SYNC_IN_WIN_def, 499fld_VIN_ASYNC_RST_def, 500fld_DVS_ASYNC_RST_def, 501fld_VIP_VENDOR_ID_def, 502fld_VIP_DEVICE_ID_def, 503fld_VIP_REVISION_ID_def, 504fld_BLACK_INT_START_def, 505fld_BLACK_INT_LENGTH_def, 506fld_UV_INT_START_def, 507fld_U_INT_LENGTH_def, 508fld_V_INT_LENGTH_def, 509fld_CRDR_ACTIVE_GAIN_def, 510fld_CBDB_ACTIVE_GAIN_def, 511fld_DVS_DIRECTION_def, 512fld_DVS_VBI_UINT8_SWAP_def, 513fld_DVS_CLK_SELECT_def, 514fld_CONTINUOUS_STREAM_def, 515fld_DVSOUT_CLK_DRV_def, 516fld_DVSOUT_DATA_DRV_def, 517fld_COMB_CNTL0_def, 518fld_COMB_CNTL1_def, 519fld_COMB_CNTL2_def, 520fld_COMB_LENGTH_def, 521fld_SYNCTIP_REF0_def, 522fld_SYNCTIP_REF1_def, 523fld_CLAMP_REF_def, 524fld_AGC_PEAKWHITE_def, 525fld_VBI_PEAKWHITE_def, 526fld_WPA_THRESHOLD_def, 527fld_WPA_TRIGGER_LO_def, 528fld_WPA_TRIGGER_HIGH_def, 529fld_LOCKOUT_START_def, 530fld_LOCKOUT_END_def, 531fld_CH_DTO_INC_def, 532fld_PLL_SGAIN_def, 533fld_PLL_FGAIN_def, 534fld_CR_BURST_GAIN_def, 535fld_CB_BURST_GAIN_def, 536fld_VERT_LOCKOUT_START_def, 537fld_VERT_LOCKOUT_END_def, 538fld_H_IN_WIND_START_def, 539fld_V_IN_WIND_START_def, 540fld_H_OUT_WIND_WIDTH_def, 541fld_V_OUT_WIND_WIDTH_def, 542fld_HS_LINE_TOTAL_def, 543fld_MIN_PULSE_WIDTH_def, 544fld_MAX_PULSE_WIDTH_def, 545fld_WIN_CLOSE_LIMIT_def, 546fld_WIN_OPEN_LIMIT_def, 547fld_VSYNC_INT_TRIGGER_def, 548fld_VSYNC_INT_HOLD_def, 549fld_VIN_M0_def, 550fld_VIN_N0_def, 551fld_MNFLIP_EN_def, 552fld_VIN_P_def, 553fld_REG_CLK_SEL_def, 554fld_VIN_M1_def, 555fld_VIN_N1_def, 556fld_VIN_DRIVER_SEL_def, 557fld_VIN_MNFLIP_REQ_def, 558fld_VIN_MNFLIP_DONE_def, 559fld_TV_LOCK_TO_VIN_def, 560fld_TV_P_FOR_WINCLK_def, 561fld_VINRST_def, 562fld_VIN_CLK_SEL_def, 563fld_VS_FIELD_BLANK_START_def, 564fld_VS_FIELD_BLANK_END_def, 565fld_VS_FIELD_IDLOCATION_def, 566fld_VS_FRAME_TOTAL_def, 567fld_SYNC_TIP_START_def, 568fld_SYNC_TIP_LENGTH_def, 569fld_GAIN_FORCE_DATA_def, 570fld_GAIN_FORCE_EN_def, 571fld_I_CLAMP_SEL_def, 572fld_I_AGC_SEL_def, 573fld_EXT_CLAMP_CAP_def, 574fld_EXT_AGC_CAP_def, 575fld_DECI_DITHER_EN_def, 576fld_ADC_PREFHI_def, 577fld_ADC_CH_GAIN_SEL_def, 578fld_HS_PLL_SGAIN_def, 579fld_NREn_def, 580fld_NRGainCntl_def, 581fld_NRBWTresh_def, 582fld_NRGCTresh_def, 583fld_NRCoefDespeclMode_def, 584fld_GPIO_5_OE_def, 585fld_GPIO_6_OE_def, 586fld_GPIO_5_OUT_def, 587fld_GPIO_6_OUT_def, 588}; 589 590/**************************************************************************** 591 * WriteRT_fld (uint32_t dwReg, uint32_t dwData) * 592 * Function: Writes a register field within Rage Theatre * 593 * Inputs: uint32_t dwReg = register field to be written * 594 * uint32_t dwData = data that will be written to the reg field * 595 * Outputs: NONE * 596 ****************************************************************************/ 597static void WriteRT_fld1 (TheatrePtr t, uint32_t dwReg, uint32_t dwData) 598{ 599 uint32_t dwResult=0; 600 uint32_t dwValue=0; 601 602 if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) 603 { 604 dwValue = (dwResult & RT_RegMap[dwReg].dwMaskLSBs) | 605 (dwData << RT_RegMap[dwReg].dwFldOffsetLSBs); 606 607 if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE) 608 { 609 /* update the memory mapped registers */ 610 RT_RegMap[dwReg].dwCurrValue = dwData; 611 } 612 613 } 614 615 return; 616 617} /* WriteRT_fld ()... */ 618 619/**************************************************************************** 620 * ReadRT_fld (uint32_t dwReg) * 621 * Function: Reads a register field within Rage Theatre * 622 * Inputs: uint32_t dwReg = register field to be read * 623 * Outputs: uint32_t - value read from register field * 624 ****************************************************************************/ 625static uint32_t ReadRT_fld1 (TheatrePtr t,uint32_t dwReg) 626{ 627 uint32_t dwResult=0; 628 629 if (RT_regr (RT_RegMap[dwReg].dwRegAddrLSBs, &dwResult) == TRUE) 630 { 631 RT_RegMap[dwReg].dwCurrValue = ((dwResult & ~RT_RegMap[dwReg].dwMaskLSBs) >> 632 RT_RegMap[dwReg].dwFldOffsetLSBs); 633 return (RT_RegMap[dwReg].dwCurrValue); 634 } 635 else 636 { 637 return (0xFFFFFFFF); 638 } 639 640} /* ReadRT_fld ()... */ 641 642#define WriteRT_fld(a,b) WriteRT_fld1(t, (a), (b)) 643#define ReadRT_fld(a) ReadRT_fld1(t,(a)) 644 645/**************************************************************************** 646 * RT_SetVINClock (uint16_t wStandard) * 647 * Function: to set the VIN clock for the selected standard * 648 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 649 * Outputs: NONE * 650 ****************************************************************************/ 651static void RT_SetVINClock(TheatrePtr t, uint16_t wStandard) 652{ 653 uint32_t dwM0=0, dwN0=0, dwP=0; 654 uint8_t ref_freq; 655 656 /* Determine the reference frequency first. This can be obtained 657 from the MMTABLE.video_decoder_type field (bits 4:7) 658 The Rage Theatre currently only supports reference frequencies of 659 27 or 29.49 MHz. */ 660 /* 661 R128ReadBIOS(0x48, 662 (uint8_t *)&bios_header, sizeof(bios_header)); 663 R128ReadBIOS(bios_header + 0x30, 664 (uint8_t *)&pll_info_block, sizeof(pll_info_block)); 665 666 R128ReadBIOS(pll_info_block+0x07, &video_decoder_type, sizeof(video_decoder_type)); 667 */ 668 ref_freq = (t->video_decoder_type & 0xF0) >> 4; 669 670 671 switch (wStandard & 0x00FF) 672 { 673 case (DEC_NTSC): /* NTSC GROUP - 480 lines */ 674 switch (wStandard & 0xFF00) 675 { 676 case (extNONE): 677 case (extNTSC): 678 case (extNTSC_J): 679 if (ref_freq == RT_FREF_2950) 680 { 681 dwM0 = 0x39; 682 dwN0 = 0x14C; 683 dwP = 0x6; 684 } 685 else 686 { 687 dwM0 = 0x0B; 688 dwN0 = 0x46; 689 dwP = 0x6; 690 } 691 break; 692 693 case (extNTSC_443): 694 if (ref_freq == RT_FREF_2950) 695 { 696 dwM0 = 0x23; 697 dwN0 = 0x88; 698 dwP = 0x7; 699 } 700 else 701 { 702 dwM0 = 0x2C; 703 dwN0 = 0x121; 704 dwP = 0x5; 705 } 706 break; 707 708 case (extPAL_M): 709 if (ref_freq == RT_FREF_2950) 710 { 711 dwM0 = 0x2C; 712 dwN0 = 0x12B; 713 dwP = 0x7; 714 } 715 else 716 { 717 dwM0 = 0x0B; 718 dwN0 = 0x46; 719 dwP = 0x6; 720 } 721 break; 722 723 default: 724 return; 725 } 726 break; 727 case (DEC_PAL): 728 switch (wStandard & 0xFF00) 729 { 730 case (extPAL): 731 case (extPAL_N): 732 case (extPAL_BGHI): 733 case (extPAL_60): 734 if (ref_freq == RT_FREF_2950) 735 { 736 dwM0 = 0x0E; 737 dwN0 = 0x65; 738 dwP = 0x6; 739 } 740 else 741 { 742 dwM0 = 0x2C; 743 dwN0 = 0x0121; 744 dwP = 0x5; 745 } 746 break; 747 748 case (extPAL_NCOMB): 749 if (ref_freq == RT_FREF_2950) 750 { 751 dwM0 = 0x23; 752 dwN0 = 0x88; 753 dwP = 0x7; 754 } 755 else 756 { 757 dwM0 = 0x37; 758 dwN0 = 0x1D3; 759 dwP = 0x8; 760 } 761 break; 762 763 default: 764 return; 765 } 766 break; 767 768 case (DEC_SECAM): 769 if (ref_freq == RT_FREF_2950) 770 { 771 dwM0 = 0xE; 772 dwN0 = 0x65; 773 dwP = 0x6; 774 } 775 else 776 { 777 dwM0 = 0x2C; 778 dwN0 = 0x121; 779 dwP = 0x5; 780 } 781 break; 782 } 783 784 /* VIN_PLL_CNTL */ 785 WriteRT_fld (fld_VIN_M0, dwM0); 786 WriteRT_fld (fld_VIN_N0, dwN0); 787 WriteRT_fld (fld_VIN_P, dwP); 788 789 return; 790} /* RT_SetVINClock ()... */ 791 792/**************************************************************************** 793 * RT_SetTint (int hue) * 794 * Function: sets the tint (hue) for the Rage Theatre video in * 795 * Inputs: int hue - the hue value to be set. * 796 * Outputs: NONE * 797 ****************************************************************************/ 798_X_EXPORT void RT_SetTint (TheatrePtr t, int hue) 799{ 800 uint32_t nhue = 0; 801 802 t->iHue=hue; 803 /* Scale hue value from -1000<->1000 to -180<->180 */ 804 hue = (double)(hue+1000) * 0.18 - 180; 805 806 /* Validate Hue level */ 807 if (hue < -180) 808 { 809 hue = -180; 810 } 811 else if (hue > 180) 812 { 813 hue = 180; 814 } 815 816 /* save the "validated" hue, but scale it back up to -1000<->1000 */ 817 t->iHue = (double)hue/0.18; 818 819 switch (t->wStandard & 0x00FF) 820 { 821 case (DEC_NTSC): /* original ATI code had _empty_ section for PAL/SECAM... which did not work, 822 obviously */ 823 case (DEC_PAL): 824 case (DEC_SECAM): 825 if (hue >= 0) 826 { 827 nhue = (uint32_t) (256 * hue)/360; 828 } 829 else 830 { 831 nhue = (uint32_t) (256 * (hue + 360))/360; 832 } 833 break; 834 835 default: break; 836 } 837 838 WriteRT_fld(fld_CP_HUE_CNTL, nhue); 839 840 return; 841 842} /* RT_SetTint ()... */ 843 844 845/**************************************************************************** 846 * RT_SetSaturation (int Saturation) * 847 * Function: sets the saturation level for the Rage Theatre video in * 848 * Inputs: int Saturation - the saturation value to be set. * 849 * Outputs: NONE * 850 ****************************************************************************/ 851_X_EXPORT void RT_SetSaturation (TheatrePtr t, int Saturation) 852{ 853 uint16_t wSaturation_V, wSaturation_U; 854 double dbSaturation = 0, dbCrGain = 0, dbCbGain = 0; 855 856 /* VALIDATE SATURATION LEVEL */ 857 if (Saturation < -1000L) 858 { 859 Saturation = -1000; 860 } 861 else if (Saturation > 1000L) 862 { 863 Saturation = 1000; 864 } 865 866 t->iSaturation = Saturation; 867 868 if (Saturation > 0) 869 { 870 /* Scale saturation up, to use full allowable register width */ 871 Saturation = (double)(Saturation) * 4.9; 872 } 873 874 dbSaturation = (double) (Saturation+1000.0) / 1000.0; 875 876 CalculateCrCbGain (t, &dbCrGain, &dbCbGain, t->wStandard); 877 878 wSaturation_U = (uint16_t) ((dbCrGain * dbSaturation * 128.0) + 0.5); 879 wSaturation_V = (uint16_t) ((dbCbGain * dbSaturation * 128.0) + 0.5); 880 881 /* SET SATURATION LEVEL */ 882 WriteRT_fld (fld_CRDR_ACTIVE_GAIN, wSaturation_U); 883 WriteRT_fld (fld_CBDB_ACTIVE_GAIN, wSaturation_V); 884 885 t->wSaturation_U = wSaturation_U; 886 t->wSaturation_V = wSaturation_V; 887 888 return; 889 890} /* RT_SetSaturation ()...*/ 891 892/**************************************************************************** 893 * RT_SetBrightness (int Brightness) * 894 * Function: sets the brightness level for the Rage Theatre video in * 895 * Inputs: int Brightness - the brightness value to be set. * 896 * Outputs: NONE * 897 ****************************************************************************/ 898_X_EXPORT void RT_SetBrightness (TheatrePtr t, int Brightness) 899{ 900 double dbSynctipRef0=0, dbContrast=1; 901 902 double dbYgain=0; 903 double dbBrightness=0; 904 double dbSetup=0; 905 uint16_t wBrightness=0; 906 907 /* VALIDATE BRIGHTNESS LEVEL */ 908 if (Brightness < -1000) 909 { 910 Brightness = -1000; 911 } 912 else if (Brightness > 1000) 913 { 914 Brightness = 1000; 915 } 916 917 /* Save value */ 918 t->iBrightness = Brightness; 919 920 t->dbBrightnessRatio = (double) (Brightness+1000.0) / 10.0; 921 922 dbBrightness = (double) (Brightness)/10.0; 923 924 dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0); 925 926 if(t->dbContrast == 0) 927 { 928 t->dbContrast = 1.0; /*NTSC default; */ 929 } 930 931 dbContrast = (double) t->dbContrast; 932 933 /* Use the following formula to determine the brightness level */ 934 switch (t->wStandard & 0x00FF) 935 { 936 case (DEC_NTSC): 937 if ((t->wStandard & 0xFF00) == extNTSC_J) 938 { 939 dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /40.0); 940 } 941 else 942 { 943 dbSetup = 7.5 * (double)(dbSynctipRef0) / 40.0; 944 dbYgain = 219.0 / (92.5 * (double)(dbSynctipRef0) / 40.0); 945 } 946 break; 947 case (DEC_PAL): 948 case (DEC_SECAM): 949 dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /43.0); 950 break; 951 default: 952 break; 953 } 954 955 wBrightness = (uint16_t) (16.0 * ((dbBrightness-dbSetup) + (16.0 / (dbContrast * dbYgain)))); 956 957 WriteRT_fld (fld_LP_BRIGHTNESS, wBrightness); 958 959 /*RT_SetSaturation (t->iSaturation); */ 960 961 return; 962 963} /* RT_SetBrightness ()... */ 964 965 966/**************************************************************************** 967 * RT_SetSharpness (uint16_t wSharpness) * 968 * Function: sets the sharpness level for the Rage Theatre video in * 969 * Inputs: uint16_t wSharpness - the sharpness value to be set. * 970 * Outputs: NONE * 971 ****************************************************************************/ 972_X_EXPORT void RT_SetSharpness (TheatrePtr t, uint16_t wSharpness) 973{ 974 switch (wSharpness) 975 { 976 case DEC_SMOOTH : 977 WriteRT_fld (fld_H_SHARPNESS, RT_NORM_SHARPNESS); 978 t->wSharpness = RT_NORM_SHARPNESS; 979 break; 980 case DEC_SHARP : 981 WriteRT_fld (fld_H_SHARPNESS, RT_HIGH_SHARPNESS); 982 t->wSharpness = RT_HIGH_SHARPNESS; 983 break; 984 default: 985 break; 986 } 987 return; 988 989} /* RT_SetSharpness ()... */ 990 991 992/**************************************************************************** 993 * RT_SetContrast (int Contrast) * 994 * Function: sets the contrast level for the Rage Theatre video in * 995 * Inputs: int Contrast - the contrast value to be set. * 996 * Outputs: NONE * 997 ****************************************************************************/ 998_X_EXPORT void RT_SetContrast (TheatrePtr t, int Contrast) 999{ 1000 double dbSynctipRef0=0, dbContrast=0; 1001 double dbYgain=0; 1002 uint8_t bTempContrast=0; 1003 1004 /* VALIDATE CONTRAST LEVEL */ 1005 if (Contrast < -1000) 1006 { 1007 Contrast = -1000; 1008 } 1009 else if (Contrast > 1000) 1010 { 1011 Contrast = 1000; 1012 } 1013 1014 /* Save contrast value */ 1015 t->iContrast = Contrast; 1016 1017 dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0); 1018 dbContrast = (double) (Contrast+1000.0) / 1000.0; 1019 1020 switch (t->wStandard & 0x00FF) 1021 { 1022 case (DEC_NTSC): 1023 if ((t->wStandard & 0xFF00) == (extNTSC_J)) 1024 { 1025 dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /40.0); 1026 } 1027 else 1028 { 1029 dbYgain = 219.0 / ( 92.5 * (double)(dbSynctipRef0) /40.0); 1030 } 1031 break; 1032 case (DEC_PAL): 1033 case (DEC_SECAM): 1034 dbYgain = 219.0 / ( 100.0 * (double)(dbSynctipRef0) /43.0); 1035 break; 1036 default: 1037 break; 1038 } 1039 1040 bTempContrast = (uint8_t) ((dbContrast * dbYgain * 64) + 0.5); 1041 1042 WriteRT_fld (fld_LP_CONTRAST, (uint32_t)bTempContrast); 1043 1044 /* Save value for future modification */ 1045 t->dbContrast = dbContrast; 1046 1047 return; 1048 1049} /* RT_SetContrast ()... */ 1050 1051/**************************************************************************** 1052 * RT_SetInterlace (uint8_t bInterlace) * 1053 * Function: to set the interlacing pattern for the Rage Theatre video in * 1054 * Inputs: uint8_t bInterlace * 1055 * Outputs: NONE * 1056 ****************************************************************************/ 1057_X_EXPORT void RT_SetInterlace (TheatrePtr t, uint8_t bInterlace) 1058{ 1059 1060 switch(bInterlace) 1061 { 1062 case (TRUE): /*DEC_INTERLACE */ 1063 WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); 1064 t->wInterlaced = (uint16_t) RT_DECINTERLACED; 1065 break; 1066 case (FALSE): /*DEC_NONINTERLACE */ 1067 WriteRT_fld (fld_V_DEINTERLACE_ON, RT_DECNONINTERLACED); 1068 t->wInterlaced = (uint16_t) RT_DECNONINTERLACED; 1069 break; 1070 default: 1071 break; 1072 } 1073 1074 return; 1075 1076} /* RT_SetInterlace ()... */ 1077 1078/**************************************************************************** 1079 * GetStandardConstants (double *LPeriod, double *FPeriod, * 1080 * double *Fsamp, uint16_t wStandard) * 1081 * Function: return timing values for a given standard * 1082 * Inputs: double *LPeriod - 1083 * double *FPeriod - 1084 * double *Fsamp - sampling frequency used for a given standard * 1085 * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1086 * Outputs: NONE * 1087 ****************************************************************************/ 1088static void GetStandardConstants (double *LPeriod, double *FPeriod, 1089 double *Fsamp, uint16_t wStandard) 1090{ 1091 *LPeriod = 0.0; 1092 *FPeriod = 0.0; 1093 *Fsamp = 0.0; 1094 1095 switch (wStandard & 0x00FF) 1096 { 1097 case (DEC_NTSC): /*NTSC GROUP - 480 lines*/ 1098 switch (wStandard & 0xFF00) 1099 { 1100 case (extNONE): 1101 case (extNTSC): 1102 case (extNTSC_J): 1103 *LPeriod = (double) 63.5555; 1104 *FPeriod = (double) 16.6833; 1105 *Fsamp = (double) 28.63636; 1106 break; 1107 case (extPAL_M): 1108 *LPeriod = (double) 63.492; 1109 *FPeriod = (double) 16.667; 1110 *Fsamp = (double) 28.63689192; 1111 break; 1112 default: 1113 return; 1114 } 1115 break; 1116 case (DEC_PAL): 1117 if( (wStandard & 0xFF00) == extPAL_N ) 1118 { 1119 *LPeriod = (double) 64.0; 1120 *FPeriod = (double) 20.0; 1121 *Fsamp = (double) 28.65645; 1122 } 1123 else 1124 { 1125 *LPeriod = (double) 64.0; 1126 *FPeriod = (double) 20.0; 1127 *Fsamp = (double) 35.46895; 1128 } 1129 break; 1130 case (DEC_SECAM): 1131 *LPeriod = (double) 64.0; 1132 *FPeriod = (double) 20.0; 1133 *Fsamp = (double) 35.46895; 1134 break; 1135 } 1136 return; 1137 1138} /* GetStandardConstants ()...*/ 1139 1140 1141/**************************************************************************** 1142 * RT_SetStandard (uint16_t wStandard) * 1143 * Function: to set the input standard for the Rage Theatre video in * 1144 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1145 * Outputs: NONE * 1146 ****************************************************************************/ 1147_X_EXPORT void RT_SetStandard (TheatrePtr t, uint16_t wStandard) 1148{ 1149 double dbFsamp=0, dbLPeriod=0, dbFPeriod=0; 1150 uint16_t wFrameTotal = 0; 1151 double dbSPPeriod = 4.70; 1152 1153 xf86DrvMsg(t->VIP->pScrn->scrnIndex,X_INFO,"Rage Theatre setting standard 0x%04x\n", 1154 wStandard); 1155 t->wStandard = wStandard; 1156 1157 /* Get the constants for the given standard. */ 1158 GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); 1159 1160 wFrameTotal = (uint16_t) (((2.0 * dbFPeriod) * 1000 / dbLPeriod) + 0.5); 1161 1162 /* Procedures before setting the standards: */ 1163 WriteRT_fld (fld_VIN_CLK_SEL, RT_REF_CLK); 1164 WriteRT_fld (fld_VINRST, RT_VINRST_RESET); 1165 1166 RT_SetVINClock (t, wStandard); 1167 1168 WriteRT_fld (fld_VINRST, RT_VINRST_ACTIVE); 1169 WriteRT_fld (fld_VIN_CLK_SEL, RT_PLL_VIN_CLK); 1170 1171 /* Program the new standards: */ 1172 switch (wStandard & 0x00FF) 1173 { 1174 case (DEC_NTSC): /*NTSC GROUP - 480 lines */ 1175 WriteRT_fld (fld_STANDARD_SEL, RT_NTSC); 1176 WriteRT_fld (fld_SYNCTIP_REF0, RT_NTSCM_SYNCTIP_REF0); 1177 WriteRT_fld (fld_SYNCTIP_REF1, RT_NTSCM_SYNCTIP_REF1); 1178 WriteRT_fld (fld_CLAMP_REF, RT_NTSCM_CLAMP_REF); 1179 WriteRT_fld (fld_AGC_PEAKWHITE, RT_NTSCM_PEAKWHITE); 1180 WriteRT_fld (fld_VBI_PEAKWHITE, RT_NTSCM_VBI_PEAKWHITE); 1181 WriteRT_fld (fld_WPA_THRESHOLD, RT_NTSCM_WPA_THRESHOLD); 1182 WriteRT_fld (fld_WPA_TRIGGER_LO, RT_NTSCM_WPA_TRIGGER_LO); 1183 WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_NTSCM_WPA_TRIGGER_HIGH); 1184 WriteRT_fld (fld_LOCKOUT_START, RT_NTSCM_LP_LOCKOUT_START); 1185 WriteRT_fld (fld_LOCKOUT_END, RT_NTSCM_LP_LOCKOUT_END); 1186 WriteRT_fld (fld_CH_DTO_INC, RT_NTSCM_CH_DTO_INC); 1187 WriteRT_fld (fld_PLL_SGAIN, RT_NTSCM_CH_PLL_SGAIN); 1188 WriteRT_fld (fld_PLL_FGAIN, RT_NTSCM_CH_PLL_FGAIN); 1189 1190 WriteRT_fld (fld_CH_HEIGHT, RT_NTSCM_CH_HEIGHT); 1191 WriteRT_fld (fld_CH_KILL_LEVEL, RT_NTSCM_CH_KILL_LEVEL); 1192 1193 WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_NTSCM_CH_AGC_ERROR_LIM); 1194 WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_NTSCM_CH_AGC_FILTER_EN); 1195 WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_NTSCM_CH_AGC_LOOP_SPEED); 1196 1197 WriteRT_fld (fld_VS_FIELD_BLANK_START, RT_NTSCM_VS_FIELD_BLANK_START); 1198 WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_NTSCM_VS_FIELD_BLANK_END); 1199 1200 WriteRT_fld (fld_H_ACTIVE_START, RT_NTSCM_H_ACTIVE_START); 1201 WriteRT_fld (fld_H_ACTIVE_END, RT_NTSCM_H_ACTIVE_END); 1202 1203 WriteRT_fld (fld_V_ACTIVE_START, RT_NTSCM_V_ACTIVE_START); 1204 WriteRT_fld (fld_V_ACTIVE_END, RT_NTSCM_V_ACTIVE_END); 1205 1206 WriteRT_fld (fld_H_VBI_WIND_START, RT_NTSCM_H_VBI_WIND_START); 1207 WriteRT_fld (fld_H_VBI_WIND_END, RT_NTSCM_H_VBI_WIND_END); 1208 1209 WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); 1210 WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); 1211 1212 WriteRT_fld (fld_UV_INT_START, (uint8_t)((0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32)); 1213 1214 WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_NTSCM_VSYNC_INT_TRIGGER); 1215 WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_NTSCM_VSYNC_INT_HOLD); 1216 1217 switch (wStandard & 0xFF00) 1218 { 1219 case (extPAL_M): 1220 case (extNONE): 1221 case (extNTSC): 1222 WriteRT_fld (fld_CR_BURST_GAIN, RT_NTSCM_CR_BURST_GAIN); 1223 WriteRT_fld (fld_CB_BURST_GAIN, RT_NTSCM_CB_BURST_GAIN); 1224 1225 WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_NTSCM_CRDR_ACTIVE_GAIN); 1226 WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_NTSCM_CBDB_ACTIVE_GAIN); 1227 1228 WriteRT_fld (fld_VERT_LOCKOUT_START, RT_NTSCM_VERT_LOCKOUT_START); 1229 WriteRT_fld (fld_VERT_LOCKOUT_END, RT_NTSCM_VERT_LOCKOUT_END); 1230 1231 break; 1232 case (extNTSC_J): 1233 WriteRT_fld (fld_CR_BURST_GAIN, RT_NTSCJ_CR_BURST_GAIN); 1234 WriteRT_fld (fld_CB_BURST_GAIN, RT_NTSCJ_CB_BURST_GAIN); 1235 1236 WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_NTSCJ_CRDR_ACTIVE_GAIN); 1237 WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_NTSCJ_CBDB_ACTIVE_GAIN); 1238 1239 WriteRT_fld (fld_CH_HEIGHT, RT_NTSCJ_CH_HEIGHT); 1240 WriteRT_fld (fld_CH_KILL_LEVEL, RT_NTSCJ_CH_KILL_LEVEL); 1241 1242 WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_NTSCJ_CH_AGC_ERROR_LIM); 1243 WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_NTSCJ_CH_AGC_FILTER_EN); 1244 WriteRT_fld (fld_CH_AGC_LOOP_SPEED, RT_NTSCJ_CH_AGC_LOOP_SPEED); 1245 1246 WriteRT_fld (fld_VERT_LOCKOUT_START, RT_NTSCJ_VERT_LOCKOUT_START); 1247 WriteRT_fld (fld_VERT_LOCKOUT_END, RT_NTSCJ_VERT_LOCKOUT_END); 1248 1249 break; 1250 default: 1251 break; 1252 } 1253 break; 1254 case (DEC_PAL): /*PAL GROUP - 525 lines */ 1255 WriteRT_fld (fld_STANDARD_SEL, RT_PAL); 1256 WriteRT_fld (fld_SYNCTIP_REF0, RT_PAL_SYNCTIP_REF0); 1257 WriteRT_fld (fld_SYNCTIP_REF1, RT_PAL_SYNCTIP_REF1); 1258 1259 WriteRT_fld (fld_CLAMP_REF, RT_PAL_CLAMP_REF); 1260 WriteRT_fld (fld_AGC_PEAKWHITE, RT_PAL_PEAKWHITE); 1261 WriteRT_fld (fld_VBI_PEAKWHITE, RT_PAL_VBI_PEAKWHITE); 1262 1263 WriteRT_fld (fld_WPA_THRESHOLD, RT_PAL_WPA_THRESHOLD); 1264 WriteRT_fld (fld_WPA_TRIGGER_LO, RT_PAL_WPA_TRIGGER_LO); 1265 WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_PAL_WPA_TRIGGER_HIGH); 1266 1267 WriteRT_fld (fld_LOCKOUT_START,RT_PAL_LP_LOCKOUT_START); 1268 WriteRT_fld (fld_LOCKOUT_END, RT_PAL_LP_LOCKOUT_END); 1269 WriteRT_fld (fld_CH_DTO_INC, RT_PAL_CH_DTO_INC); 1270 WriteRT_fld (fld_PLL_SGAIN, RT_PAL_CH_PLL_SGAIN); 1271 WriteRT_fld (fld_PLL_FGAIN, RT_PAL_CH_PLL_FGAIN); 1272 1273 WriteRT_fld (fld_CR_BURST_GAIN, RT_PAL_CR_BURST_GAIN); 1274 WriteRT_fld (fld_CB_BURST_GAIN, RT_PAL_CB_BURST_GAIN); 1275 1276 WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_PAL_CRDR_ACTIVE_GAIN); 1277 WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_PAL_CBDB_ACTIVE_GAIN); 1278 1279 WriteRT_fld (fld_CH_HEIGHT, RT_PAL_CH_HEIGHT); 1280 WriteRT_fld (fld_CH_KILL_LEVEL, RT_PAL_CH_KILL_LEVEL); 1281 1282 WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_PAL_CH_AGC_ERROR_LIM); 1283 WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_PAL_CH_AGC_FILTER_EN); 1284 WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_PAL_CH_AGC_LOOP_SPEED); 1285 1286 WriteRT_fld (fld_VERT_LOCKOUT_START, RT_PAL_VERT_LOCKOUT_START); 1287 WriteRT_fld (fld_VERT_LOCKOUT_END, RT_PAL_VERT_LOCKOUT_END); 1288 WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); 1289 1290 WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); 1291 1292 WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); 1293 WriteRT_fld (fld_H_ACTIVE_END, RT_PAL_H_ACTIVE_END); 1294 1295 WriteRT_fld (fld_V_ACTIVE_START, RT_PAL_V_ACTIVE_START); 1296 WriteRT_fld (fld_V_ACTIVE_END, RT_PAL_V_ACTIVE_END); 1297 1298 WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); 1299 WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); 1300 1301 WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); 1302 WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); 1303 1304 /* Magic 0.10 is correct - according to Ivo. Also see SECAM code below */ 1305/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ 1306 WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); 1307 1308 WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); 1309 WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); 1310 1311 break; 1312 case (DEC_SECAM): /*PAL GROUP*/ 1313 WriteRT_fld (fld_STANDARD_SEL, RT_SECAM); 1314 WriteRT_fld (fld_SYNCTIP_REF0, RT_SECAM_SYNCTIP_REF0); 1315 WriteRT_fld (fld_SYNCTIP_REF1, RT_SECAM_SYNCTIP_REF1); 1316 WriteRT_fld (fld_CLAMP_REF, RT_SECAM_CLAMP_REF); 1317 WriteRT_fld (fld_AGC_PEAKWHITE, RT_SECAM_PEAKWHITE); 1318 WriteRT_fld (fld_VBI_PEAKWHITE, RT_SECAM_VBI_PEAKWHITE); 1319 1320 WriteRT_fld (fld_WPA_THRESHOLD, RT_SECAM_WPA_THRESHOLD); 1321 1322 WriteRT_fld (fld_WPA_TRIGGER_LO, RT_SECAM_WPA_TRIGGER_LO); 1323 WriteRT_fld (fld_WPA_TRIGGER_HIGH, RT_SECAM_WPA_TRIGGER_HIGH); 1324 1325 WriteRT_fld (fld_LOCKOUT_START,RT_SECAM_LP_LOCKOUT_START); 1326 WriteRT_fld (fld_LOCKOUT_END, RT_SECAM_LP_LOCKOUT_END); 1327 1328 WriteRT_fld (fld_CH_DTO_INC, RT_SECAM_CH_DTO_INC); 1329 WriteRT_fld (fld_PLL_SGAIN, RT_SECAM_CH_PLL_SGAIN); 1330 WriteRT_fld (fld_PLL_FGAIN, RT_SECAM_CH_PLL_FGAIN); 1331 1332 WriteRT_fld (fld_CR_BURST_GAIN, RT_SECAM_CR_BURST_GAIN); 1333 WriteRT_fld (fld_CB_BURST_GAIN, RT_SECAM_CB_BURST_GAIN); 1334 1335 WriteRT_fld (fld_CRDR_ACTIVE_GAIN, RT_SECAM_CRDR_ACTIVE_GAIN); 1336 WriteRT_fld (fld_CBDB_ACTIVE_GAIN, RT_SECAM_CBDB_ACTIVE_GAIN); 1337 1338 WriteRT_fld (fld_CH_HEIGHT, RT_SECAM_CH_HEIGHT); 1339 WriteRT_fld (fld_CH_KILL_LEVEL, RT_SECAM_CH_KILL_LEVEL); 1340 1341 WriteRT_fld (fld_CH_AGC_ERROR_LIM, RT_SECAM_CH_AGC_ERROR_LIM); 1342 WriteRT_fld (fld_CH_AGC_FILTER_EN, RT_SECAM_CH_AGC_FILTER_EN); 1343 WriteRT_fld (fld_CH_AGC_LOOP_SPEED,RT_SECAM_CH_AGC_LOOP_SPEED); 1344 1345 WriteRT_fld (fld_VERT_LOCKOUT_START, RT_SECAM_VERT_LOCKOUT_START); /*Might not need */ 1346 WriteRT_fld (fld_VERT_LOCKOUT_END, RT_SECAM_VERT_LOCKOUT_END); /* Might not need */ 1347 1348 WriteRT_fld (fld_VS_FIELD_BLANK_START, (uint16_t)RT_PALSEM_VS_FIELD_BLANK_START); 1349 WriteRT_fld (fld_VS_FIELD_BLANK_END, RT_PAL_VS_FIELD_BLANK_END); 1350 1351 WriteRT_fld (fld_H_ACTIVE_START, RT_PAL_H_ACTIVE_START); 1352 WriteRT_fld (fld_H_ACTIVE_END, RT_PAL_H_ACTIVE_END); 1353 1354 WriteRT_fld (fld_V_ACTIVE_START, RT_PAL_V_ACTIVE_START); 1355 WriteRT_fld (fld_V_ACTIVE_END, RT_PAL_V_ACTIVE_END); 1356 1357 WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); 1358 WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); 1359 1360 WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); 1361 WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); 1362 1363 WriteRT_fld (fld_VSYNC_INT_TRIGGER , (uint16_t) RT_PALSEM_VSYNC_INT_TRIGGER); 1364 WriteRT_fld (fld_VSYNC_INT_HOLD, (uint16_t) RT_PALSEM_VSYNC_INT_HOLD); 1365 1366/* WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.12 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); */ 1367 WriteRT_fld (fld_UV_INT_START, (uint8_t)( (0.10 * dbLPeriod * dbFsamp / 2.0) + 0.5 - 32 )); 1368 1369 break; 1370 default: 1371 break; 1372 } 1373 1374 if (t->wConnector == DEC_SVIDEO) 1375 { 1376 1377 RT_SetCombFilter (t, wStandard, RT_SVIDEO); 1378 } 1379 else 1380 { 1381 /* Set up extra (connector and std) registers. */ 1382 RT_SetCombFilter (t, wStandard, RT_COMPOSITE); 1383 } 1384 1385 /* Set the following values according to the formulas */ 1386 WriteRT_fld (fld_HS_LINE_TOTAL, (uint16_t)((dbLPeriod * dbFsamp / 2.0) +0.5)); 1387 /* According to Ivo PAL/SECAM needs different treatment */ 1388 switch(wStandard & 0x00FF) 1389 { 1390 case DEC_PAL: 1391 case DEC_SECAM: 1392 WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.5 * dbSPPeriod * dbFsamp/2.0)); 1393 WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.5 * dbSPPeriod * dbFsamp/2.0)); 1394 WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); 1395 WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(2.39 * dbSPPeriod * dbFsamp / 2.0)); 1396 /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)RT_PAL_FIELD_IDLOCATION); */ 1397 /* According to docs the following value will work right, though the resulting stream deviates 1398 slightly from CCIR..., in particular the value that was before will do nuts to VCRs in 1399 pause/rewind state. */ 1400 WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); 1401 WriteRT_fld (fld_HS_PLL_SGAIN, 2); 1402 break; 1403 case DEC_NTSC: 1404 WriteRT_fld (fld_MIN_PULSE_WIDTH, (uint8_t)(0.75 * dbSPPeriod * dbFsamp/2.0)); 1405 WriteRT_fld (fld_MAX_PULSE_WIDTH, (uint8_t)(1.25 * dbSPPeriod * dbFsamp/2.0)); 1406 WriteRT_fld (fld_WIN_OPEN_LIMIT, (uint16_t)(((dbLPeriod * dbFsamp / 4.0) + 0.5) - 16)); 1407 WriteRT_fld (fld_WIN_CLOSE_LIMIT, (uint16_t)(1.15 * dbSPPeriod * dbFsamp / 2.0)); 1408 /* WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)fld_VS_FIELD_IDLOCATION_def);*/ 1409 /* I think the default value was the same as the one here.. does not hurt to hardcode it */ 1410 WriteRT_fld (fld_VS_FIELD_IDLOCATION, (uint16_t)0x01); 1411 1412 } 1413 1414 WriteRT_fld (fld_VS_FRAME_TOTAL, (uint16_t)(wFrameTotal) + 10); 1415 WriteRT_fld (fld_BLACK_INT_START, (uint8_t)((0.09 * dbLPeriod * dbFsamp / 2.0) - 32 )); 1416 WriteRT_fld (fld_SYNC_TIP_START, (uint16_t)((dbLPeriod * dbFsamp / 2.0 + 0.5) - 28 )); 1417 1418 return; 1419 1420} /* RT_SetStandard ()... */ 1421 1422 1423 1424/**************************************************************************** 1425 * RT_SetCombFilter (uint16_t wStandard, uint16_t wConnector) * 1426 * Function: sets the input comb filter based on the standard and * 1427 * connector being used (composite vs. svideo) * 1428 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1429 * uint16_t wConnector - COMPOSITE, SVIDEO * 1430 * Outputs: NONE * 1431 ****************************************************************************/ 1432static void RT_SetCombFilter (TheatrePtr t, uint16_t wStandard, uint16_t wConnector) 1433{ 1434 uint32_t dwComb_Cntl0=0; 1435 uint32_t dwComb_Cntl1=0; 1436 uint32_t dwComb_Cntl2=0; 1437 uint32_t dwComb_Line_Length=0; 1438 1439 switch (wConnector) 1440 { 1441 case RT_COMPOSITE: 1442 switch (wStandard & 0x00FF) 1443 { 1444 case (DEC_NTSC): 1445 switch (wStandard & 0xFF00) 1446 { 1447 case (extNONE): 1448 case (extNTSC): 1449 case (extNTSC_J): 1450 dwComb_Cntl0= RT_NTSCM_COMB_CNTL0_COMPOSITE; 1451 dwComb_Cntl1= RT_NTSCM_COMB_CNTL1_COMPOSITE; 1452 dwComb_Cntl2= RT_NTSCM_COMB_CNTL2_COMPOSITE; 1453 dwComb_Line_Length= RT_NTSCM_COMB_LENGTH_COMPOSITE; 1454 break; 1455 case (extPAL_M): 1456 dwComb_Cntl0= RT_PALM_COMB_CNTL0_COMPOSITE; 1457 dwComb_Cntl1= RT_PALM_COMB_CNTL1_COMPOSITE; 1458 dwComb_Cntl2= RT_PALM_COMB_CNTL2_COMPOSITE; 1459 dwComb_Line_Length= RT_PALM_COMB_LENGTH_COMPOSITE; 1460 break; 1461 default: 1462 return; 1463 } 1464 break; 1465 case (DEC_PAL): 1466 switch (wStandard & 0xFF00) 1467 { 1468 case (extNONE): 1469 case (extPAL): 1470 dwComb_Cntl0= RT_PAL_COMB_CNTL0_COMPOSITE; 1471 dwComb_Cntl1= RT_PAL_COMB_CNTL1_COMPOSITE; 1472 dwComb_Cntl2= RT_PAL_COMB_CNTL2_COMPOSITE; 1473 dwComb_Line_Length= RT_PAL_COMB_LENGTH_COMPOSITE; 1474 break; 1475 case (extPAL_N): 1476 dwComb_Cntl0= RT_PALN_COMB_CNTL0_COMPOSITE; 1477 dwComb_Cntl1= RT_PALN_COMB_CNTL1_COMPOSITE; 1478 dwComb_Cntl2= RT_PALN_COMB_CNTL2_COMPOSITE; 1479 dwComb_Line_Length= RT_PALN_COMB_LENGTH_COMPOSITE; 1480 break; 1481 default: 1482 return; 1483 } 1484 break; 1485 case (DEC_SECAM): 1486 dwComb_Cntl0= RT_SECAM_COMB_CNTL0_COMPOSITE; 1487 dwComb_Cntl1= RT_SECAM_COMB_CNTL1_COMPOSITE; 1488 dwComb_Cntl2= RT_SECAM_COMB_CNTL2_COMPOSITE; 1489 dwComb_Line_Length= RT_SECAM_COMB_LENGTH_COMPOSITE; 1490 break; 1491 default: 1492 return; 1493 } 1494 break; 1495 case RT_SVIDEO: 1496 switch (wStandard & 0x00FF) 1497 { 1498 case (DEC_NTSC): 1499 switch (wStandard & 0xFF00) 1500 { 1501 case (extNONE): 1502 case (extNTSC): 1503 dwComb_Cntl0= RT_NTSCM_COMB_CNTL0_SVIDEO; 1504 dwComb_Cntl1= RT_NTSCM_COMB_CNTL1_SVIDEO; 1505 dwComb_Cntl2= RT_NTSCM_COMB_CNTL2_SVIDEO; 1506 dwComb_Line_Length= RT_NTSCM_COMB_LENGTH_SVIDEO; 1507 break; 1508 case (extPAL_M): 1509 dwComb_Cntl0= RT_PALM_COMB_CNTL0_SVIDEO; 1510 dwComb_Cntl1= RT_PALM_COMB_CNTL1_SVIDEO; 1511 dwComb_Cntl2= RT_PALM_COMB_CNTL2_SVIDEO; 1512 dwComb_Line_Length= RT_PALM_COMB_LENGTH_SVIDEO; 1513 break; 1514 default: 1515 return; 1516 } 1517 break; 1518 case (DEC_PAL): 1519 switch (wStandard & 0xFF00) 1520 { 1521 case (extNONE): 1522 case (extPAL): 1523 dwComb_Cntl0= RT_PAL_COMB_CNTL0_SVIDEO; 1524 dwComb_Cntl1= RT_PAL_COMB_CNTL1_SVIDEO; 1525 dwComb_Cntl2= RT_PAL_COMB_CNTL2_SVIDEO; 1526 dwComb_Line_Length= RT_PAL_COMB_LENGTH_SVIDEO; 1527 break; 1528 case (extPAL_N): 1529 dwComb_Cntl0= RT_PALN_COMB_CNTL0_SVIDEO; 1530 dwComb_Cntl1= RT_PALN_COMB_CNTL1_SVIDEO; 1531 dwComb_Cntl2= RT_PALN_COMB_CNTL2_SVIDEO; 1532 dwComb_Line_Length= RT_PALN_COMB_LENGTH_SVIDEO; 1533 break; 1534 default: 1535 return; 1536 } 1537 break; 1538 case (DEC_SECAM): 1539 dwComb_Cntl0= RT_SECAM_COMB_CNTL0_SVIDEO; 1540 dwComb_Cntl1= RT_SECAM_COMB_CNTL1_SVIDEO; 1541 dwComb_Cntl2= RT_SECAM_COMB_CNTL2_SVIDEO; 1542 dwComb_Line_Length= RT_SECAM_COMB_LENGTH_SVIDEO; 1543 break; 1544 default: 1545 return; 1546 } 1547 break; 1548 default: 1549 return; 1550 } 1551 1552 WriteRT_fld (fld_COMB_CNTL0, dwComb_Cntl0); 1553 WriteRT_fld (fld_COMB_CNTL1, dwComb_Cntl1); 1554 WriteRT_fld (fld_COMB_CNTL2, dwComb_Cntl2); 1555 WriteRT_fld (fld_COMB_LENGTH, dwComb_Line_Length); 1556 1557 return; 1558 1559} /* RT_SetCombFilter ()... */ 1560 1561 1562/**************************************************************************** 1563 * RT_SetOutputVideoSize (uint16_t wHorzSize, uint16_t wVertSize, * 1564 * uint8_t fCC_On, uint8_t fVBICap_On) * 1565 * Function: sets the output video size for the Rage Theatre video in * 1566 * Inputs: uint16_t wHorzSize - width of output in pixels * 1567 * uint16_t wVertSize - height of output in pixels (lines) * 1568 * uint8_t fCC_On - enable CC output * 1569 * uint8_t fVBI_Cap_On - enable VBI capture * 1570 * Outputs: NONE * 1571 ****************************************************************************/ 1572_X_EXPORT void RT_SetOutputVideoSize (TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On) 1573{ 1574 uint32_t dwHwinStart=0; 1575 uint32_t dwHScaleRatio=0; 1576 uint32_t dwHActiveLength=0; 1577 uint32_t dwVwinStart=0; 1578 uint32_t dwVScaleRatio=0; 1579 uint32_t dwVActiveLength=0; 1580 uint32_t dwTempRatio=0; 1581 uint32_t dwEvenFieldOffset=0; 1582 uint32_t dwOddFieldOffset=0; 1583 uint32_t dwXin=0; 1584 uint32_t dwYin=0; 1585 1586 if (fVBICap_On) 1587 { 1588 WriteRT_fld (fld_VBI_CAPTURE_ENABLE, 1); 1589 WriteRT_fld (fld_VBI_SCALING_RATIO, fld_VBI_SCALING_RATIO_def); 1590 switch (t->wStandard & 0x00FF) 1591 { 1592 case (DEC_NTSC): 1593 WriteRT_fld (fld_H_VBI_WIND_START, RT_NTSCM_H_VBI_WIND_START); 1594 WriteRT_fld (fld_H_VBI_WIND_END, RT_NTSCM_H_VBI_WIND_END); 1595 WriteRT_fld (fld_V_VBI_WIND_START, RT_NTSCM_V_VBI_WIND_START); 1596 WriteRT_fld (fld_V_VBI_WIND_END, RT_NTSCM_V_VBI_WIND_END); 1597 break; 1598 case (DEC_PAL): 1599 WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); 1600 WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); 1601 WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); 1602 WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); 1603 break; 1604 case (DEC_SECAM): 1605 WriteRT_fld (fld_H_VBI_WIND_START, RT_PAL_H_VBI_WIND_START); 1606 WriteRT_fld (fld_H_VBI_WIND_END, RT_PAL_H_VBI_WIND_END); 1607 WriteRT_fld (fld_V_VBI_WIND_START, RT_PAL_V_VBI_WIND_START); 1608 WriteRT_fld (fld_V_VBI_WIND_END, RT_PAL_V_VBI_WIND_END); 1609 break; 1610 default: 1611 break; 1612 } 1613 } 1614 else 1615 { 1616 WriteRT_fld (fld_VBI_CAPTURE_ENABLE, 0); 1617 } 1618 1619 if (t->wInterlaced != RT_DECINTERLACED) 1620 { 1621 wVertSize *= 2; 1622 } 1623 1624 /*1. Calculate Horizontal Scaling ratio:*/ 1625 switch (t->wStandard & 0x00FF) 1626 { 1627 case (DEC_NTSC): 1628 dwHwinStart = RT_NTSCM_H_IN_START; 1629 dwXin = (ReadRT_fld (fld_H_ACTIVE_END) - ReadRT_fld (fld_H_ACTIVE_START)); /*tempscaler*/ 1630 dwXin = RT_NTSC_H_ACTIVE_SIZE; 1631 dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); 1632 dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ 1633 dwHActiveLength = wHorzSize; 1634 break; 1635 case (DEC_PAL): 1636 dwHwinStart = RT_PAL_H_IN_START; 1637 dwXin = RT_PAL_H_ACTIVE_SIZE; 1638 dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); 1639 dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ 1640 dwHActiveLength = wHorzSize; 1641 break; 1642 case (DEC_SECAM): 1643 dwHwinStart = RT_SECAM_H_IN_START; 1644 dwXin = RT_SECAM_H_ACTIVE_SIZE; 1645 dwHScaleRatio = (uint32_t) ((long) dwXin * 65536L / wHorzSize); 1646 dwHScaleRatio = dwHScaleRatio & 0x001FFFFF; /*21 bit number;*/ 1647 dwHActiveLength = wHorzSize; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 /*2. Calculate Vertical Scaling ratio:*/ 1654 switch (t->wStandard & 0x00FF) 1655 { 1656 case (DEC_NTSC): 1657 dwVwinStart = RT_NTSCM_V_IN_START; 1658 /* dwYin = (ReadRT_fld (fld_V_ACTIVE_END) - ReadRT_fld (fld_V_ACTIVE_START)); */ /*tempscaler*/ 1659 dwYin = RT_NTSCM_V_ACTIVE_SIZE; 1660 dwTempRatio = (uint32_t)((long) wVertSize / dwYin); 1661 dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); 1662 dwVScaleRatio = dwVScaleRatio & 0x00000FFF; 1663 dwVActiveLength = wVertSize/2; 1664 break; 1665 case (DEC_PAL): 1666 dwVwinStart = RT_PAL_V_IN_START; 1667 dwYin = RT_PAL_V_ACTIVE_SIZE; 1668 dwTempRatio = (uint32_t)(wVertSize/dwYin); 1669 dwVScaleRatio = (uint32_t)((long)wVertSize * 2048L / dwYin); 1670 dwVScaleRatio = dwVScaleRatio & 0x00000FFF; 1671 dwVActiveLength = wVertSize/2; 1672 break; 1673 case (DEC_SECAM): 1674 dwVwinStart = RT_SECAM_V_IN_START; 1675 dwYin = RT_SECAM_V_ACTIVE_SIZE; 1676 dwTempRatio = (uint32_t) (wVertSize / dwYin); 1677 dwVScaleRatio = (uint32_t) ((long) wVertSize * 2048L / dwYin); 1678 dwVScaleRatio = dwVScaleRatio & 0x00000FFF; 1679 dwVActiveLength = wVertSize/2; 1680 break; 1681 default: 1682 break; 1683 } 1684 1685 /*4. Set up offset based on if interlaced or not:*/ 1686 if (t->wInterlaced == RT_DECINTERLACED) 1687 { 1688 dwEvenFieldOffset = (uint32_t) ((1.0 - ((double) wVertSize / (double) dwYin)) * 512.0); 1689 dwOddFieldOffset = dwEvenFieldOffset; 1690 WriteRT_fld (fld_V_DEINTERLACE_ON, 0x1); 1691 } 1692 else 1693 { 1694 dwEvenFieldOffset = (uint32_t)(dwTempRatio * 512.0); 1695 dwOddFieldOffset = (uint32_t)(2048 - dwEvenFieldOffset); 1696 WriteRT_fld (fld_V_DEINTERLACE_ON, 0x0); 1697 } 1698 1699 /* Set the registers:*/ 1700 WriteRT_fld (fld_H_IN_WIND_START, dwHwinStart); 1701 WriteRT_fld (fld_H_SCALE_RATIO, dwHScaleRatio); 1702 WriteRT_fld (fld_H_OUT_WIND_WIDTH, dwHActiveLength); 1703 1704 WriteRT_fld (fld_V_IN_WIND_START, dwVwinStart); 1705 WriteRT_fld (fld_V_SCALE_RATIO, dwVScaleRatio); 1706 WriteRT_fld (fld_V_OUT_WIND_WIDTH, dwVActiveLength); 1707 1708 WriteRT_fld (fld_EVENF_OFFSET, dwEvenFieldOffset); 1709 WriteRT_fld (fld_ODDF_OFFSET, dwOddFieldOffset); 1710 1711 t->dwHorzScalingRatio = dwHScaleRatio; 1712 t->dwVertScalingRatio = dwVScaleRatio; 1713 1714 return; 1715 1716} /* RT_SetOutputVideoSize ()...*/ 1717 1718 1719 1720/**************************************************************************** 1721 * CalculateCrCbGain (double *CrGain, double *CbGain, uint16_t wStandard) * 1722 * Function: * 1723 * Inputs: double *CrGain - 1724 * double *CbGain - 1725 * uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1726 * Outputs: NONE * 1727 ****************************************************************************/ 1728static void CalculateCrCbGain (TheatrePtr t, double *CrGain, double *CbGain, uint16_t wStandard) 1729{ 1730 #define UVFLTGAIN 1.5 1731 #define FRMAX 280000.0 1732 #define FBMAX 230000.0 1733 1734 double dbSynctipRef0=0, dbFsamp=0, dbLPeriod=0, dbFPeriod=0; 1735 1736 dbSynctipRef0 = ReadRT_fld (fld_SYNCTIP_REF0); 1737 1738 GetStandardConstants (&dbLPeriod, &dbFPeriod, &dbFsamp, wStandard); 1739 1740 *CrGain=0.0; 1741 *CbGain=0.0; 1742 1743 switch (wStandard & 0x00FF) 1744 { 1745 case (DEC_NTSC): /*NTSC GROUP - 480 lines*/ 1746 switch (wStandard & 0xFF00) 1747 { 1748 case (extNONE): 1749 case (extNTSC): 1750 case (extPAL_M): 1751 *CrGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN); 1752 *CbGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN); 1753 break; 1754 case (extNTSC_J): 1755 *CrGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/100.0) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN); 1756 *CbGain = (double)(40.0 / (dbSynctipRef0)) * (100.0/100.0) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN); 1757 break; 1758 default: 1759 return; 1760 } 1761 break; 1762 case (DEC_PAL): 1763 *CrGain = (double)(43.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.877) * ((112.0/70.1)/UVFLTGAIN); 1764 *CbGain = (double)(43.0 / (dbSynctipRef0)) * (100.0/92.5) * (1.0/0.492) * ((112.0/88.6)/UVFLTGAIN); 1765 break; 1766 case (DEC_SECAM): 1767 *CrGain = (double) 32.0 * 32768.0 / FRMAX / (33554432.0 / dbFsamp) * (1.597 / 1.902) / UVFLTGAIN; 1768 *CbGain = (double) 32.0 * 32768.0 / FBMAX / (33554432.0 / dbFsamp) * (1.267 / 1.505) / UVFLTGAIN; 1769 break; 1770 } 1771 1772 return; 1773 1774} /* CalculateCrCbGain ()...*/ 1775 1776 1777/**************************************************************************** 1778 * RT_SetConnector (uint16_t wStandard, int tunerFlag) * 1779 * Function: 1780 * Inputs: uint16_t wStandard - input standard (NTSC, PAL, SECAM) * 1781 * int tunerFlag 1782 * Outputs: NONE * 1783 ****************************************************************************/ 1784void RT_SetConnector (TheatrePtr t, uint16_t wConnector, int tunerFlag) 1785{ 1786 uint32_t dwTempContrast=0; 1787 int i; 1788 long counter; 1789 1790 t->wConnector = wConnector; 1791 1792 /* Get the contrast value - make sure we are viewing a visible line*/ 1793 counter=0; 1794 #if 0 1795 while (!((ReadRT_fld (fld_VS_LINE_COUNT)> 1) && (ReadRT_fld (fld_VS_LINE_COUNT)<20)) && (counter < 100000)){ 1796 #endif 1797 while ((ReadRT_fld (fld_VS_LINE_COUNT)<20) && (counter < 10000)){ 1798 counter++; 1799 } 1800 dwTempContrast = ReadRT_fld (fld_LP_CONTRAST); 1801 if(counter>=10000)xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, 1802 "Rage Theatre: timeout waiting for line count (%u)\n", 1803 (unsigned)ReadRT_fld (fld_VS_LINE_COUNT)); 1804 1805 1806 WriteRT_fld (fld_LP_CONTRAST, 0x0); 1807 1808 switch (wConnector) 1809 { 1810 case (DEC_TUNER): /* Tuner*/ 1811 WriteRT_fld (fld_INPUT_SELECT, t->wTunerConnector ); 1812 WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE); 1813 RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE); 1814 break; 1815 case (DEC_COMPOSITE): /* Comp*/ 1816 WriteRT_fld (fld_INPUT_SELECT, t->wComp0Connector); 1817 WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE); 1818 RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE); 1819 break; 1820 case (DEC_SVIDEO): /* Svideo*/ 1821 WriteRT_fld (fld_INPUT_SELECT, t->wSVideo0Connector); 1822 WriteRT_fld (fld_STANDARD_YC, RT_SVIDEO); 1823 RT_SetCombFilter (t, t->wStandard, RT_SVIDEO); 1824 break; 1825 default: 1826 WriteRT_fld (fld_INPUT_SELECT, t->wComp0Connector); 1827 WriteRT_fld (fld_STANDARD_YC, RT_COMPOSITE); 1828 RT_SetCombFilter (t, t->wStandard, RT_COMPOSITE); 1829 break; 1830 } 1831 1832 t->wConnector = wConnector; 1833 1834 WriteRT_fld (fld_COMB_CNTL1, ReadRT_fld (fld_COMB_CNTL1) ^ 0x100); 1835 WriteRT_fld (fld_COMB_CNTL1, ReadRT_fld (fld_COMB_CNTL1) ^ 0x100); 1836 1837 /* wait at most 1 sec here 1838 VIP bus has a bandwidth of 27MB and it is 8bit. 1839 A single Rage Theatre read should take at least 6 bytes (2 for address one way and 4 for data the other way) 1840 However there are also latencies associated with such reads, plus latencies for PCI accesses. 1841 1842 I guess we should not be doing more than 100000 per second.. At some point 1843 I should really write a program to time this. 1844 */ 1845 i = 100000; 1846 1847 while ((i>=0) && (! ReadRT_fld (fld_HS_GENLOCKED))) 1848 { 1849 i--; 1850 } 1851 if(i<0) xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, "Rage Theatre: waiting for fld_HS_GENLOCKED failed\n"); 1852 /* now we are waiting for a non-visible line.. and there is absolutely no point to wait too long */ 1853 counter = 0; 1854 while (!((ReadRT_fld (fld_VS_LINE_COUNT)> 1) && (ReadRT_fld (fld_VS_LINE_COUNT)<20)) && (counter < 10000)){ 1855 counter++; 1856 } 1857 WriteRT_fld (fld_LP_CONTRAST, dwTempContrast); 1858 if(counter>=10000)xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, 1859 "Rage Theatre: timeout waiting for line count (%u)\n", 1860 (unsigned)ReadRT_fld (fld_VS_LINE_COUNT)); 1861 1862 1863 1864 return; 1865 1866} /* RT_SetConnector ()...*/ 1867 1868 1869_X_EXPORT void InitTheatre(TheatrePtr t) 1870{ 1871 uint32_t data; 1872 1873 1874 /* 0 reset Rage Theatre */ 1875 ShutdownTheatre(t); 1876 usleep(100000); 1877 1878 t->mode=MODE_INITIALIZATION_IN_PROGRESS; 1879 /* 1. 1880 Set the VIN_PLL to NTSC value */ 1881 RT_SetVINClock(t, RT_NTSC); 1882 1883 /* Take VINRST and L54RST out of reset */ 1884 RT_regr (VIP_PLL_CNTL1, &data); 1885 RT_regw (VIP_PLL_CNTL1, data & ~((RT_VINRST_RESET << 1) | (RT_L54RST_RESET << 3))); 1886 RT_regr (VIP_PLL_CNTL1, &data); 1887 1888 /* Set VIN_CLK_SEL to PLL_VIN_CLK */ 1889 RT_regr (VIP_CLOCK_SEL_CNTL, &data); 1890 RT_regw (VIP_CLOCK_SEL_CNTL, data | (RT_PLL_VIN_CLK << 7)); 1891 RT_regr (VIP_CLOCK_SEL_CNTL, &data); 1892 1893 /* 2. 1894 Set HW_DEBUG to 0xF000 before setting the standards registers */ 1895 RT_regw (VIP_HW_DEBUG, 0x0000F000); 1896 1897 /* wait for things to settle */ 1898 usleep(100000); 1899 1900 RT_SetStandard(t, t->wStandard); 1901 1902 /* 3. 1903 Set DVS port to OUTPUT */ 1904 RT_regr (VIP_DVS_PORT_CTRL, &data); 1905 RT_regw (VIP_DVS_PORT_CTRL, data | RT_DVSDIR_OUT); 1906 RT_regr (VIP_DVS_PORT_CTRL, &data); 1907 1908 /* 4. 1909 Set default values for ADC_CNTL */ 1910 RT_regw (VIP_ADC_CNTL, RT_ADC_CNTL_DEFAULT); 1911 1912 /* 5. 1913 Clear the VIN_ASYNC_RST bit */ 1914 RT_regr (VIP_MASTER_CNTL, &data); 1915 RT_regw (VIP_MASTER_CNTL, data & ~0x20); 1916 RT_regr (VIP_MASTER_CNTL, &data); 1917 1918 /* Clear the DVS_ASYNC_RST bit */ 1919 RT_regr (VIP_MASTER_CNTL, &data); 1920 RT_regw (VIP_MASTER_CNTL, data & ~(RT_DVS_ASYNC_RST)); 1921 RT_regr (VIP_MASTER_CNTL, &data); 1922 1923 /* Set the GENLOCK delay */ 1924 RT_regw (VIP_HS_GENLOCKDELAY, 0x10); 1925 1926 RT_regr (fld_DVS_DIRECTION, &data); 1927 RT_regw (fld_DVS_DIRECTION, data & RT_DVSDIR_OUT); 1928/* WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); */ 1929 1930 t->mode=MODE_INITIALIZED_FOR_TV_IN; 1931} 1932 1933 1934_X_EXPORT void ShutdownTheatre(TheatrePtr t) 1935{ 1936 WriteRT_fld (fld_VIN_ASYNC_RST, RT_ASYNC_DISABLE); 1937 WriteRT_fld (fld_VINRST , RT_VINRST_RESET); 1938 WriteRT_fld (fld_ADC_PDWN , RT_ADC_DISABLE); 1939 WriteRT_fld (fld_DVS_DIRECTION, RT_DVSDIR_IN); 1940 t->mode=MODE_UNINITIALIZED; 1941} 1942 1943_X_EXPORT void DumpRageTheatreRegs(TheatrePtr t) 1944{ 1945 int i; 1946 uint32_t data; 1947 1948 for(i=0;i<0x900;i+=4) 1949 { 1950 RT_regr(i, &data); 1951 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, 1952 "register 0x%04x is equal to 0x%08x\n", i, (unsigned)data); 1953 } 1954 1955} 1956 1957void DumpRageTheatreRegsByName(TheatrePtr t) 1958{ 1959 int i; 1960 uint32_t data; 1961 struct { char *name; long addr; } rt_reg_list[]={ 1962 { "ADC_CNTL ", 0x0400 }, 1963 { "ADC_DEBUG ", 0x0404 }, 1964 { "AUD_CLK_DIVIDERS ", 0x00e8 }, 1965 { "AUD_DTO_INCREMENTS ", 0x00ec }, 1966 { "AUD_PLL_CNTL ", 0x00e0 }, 1967 { "AUD_PLL_FINE_CNTL ", 0x00e4 }, 1968 { "CLKOUT_CNTL ", 0x004c }, 1969 { "CLKOUT_GPIO_CNTL ", 0x0038 }, 1970 { "CLOCK_SEL_CNTL ", 0x00d0 }, 1971 { "COMB_CNTL0 ", 0x0440 }, 1972 { "COMB_CNTL1 ", 0x0444 }, 1973 { "COMB_CNTL2 ", 0x0448 }, 1974 { "COMB_LINE_LENGTH ", 0x044c }, 1975 { "CP_ACTIVE_GAIN ", 0x0594 }, 1976 { "CP_AGC_CNTL ", 0x0590 }, 1977 { "CP_BURST_GAIN ", 0x058c }, 1978 { "CP_DEBUG_FORCE ", 0x05b8 }, 1979 { "CP_HUE_CNTL ", 0x0588 }, 1980 { "CP_PLL_CNTL0 ", 0x0580 }, 1981 { "CP_PLL_CNTL1 ", 0x0584 }, 1982 { "CP_PLL_STATUS0 ", 0x0598 }, 1983 { "CP_PLL_STATUS1 ", 0x059c }, 1984 { "CP_PLL_STATUS2 ", 0x05a0 }, 1985 { "CP_PLL_STATUS3 ", 0x05a4 }, 1986 { "CP_PLL_STATUS4 ", 0x05a8 }, 1987 { "CP_PLL_STATUS5 ", 0x05ac }, 1988 { "CP_PLL_STATUS6 ", 0x05b0 }, 1989 { "CP_PLL_STATUS7 ", 0x05b4 }, 1990 { "CP_VERT_LOCKOUT ", 0x05bc }, 1991 { "CRC_CNTL ", 0x02c0 }, 1992 { "CRT_DTO_INCREMENTS ", 0x0394 }, 1993 { "CRT_PLL_CNTL ", 0x00c4 }, 1994 { "CRT_PLL_FINE_CNTL ", 0x00bc }, 1995 { "DECODER_DEBUG_CNTL ", 0x05d4 }, 1996 { "DELAY_ONE_MAP_A ", 0x0114 }, 1997 { "DELAY_ONE_MAP_B ", 0x0118 }, 1998 { "DELAY_ZERO_MAP_A ", 0x011c }, 1999 { "DELAY_ZERO_MAP_B ", 0x0120 }, 2000 { "DFCOUNT ", 0x00a4 }, 2001 { "DFRESTART ", 0x00a8 }, 2002 { "DHRESTART ", 0x00ac }, 2003 { "DVRESTART ", 0x00b0 }, 2004 { "DVS_PORT_CTRL ", 0x0610 }, 2005 { "DVS_PORT_READBACK ", 0x0614 }, 2006 { "FIFOA_CONFIG ", 0x0800 }, 2007 { "FIFOB_CONFIG ", 0x0804 }, 2008 { "FIFOC_CONFIG ", 0x0808 }, 2009 { "FRAME_LOCK_CNTL ", 0x0100 }, 2010 { "GAIN_LIMIT_SETTINGS ", 0x01e4 }, 2011 { "GPIO_CNTL ", 0x0034 }, 2012 { "GPIO_INOUT ", 0x0030 }, 2013 { "HCOUNT ", 0x0090 }, 2014 { "HDISP ", 0x0084 }, 2015 { "HOST_RD_WT_CNTL ", 0x0188 }, 2016 { "HOST_READ_DATA ", 0x0180 }, 2017 { "HOST_WRITE_DATA ", 0x0184 }, 2018 { "HSIZE ", 0x0088 }, 2019 { "HSTART ", 0x008c }, 2020 { "HS_DTOINC ", 0x0484 }, 2021 { "HS_GENLOCKDELAY ", 0x0490 }, 2022 { "HS_MINMAXWIDTH ", 0x048c }, 2023 { "HS_PLINE ", 0x0480 }, 2024 { "HS_PLLGAIN ", 0x0488 }, 2025 { "HS_PLL_ERROR ", 0x04a0 }, 2026 { "HS_PLL_FS_PATH ", 0x04a4 }, 2027 { "HS_PULSE_WIDTH ", 0x049c }, 2028 { "HS_WINDOW_LIMIT ", 0x0494 }, 2029 { "HS_WINDOW_OC_SPEED ", 0x0498 }, 2030 { "HTOTAL ", 0x0080 }, 2031 { "HW_DEBUG ", 0x0010 }, 2032 { "H_ACTIVE_WINDOW ", 0x05c0 }, 2033 { "H_SCALER_CONTROL ", 0x0600 }, 2034 { "H_VBI_WINDOW ", 0x05c8 }, 2035 { "I2C_CNTL ", 0x0054 }, 2036 { "I2C_CNTL_0 ", 0x0020 }, 2037 { "I2C_CNTL_1 ", 0x0024 }, 2038 { "I2C_DATA ", 0x0028 }, 2039 { "I2S_RECEIVE_CNTL ", 0x081c }, 2040 { "I2S_TRANSMIT_CNTL ", 0x0818 }, 2041 { "IIS_TX_CNT_REG ", 0x0824 }, 2042 { "INT_CNTL ", 0x002c }, 2043 { "L54_DTO_INCREMENTS ", 0x00f8 }, 2044 { "L54_PLL_CNTL ", 0x00f0 }, 2045 { "L54_PLL_FINE_CNTL ", 0x00f4 }, 2046 { "LINEAR_GAIN_SETTINGS ", 0x01e8 }, 2047 { "LP_AGC_CLAMP_CNTL0 ", 0x0500 }, 2048 { "LP_AGC_CLAMP_CNTL1 ", 0x0504 }, 2049 { "LP_BLACK_LEVEL ", 0x051c }, 2050 { "LP_BRIGHTNESS ", 0x0508 }, 2051 { "LP_CONTRAST ", 0x050c }, 2052 { "LP_SLICE_LEVEL ", 0x0520 }, 2053 { "LP_SLICE_LIMIT ", 0x0510 }, 2054 { "LP_SYNCTIP_LEVEL ", 0x0524 }, 2055 { "LP_VERT_LOCKOUT ", 0x0528 }, 2056 { "LP_WPA_CNTL0 ", 0x0514 }, 2057 { "LP_WPA_CNTL1 ", 0x0518 }, 2058 { "MASTER_CNTL ", 0x0040 }, 2059 { "MODULATOR_CNTL1 ", 0x0200 }, 2060 { "MODULATOR_CNTL2 ", 0x0204 }, 2061 { "MV_LEVEL_CNTL1 ", 0x0210 }, 2062 { "MV_LEVEL_CNTL2 ", 0x0214 }, 2063 { "MV_MODE_CNTL ", 0x0208 }, 2064 { "MV_STATUS ", 0x0330 }, 2065 { "MV_STRIPE_CNTL ", 0x020c }, 2066 { "NOISE_CNTL0 ", 0x0450 }, 2067 { "PLL_CNTL0 ", 0x00c8 }, 2068 { "PLL_CNTL1 ", 0x00fc }, 2069 { "PLL_TEST_CNTL ", 0x00cc }, 2070 { "PRE_DAC_MUX_CNTL ", 0x0240 }, 2071 { "RGB_CNTL ", 0x0048 }, 2072 { "RIPINTF_PORT_CNTL ", 0x003c }, 2073 { "SCALER_IN_WINDOW ", 0x0618 }, 2074 { "SCALER_OUT_WINDOW ", 0x061c }, 2075 { "SG_BLACK_GATE ", 0x04c0 }, 2076 { "SG_SYNCTIP_GATE ", 0x04c4 }, 2077 { "SG_UVGATE_GATE ", 0x04c8 }, 2078 { "SINGLE_STEP_DATA ", 0x05d8 }, 2079 { "SPDIF_AC3_PREAMBLE ", 0x0814 }, 2080 { "SPDIF_CHANNEL_STAT ", 0x0810 }, 2081 { "SPDIF_PORT_CNTL ", 0x080c }, 2082 { "SPDIF_TX_CNT_REG ", 0x0820 }, 2083 { "STANDARD_SELECT ", 0x0408 }, 2084 { "SW_SCRATCH ", 0x0014 }, 2085 { "SYNC_CNTL ", 0x0050 }, 2086 { "SYNC_LOCK_CNTL ", 0x0104 }, 2087 { "SYNC_SIZE ", 0x00b4 }, 2088 { "THERMO2BIN_STATUS ", 0x040c }, 2089 { "TIMING_CNTL ", 0x01c4 }, 2090 { "TVO_DATA_DELAY_A ", 0x0140 }, 2091 { "TVO_DATA_DELAY_B ", 0x0144 }, 2092 { "TVO_SYNC_PAT_ACCUM ", 0x0108 }, 2093 { "TVO_SYNC_PAT_EXPECT ", 0x0110 }, 2094 { "TVO_SYNC_THRESHOLD ", 0x010c }, 2095 { "TV_DAC_CNTL ", 0x0280 }, 2096 { "TV_DTO_INCREMENTS ", 0x0390 }, 2097 { "TV_PLL_CNTL ", 0x00c0 }, 2098 { "TV_PLL_FINE_CNTL ", 0x00b8 }, 2099 { "UPSAMP_AND_GAIN_CNTL ", 0x01e0 }, 2100 { "UPSAMP_COEFF0_0 ", 0x0340 }, 2101 { "UPSAMP_COEFF0_1 ", 0x0344 }, 2102 { "UPSAMP_COEFF0_2 ", 0x0348 }, 2103 { "UPSAMP_COEFF1_0 ", 0x034c }, 2104 { "UPSAMP_COEFF1_1 ", 0x0350 }, 2105 { "UPSAMP_COEFF1_2 ", 0x0354 }, 2106 { "UPSAMP_COEFF2_0 ", 0x0358 }, 2107 { "UPSAMP_COEFF2_1 ", 0x035c }, 2108 { "UPSAMP_COEFF2_2 ", 0x0360 }, 2109 { "UPSAMP_COEFF3_0 ", 0x0364 }, 2110 { "UPSAMP_COEFF3_1 ", 0x0368 }, 2111 { "UPSAMP_COEFF3_2 ", 0x036c }, 2112 { "UPSAMP_COEFF4_0 ", 0x0370 }, 2113 { "UPSAMP_COEFF4_1 ", 0x0374 }, 2114 { "UPSAMP_COEFF4_2 ", 0x0378 }, 2115 { "UV_ADR ", 0x0300 }, 2116 { "VBI_20BIT_CNTL ", 0x02d0 }, 2117 { "VBI_CC_CNTL ", 0x02c8 }, 2118 { "VBI_CONTROL ", 0x05d0 }, 2119 { "VBI_DTO_CNTL ", 0x02d4 }, 2120 { "VBI_EDS_CNTL ", 0x02cc }, 2121 { "VBI_LEVEL_CNTL ", 0x02d8 }, 2122 { "VBI_SCALER_CONTROL ", 0x060c }, 2123 { "VCOUNT ", 0x009c }, 2124 { "VDISP ", 0x0098 }, 2125 { "VFTOTAL ", 0x00a0 }, 2126 { "VIDEO_PORT_SIG ", 0x02c4 }, 2127 { "VIN_PLL_CNTL ", 0x00d4 }, 2128 { "VIN_PLL_FINE_CNTL ", 0x00d8 }, 2129 { "VIP_COMMAND_STATUS ", 0x0008 }, 2130 { "VIP_REVISION_ID ", 0x000c }, 2131 { "VIP_SUB_VENDOR_DEVICE_ID", 0x0004 }, 2132 { "VIP_VENDOR_DEVICE_ID ", 0x0000 }, 2133 { "VSCALER_CNTL1 ", 0x01c0 }, 2134 { "VSCALER_CNTL2 ", 0x01c8 }, 2135 { "VSYNC_DIFF_CNTL ", 0x03a0 }, 2136 { "VSYNC_DIFF_LIMITS ", 0x03a4 }, 2137 { "VSYNC_DIFF_RD_DATA ", 0x03a8 }, 2138 { "VS_BLANKING_CNTL ", 0x0544 }, 2139 { "VS_COUNTER_CNTL ", 0x054c }, 2140 { "VS_DETECTOR_CNTL ", 0x0540 }, 2141 { "VS_FIELD_ID_CNTL ", 0x0548 }, 2142 { "VS_FRAME_TOTAL ", 0x0550 }, 2143 { "VS_LINE_COUNT ", 0x0554 }, 2144 { "VTOTAL ", 0x0094 }, 2145 { "V_ACTIVE_WINDOW ", 0x05c4 }, 2146 { "V_DEINTERLACE_CONTROL ", 0x0608 }, 2147 { "V_SCALER_CONTROL ", 0x0604 }, 2148 { "V_VBI_WINDOW ", 0x05cc }, 2149 { "Y_FALL_CNTL ", 0x01cc }, 2150 { "Y_RISE_CNTL ", 0x01d0 }, 2151 { "Y_SAW_TOOTH_CNTL ", 0x01d4 }, 2152 {NULL, 0} 2153 }; 2154 2155 for(i=0; rt_reg_list[i].name!=NULL;i++){ 2156 RT_regr(rt_reg_list[i].addr, &data); 2157 xf86DrvMsg(t->VIP->pScrn->scrnIndex, X_INFO, 2158 "register (0x%04lx) %s is equal to 0x%08x\n", 2159 rt_reg_list[i].addr, rt_reg_list[i].name, (unsigned)data); 2160 } 2161 2162} 2163 2164_X_EXPORT void ResetTheatreRegsForNoTVout(TheatrePtr t) 2165{ 2166 RT_regw(VIP_CLKOUT_CNTL, 0x0); 2167 RT_regw(VIP_HCOUNT, 0x0); 2168 RT_regw(VIP_VCOUNT, 0x0); 2169 RT_regw(VIP_DFCOUNT, 0x0); 2170 #if 0 2171 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ 2172 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); 2173 #endif 2174 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0); 2175} 2176 2177 2178_X_EXPORT void ResetTheatreRegsForTVout(TheatrePtr t) 2179{ 2180/* RT_regw(VIP_HW_DEBUG, 0x200); */ 2181/* RT_regw(VIP_INT_CNTL, 0x0); 2182 RT_regw(VIP_GPIO_INOUT, 0x10090000); 2183 RT_regw(VIP_GPIO_INOUT, 0x340b0000); */ 2184/* RT_regw(VIP_MASTER_CNTL, 0x6e8); */ 2185 RT_regw(VIP_CLKOUT_CNTL, 0x29); 2186#if 1 2187 RT_regw(VIP_HCOUNT, 0x1d1); 2188 RT_regw(VIP_VCOUNT, 0x1e3); 2189#else 2190 RT_regw(VIP_HCOUNT, 0x322); 2191 RT_regw(VIP_VCOUNT, 0x151); 2192#endif 2193 RT_regw(VIP_DFCOUNT, 0x01); 2194/* RT_regw(VIP_CLOCK_SEL_CNTL, 0xb7); versus 0x237 <-> 0x2b7 */ 2195 RT_regw(VIP_CLOCK_SEL_CNTL, 0x2b7); /* versus 0x237 <-> 0x2b7 */ 2196 RT_regw(VIP_VIN_PLL_CNTL, 0x60a6039); 2197/* RT_regw(VIP_PLL_CNTL1, 0xacacac74); */ 2198 RT_regw(VIP_FRAME_LOCK_CNTL, 0x0f); 2199/* RT_regw(VIP_ADC_CNTL, 0x02a420a8); 2200 RT_regw(VIP_COMB_CNTL_0, 0x0d438083); 2201 RT_regw(VIP_COMB_CNTL_2, 0x06080102); 2202 RT_regw(VIP_HS_MINMAXWIDTH, 0x462f); 2203 ... 2204 */ 2205/* 2206 RT_regw(VIP_HS_PULSE_WIDTH, 0x359); 2207 RT_regw(VIP_HS_PLL_ERROR, 0xab6); 2208 RT_regw(VIP_HS_PLL_FS_PATH, 0x7fff08f8); 2209 RT_regw(VIP_VS_LINE_COUNT, 0x49b5e005); 2210 */ 2211} 2212