1/*
2 * Modified 1996 by Egbert Eich <eich@xfree86.org>
3 * Modified 1996 by David Bateman <dbateman@club-internet.fr>
4 *
5 * Permission to use, copy, modify, distribute, and sell this software and its
6 * documentation for any purpose is hereby granted without fee, provided that
7 * the above copyright notice appear in all copies and that both that
8 * copyright notice and this permission notice appear in supporting
9 * documentation, and that the name of the authors not be used in
10 * advertising or publicity pertaining to distribution of the software without
11 * specific, written prior permission.  The authors makes no representations
12 * about the suitability of this software for any purpose.  It is provided
13 * "as is" without express or implied warranty.
14 *
15 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
16 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
17 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
19 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
20 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
21 * PERFORMANCE OF THIS SOFTWARE.
22 */
23
24
25
26#ifndef _CT_DRIVER_H_
27#define _CT_DRIVER_H_
28
29#include "ct_pcirename.h"
30#ifdef HAVE_XAA_H
31#include "xaa.h"
32#include "xaalocal.h"		/* XAA internals as we replace some of XAA */
33#endif
34#include "exa.h"
35#include "vbe.h"
36#include "xf86Cursor.h"
37#include "xf86i2c.h"
38#include "xf86DDC.h"
39#include "xf86xv.h"
40#include "vgaHW.h"
41#include <string.h>
42#include <unistd.h>
43
44#include "compat-api.h"
45
46/* Supported chipsets */
47typedef enum {
48    CHIPS_CT65520,
49    CHIPS_CT65525,
50    CHIPS_CT65530,
51    CHIPS_CT65535,
52    CHIPS_CT65540,
53    CHIPS_CT65545,
54    CHIPS_CT65546,
55    CHIPS_CT65548,
56    CHIPS_CT65550,
57    CHIPS_CT65554,
58    CHIPS_CT65555,
59    CHIPS_CT68554,
60    CHIPS_CT69000,
61    CHIPS_CT69030,
62    CHIPS_CT64200,
63    CHIPS_CT64300
64} CHIPSType;
65
66/* Clock related */
67typedef struct {
68    unsigned char msr;		/* Dot Clock Related */
69    unsigned char fcr;
70    unsigned char xr02;
71    unsigned char xr03;
72    unsigned char xr33;
73    unsigned char xr54;
74    unsigned char fr03;
75    int Clock;
76    int FPClock;
77} CHIPSClockReg, *CHIPSClockPtr;
78
79typedef struct {
80    unsigned int ProbedClk;
81    unsigned int Max;		/* Memory Clock Related */
82    unsigned int Clk;
83    unsigned char M;
84    unsigned char N;
85    unsigned char P;
86    unsigned char PSN;
87    unsigned char xrCC;
88    unsigned char xrCD;
89    unsigned char xrCE;
90} CHIPSMemClockReg, *CHIPSMemClockPtr;
91
92#define TYPE_HW 0x01
93#define TYPE_PROGRAMMABLE 0x02
94#define GET_TYPE 0x0F
95#define OLD_STYLE 0x10
96#define NEW_STYLE 0x20
97#define HiQV_STYLE 0x30
98#define WINGINE_1_STYLE 0x40        /* 64300: external clock; 4 clocks    */
99#define WINGINE_2_STYLE 0x50        /* 64300: internal clock; 2 hw-clocks */
100#define GET_STYLE 0xF0
101#define LCD_TEXT_CLK_FREQ 25000	    /* lcd textclock if TYPE_PROGRAMMABLE */
102#define CRT_TEXT_CLK_FREQ 28322     /* crt textclock if TYPE_PROGRAMMABLE */
103#define Fref 14318180               /* The reference clock in Hertz       */
104
105/* The capability flags for the C&T chipsets */
106#define ChipsLinearSupport	0x00000001
107#define ChipsAccelSupport	0x00000002
108#define ChipsFullMMIOSupport	0x00000004
109#define ChipsMMIOSupport	0x00000008
110#define ChipsHDepthSupport	0x00000010
111#define ChipsDPMSSupport	0x00000020
112#define ChipsTMEDSupport	0x00000040
113#define ChipsGammaSupport	0x00000080
114#define ChipsVideoSupport	0x00000100
115#define ChipsDualChannelSupport	0x00000200
116#define ChipsDualRefresh	0x00000400
117#define Chips64BitMemory	0x00000800
118
119/* Options flags for the C&T chipsets */
120#define ChipsHWCursor		0x00001000
121#define ChipsShadowFB		0x00002000
122#define ChipsUseNewFB		0x00008000
123
124/* Architecture type flags */
125#define ChipsHiQV		0x00010000
126#define ChipsWingine		0x00020000
127#define IS_Wingine(x)		((x->Flags) & ChipsWingine)
128#define IS_HiQV(x)		((x->Flags) & ChipsHiQV)
129
130/* Acceleration flags for the C&T chipsets */
131#define ChipsColorTransparency	0x0100000
132#define ChipsImageReadSupport	0x0200000
133
134/* Overlay Transparency Key */
135#define TRANSPARENCY_KEY 255
136
137/* Flag Bus Types */
138#define ChipsUnknown	0
139#define ChipsISA	1
140#define ChipsVLB	2
141#define ChipsPCI	3
142#define ChipsCPUDirect	4
143#define ChipsPIB	5
144#define ChipsMCB	6
145
146/* Macro's to select the 32 bit acceleration registers */
147#define DR(x) cPtr->Regs32[x]	/* For CT655xx naming scheme  */
148#define MR(x) cPtr->Regs32[x]	/* CT655xx MMIO naming scheme */
149#define BR(x) cPtr->Regs32[x]	/* For HiQV naming scheme     */
150#define MMIOmeml(x) *(CARD32 *)(cPtr->MMIOBase + (x))
151#if 0
152#define MMIOmemw(x) *(CARD16 *)(cPtr->MMIOBase + (x))
153#endif
154/* Monitor or flat panel type flags */
155#define ChipsCRT	0x0010
156#define ChipsLCD	0x1000
157#define ChipsLCDProbed	0x2000
158#define ChipsTFT	0x0100
159#define ChipsDS		0x0200
160#define ChipsDD		0x0400
161#define ChipsSS		0x0800
162#define IS_STN(x)	((x) & 0xE00)
163
164/* Dual channel register enable masks */
165#define IOSS_MASK	0xE0
166#define IOSS_BOTH	0x13
167#define IOSS_PIPE_A	0x11
168#define IOSS_PIPE_B	0x1E
169#define MSS_MASK	0xF0
170#define MSS_BOTH	0x0B
171#define MSS_PIPE_A	0x02
172#define MSS_PIPE_B	0x05
173/* Aggregate value of MSS shadow bits -GHB */
174#define MSS_SHADOW  0x07
175
176/* Storage for the registers of the C&T chipsets */
177typedef struct {
178	unsigned char XR[0xFF];
179	unsigned char CR[0x80];
180	unsigned char FR[0x80];
181	unsigned char MR[0x80];
182	CHIPSClockReg Clock;
183} CHIPSRegRec, *CHIPSRegPtr;
184
185/* Storage for the flat panel size */
186typedef struct {
187    int HDisplay;
188    int HRetraceStart;
189    int HRetraceEnd;
190    int HTotal;
191    int VDisplay;
192    int VRetraceStart;
193    int VTotal;
194} CHIPSPanelSizeRec, *CHIPSPanelSizePtr;
195
196/* Some variables needed in the XAA acceleration */
197typedef struct {
198    /* General variable */
199    unsigned int CommandFlags;
200    unsigned int BytesPerPixel;
201    unsigned int BitsPerPixel;
202    unsigned int FbOffset;
203    unsigned int PitchInBytes;
204    unsigned int ScratchAddress;
205    /* 64k for color expansion and imagewrites */
206    unsigned char * BltDataWindow;
207    /* Hardware cursor address */
208    unsigned int CursorAddress;
209    Bool UseHWCursor;
210    /* Boundaries of the pixmap cache */
211    unsigned int CacheStart;
212    unsigned int CacheEnd;
213    /* Storage for pattern mask */
214    int planemask;
215    int srcpitch, srcoffset, xdir, ydir;
216    /* Storage for foreground and background color */
217    int fgColor;
218    int bgColor;
219    /* For the 8x8 pattern fills */
220    int patternyrot;
221    /* For cached stipple fills */
222    int SlotWidth;
223    /* Variables for the 24bpp fill */
224    unsigned char fgpixel;
225    unsigned char bgpixel;
226    unsigned char xorpixel;
227    Bool fastfill;
228    Bool rgb24equal;
229    int fillindex;
230    unsigned int width24bpp;
231    unsigned int color24bpp;
232    unsigned int rop24bpp;
233} CHIPSACLRec, *CHIPSACLPtr;
234#define CHIPSACLPTR(p)	&((CHIPSPtr)((p)->driverPrivate))->Accel
235
236/* Storage for some register values that are messed up by suspend/resumes */
237typedef struct {
238    unsigned char xr02;
239    unsigned char xr03;
240    unsigned char xr14;
241    unsigned char xr15;
242    unsigned char vgaIOBaseFlag;
243} CHIPSSuspendHackRec, *CHIPSSuspendHackPtr;
244
245/* The functions to access the C&T extended registers */
246typedef struct _CHIPSRec *CHIPSPtr;
247typedef CARD8 (*chipsReadXRPtr)(CHIPSPtr cPtr, CARD8 index);
248typedef void (*chipsWriteXRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
249typedef CARD8 (*chipsReadFRPtr)(CHIPSPtr cPtr, CARD8 index);
250typedef void (*chipsWriteFRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
251typedef CARD8 (*chipsReadMRPtr)(CHIPSPtr cPtr, CARD8 index);
252typedef void (*chipsWriteMRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
253typedef CARD8 (*chipsReadMSSPtr)(CHIPSPtr cPtr);
254typedef void (*chipsWriteMSSPtr)(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value);
255typedef CARD8 (*chipsReadIOSSPtr)(CHIPSPtr cPtr);
256typedef void (*chipsWriteIOSSPtr)(CHIPSPtr cPtr, CARD8 value);
257
258/* The privates of the C&T driver */
259#define CHIPSPTR(p)	((CHIPSPtr)((p)->driverPrivate))
260
261
262typedef struct {
263    int			lastInstance;
264    int			refCount;
265    CARD32		masterFbAddress;
266    long		masterFbMapSize;
267    CARD32		slaveFbAddress;
268    long		slaveFbMapSize;
269    int			mastervideoRam;
270    int			slavevideoRam;
271    Bool		masterOpen;
272    Bool		slaveOpen;
273    Bool		masterActive;
274    Bool		slaveActive;
275} CHIPSEntRec, *CHIPSEntPtr;
276
277
278typedef struct _CHIPSRec {
279    pciVideoPtr		PciInfo;
280#ifndef XSERVER_LIBPCIACCESS
281    PCITAG		PciTag;
282#endif
283    int			Chipset;
284    EntityInfoPtr       pEnt;
285    unsigned long	PIOBase;
286    unsigned long	IOAddress;
287    unsigned long	FbAddress;
288    unsigned int	IOBase;
289    unsigned char *	FbBase;
290    unsigned char *	MMIOBase;
291    unsigned char *	MMIOBaseVGA;
292    unsigned char *	MMIOBasePipeA;
293    unsigned char *	MMIOBasePipeB;
294    long		FbMapSize;
295    unsigned char *	ShadowPtr;
296    int			ShadowPitch;
297    int                 Rotate;
298    void		(*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y);
299    int                 FbOffset16;
300    int                 FbSize16;
301    OptionInfoPtr	Options;
302    CHIPSPanelSizeRec	PanelSize;
303    int			FrameBufferSize;
304    Bool		SyncResetIgn;
305    Bool		UseMMIO;
306    Bool		UseFullMMIO;
307    Bool		UseDualChannel;
308    int			Monitor;
309    int			MinClock;
310    int			MaxClock;
311    CHIPSClockReg	SaveClock;		/* Storage for ClockSelect */
312    CHIPSMemClockReg	MemClock;
313    unsigned char	ClockType;
314    unsigned char	CRTClk[4];
315    unsigned char       FPClk[4];
316    int                 FPclock;
317    int                 FPclkInx;
318    int                 CRTclkInx;
319    Bool                FPClkModified;
320    int			ClockMulFactor;
321    int			Rounding;
322    CHIPSSuspendHackRec	SuspendHack;
323    CARD32		PanelType;
324    CHIPSRegRec		ModeReg;
325    CHIPSRegRec		SavedReg;
326    CHIPSRegRec		SavedReg2;
327    vgaRegRec		VgaSavedReg2;
328    unsigned int *	Regs32;
329    unsigned int	Flags;
330    CARD32		Bus;
331#ifdef HAVE_XAA_H
332    XAAInfoRecPtr	AccelInfoRec;
333#endif
334    ExaDriverPtr 	pExa;
335    xf86CursorInfoPtr	CursorInfoRec;
336    CHIPSACLRec		Accel;
337    unsigned int	HWCursorContents;
338    Bool		HWCursorShown;
339    DGAModePtr		DGAModes;
340    int			numDGAModes;
341    Bool		DGAactive;
342    int			DGAViewportStatus;
343    CloseScreenProcPtr	CloseScreen;
344    ScreenBlockHandlerProcPtr BlockHandler;
345    void		(*VideoTimerCallback)(ScrnInfoPtr, Time);
346    int			videoKey;
347    XF86VideoAdaptorPtr	adaptor;
348    int			OverlaySkewX;
349    int			OverlaySkewY;
350    int			VideoZoomMax;
351    Bool		SecondCrtc;
352    CHIPSEntPtr		entityPrivate;
353    unsigned char	storeMSS;
354    unsigned char	storeIOSS;
355#ifdef __arm__
356#ifdef __NetBSD__
357    int			TVMode;
358#endif
359    int			Bank;
360#endif
361    unsigned char       ddc_mask;
362    I2CBusPtr           I2C;
363    vbeInfoPtr          pVbe;
364    chipsReadXRPtr	readXR;
365    chipsWriteXRPtr	writeXR;
366    chipsReadFRPtr	readFR;
367    chipsWriteFRPtr	writeFR;
368    chipsReadMRPtr	readMR;
369    chipsWriteMRPtr	writeMR;
370    chipsReadMSSPtr	readMSS;
371    chipsWriteMSSPtr	writeMSS;
372    chipsReadIOSSPtr	readIOSS;
373    chipsWriteIOSSPtr	writeIOSS;
374    Bool cursorDelay;
375    unsigned int viewportMask;
376    Bool dualEndianAp;
377} CHIPSRec;
378
379typedef struct _CHIPSi2c {
380  unsigned char i2cClockBit;
381  unsigned char i2cDataBit;
382  CHIPSPtr cPtr;
383} CHIPSI2CRec, *CHIPSI2CPtr;
384
385/* External variables */
386extern int ChipsAluConv[];
387extern int ChipsAluConv2[];
388extern int ChipsAluConv3[];
389extern unsigned int ChipsReg32[];
390extern unsigned int ChipsReg32HiQV[];
391
392/* Prototypes */
393
394void CHIPSAdjustFrame(ADJUST_FRAME_ARGS_DECL);
395Bool CHIPSSwitchMode(SWITCH_MODE_ARGS_DECL);
396
397/* video */
398void CHIPSInitVideo(ScreenPtr pScreen);
399void CHIPSResetVideo(ScrnInfoPtr pScrn);
400
401/* banking */
402int CHIPSSetRead(ScreenPtr pScreen, int bank);
403int CHIPSSetWrite(ScreenPtr pScreen, int bank);
404int CHIPSSetReadWrite(ScreenPtr pScreen, int bank);
405int CHIPSSetReadPlanar(ScreenPtr pScreen, int bank);
406int CHIPSSetWritePlanar(ScreenPtr pScreen, int bank);
407int CHIPSSetReadWritePlanar(ScreenPtr pScreen, int bank);
408int CHIPSWINSetRead(ScreenPtr pScreen, int bank);
409int CHIPSWINSetWrite(ScreenPtr pScreen, int bank);
410int CHIPSWINSetReadWrite(ScreenPtr pScreen, int bank);
411int CHIPSWINSetReadPlanar(ScreenPtr pScreen, int bank);
412int CHIPSWINSetWritePlanar(ScreenPtr pScreen, int bank);
413int CHIPSWINSetReadWritePlanar(ScreenPtr pScreen, int bank);
414int CHIPSHiQVSetReadWrite(ScreenPtr pScreen, int bank);
415int CHIPSHiQVSetReadWritePlanar(ScreenPtr pScreen, int bank);
416
417/* acceleration */
418Bool CHIPSAccelInit(ScreenPtr pScreen);
419void CHIPSSync(ScrnInfoPtr pScrn);
420Bool CHIPSMMIOAccelInit(ScreenPtr pScreen);
421void CHIPSMMIOSync(ScrnInfoPtr pScrn);
422Bool CHIPSHiQVAccelInit(ScreenPtr pScreen);
423void CHIPSHiQVSync(ScrnInfoPtr pScrn);
424Bool CHIPSCursorInit(ScreenPtr pScreen);
425Bool CHIPSInitEXA(ScreenPtr pScreen);
426
427/* register access functions */
428void CHIPSSetStdExtFuncs(CHIPSPtr cPtr);
429void CHIPSSetMmioExtFuncs(CHIPSPtr cPtr);
430void CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset);
431
432/* ddc */
433extern void chips_ddc1(ScrnInfoPtr pScrn);
434extern Bool chips_i2cInit(ScrnInfoPtr pScrn);
435
436/* dga */
437Bool CHIPSDGAInit(ScreenPtr pScreen);
438
439/* shadow fb */
440void     chipsRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
441void     chipsRefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
442void     chipsRefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
443void     chipsRefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
444void     chipsRefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
445void     chipsPointerMoved(SCRN_ARG_TYPE arg, int x, int y);
446
447#if X_BYTE_ORDER == X_BIG_ENDIAN
448# define BE_SWAP_APRETURE(pScrn,cPtr) \
449           ((pScrn->bitsPerPixel == 16) && cPtr->dualEndianAp)
450#endif
451
452/*
453 * Some macros for switching display channels. NOTE... It appears that we
454 * can't write to both display channels at the same time, and so the options
455 * MSS_BOTH and IOSS_BOTH should not be used. Need to get around this by set
456 * dual channel mode to pipe A by default and handling multiple channel writes
457 * in ModeInit..
458 */
459
460#define DUALOPEN \
461    {									      \
462        /* Set the IOSS/MSS registers to point to the right register set */   \
463	if (xf86IsEntityShared(pScrn->entityList[0])) { 		      \
464	    if (cPtr->SecondCrtc == TRUE) {				      \
465		cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
466					IOSS_PIPE_B));			      \
467		cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &      \
468					MSS_MASK) | MSS_PIPE_B));	      \
469		cPtrEnt->slaveOpen = TRUE;				      \
470		cPtrEnt->slaveActive = TRUE;				      \
471		cPtrEnt->masterActive = FALSE;				      \
472	    } else {							      \
473		cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
474					IOSS_PIPE_A));			      \
475		cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &      \
476					MSS_MASK) | MSS_PIPE_A));	      \
477		cPtrEnt->masterOpen = TRUE;				      \
478		cPtrEnt->masterActive = TRUE;				      \
479		cPtrEnt->slaveActive = FALSE;				      \
480	    }								      \
481	} else {							      \
482	    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | 	      \
483					IOSS_PIPE_A));			      \
484	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &	      \
485					MSS_MASK) | MSS_PIPE_A));	      \
486	}								      \
487    }
488
489#define DUALREOPEN							      \
490    {									      \
491	if (xf86IsEntityShared(pScrn->entityList[0])) { 		      \
492	    if (cPtr->SecondCrtc == TRUE) {				      \
493		if (! cPtrEnt->slaveActive) {				      \
494		    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |    \
495					IOSS_PIPE_B));			      \
496		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &  \
497					MSS_MASK) | MSS_PIPE_B));	      \
498		    cPtrEnt->slaveOpen = TRUE;				      \
499		    cPtrEnt->slaveActive = TRUE;			      \
500		    cPtrEnt->masterActive = FALSE;			      \
501		}							      \
502	    } else {							      \
503		if (! cPtrEnt->masterActive) {				      \
504		    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |    \
505					IOSS_PIPE_A));			      \
506		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &  \
507					MSS_MASK) | MSS_PIPE_A));	      \
508		    cPtrEnt->masterOpen = TRUE;				      \
509		    cPtrEnt->masterActive = TRUE;			      \
510		    cPtrEnt->slaveActive = FALSE;			      \
511		}							      \
512	    }								      \
513	}								      \
514    }
515
516#define DUALCLOSE							      \
517    {									      \
518	if (! xf86IsEntityShared(pScrn->entityList[0])) {		      \
519	    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
520			       IOSS_PIPE_A));				      \
521	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &	      \
522				MSS_MASK) | MSS_PIPE_A));		      \
523	    chipsHWCursorOff(cPtr, pScrn);				      \
524	    chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg,		      \
525				&cPtr->SavedReg, TRUE);			      \
526	    chipsLock(pScrn);						      \
527	    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
528			       IOSS_PIPE_B));				      \
529	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &	      \
530				MSS_MASK) | MSS_PIPE_B)); 		      \
531	    chipsHWCursorOff(cPtr, pScrn);				      \
532	    chipsRestore(pScrn, &cPtr->VgaSavedReg2, &cPtr->SavedReg2, TRUE); \
533	    cPtr->writeIOSS(cPtr, cPtr->storeIOSS);			      \
534	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS);	      \
535	    chipsLock(pScrn);						      \
536	} else {							      \
537	    chipsHWCursorOff(cPtr, pScrn);				      \
538	    chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,\
539					TRUE);				      \
540	    if (cPtr->SecondCrtc == TRUE) {				      \
541		cPtrEnt->slaveActive = FALSE;				      \
542		cPtrEnt->slaveOpen = FALSE;				      \
543		if (! cPtrEnt->masterActive) {				      \
544		    cPtr->writeIOSS(cPtr, cPtr->storeIOSS);		      \
545		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS);    \
546		    chipsLock(pScrn);					      \
547		}							      \
548	    } else {							      \
549		cPtrEnt->masterActive = FALSE;				      \
550		cPtrEnt->masterOpen = FALSE;				      \
551		if (! cPtrEnt->slaveActive) {				      \
552		    cPtr->writeIOSS(cPtr, cPtr->storeIOSS);		      \
553		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS);    \
554		    chipsLock(pScrn);					      \
555		}							      \
556	    }								      \
557	}								      \
558    }
559
560
561/* To aid debugging of 32 bit register access we make the following defines */
562/*
563#define DEBUG
564#define CT_HW_DEBUG
565*/
566#if defined(DEBUG) & defined(CT_HW_DEBUG)
567#define HW_DEBUG(x) {usleep(500000); ErrorF("Register/Address: 0x%X\n",x);}
568#else
569#define HW_DEBUG(x)
570#endif
571#endif
572