ct_driver.h revision d51ac6bd 
1/*
2 * Modified 1996 by Egbert Eich <eich@xfree86.org>
3 * Modified 1996 by David Bateman <dbateman@club-internet.fr>
4 *
5 * Permission to use, copy, modify, distribute, and sell this software and its
6 * documentation for any purpose is hereby granted without fee, provided that
7 * the above copyright notice appear in all copies and that both that
8 * copyright notice and this permission notice appear in supporting
9 * documentation, and that the name of the authors not be used in
10 * advertising or publicity pertaining to distribution of the software without
11 * specific, written prior permission.  The authors makes no representations
12 * about the suitability of this software for any purpose.  It is provided
13 * "as is" without express or implied warranty.
14 *
15 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
16 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
17 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
18 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
19 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
20 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
21 * PERFORMANCE OF THIS SOFTWARE.
22 */
23
24
25
26#ifndef _CT_DRIVER_H_
27#define _CT_DRIVER_H_
28
29#include "ct_pcirename.h"
30#ifdef HAVE_XAA_H
31#include "xaa.h"
32#include "xaalocal.h"		/* XAA internals as we replace some of XAA */
33#endif
34#include "vbe.h"
35#include "xf86Cursor.h"
36#include "xf86i2c.h"
37#include "xf86DDC.h"
38#include "xf86xv.h"
39#include "vgaHW.h"
40#include <string.h>
41#include <unistd.h>
42
43#include "compat-api.h"
44
45/* Supported chipsets */
46typedef enum {
47    CHIPS_CT65520,
48    CHIPS_CT65525,
49    CHIPS_CT65530,
50    CHIPS_CT65535,
51    CHIPS_CT65540,
52    CHIPS_CT65545,
53    CHIPS_CT65546,
54    CHIPS_CT65548,
55    CHIPS_CT65550,
56    CHIPS_CT65554,
57    CHIPS_CT65555,
58    CHIPS_CT68554,
59    CHIPS_CT69000,
60    CHIPS_CT69030,
61    CHIPS_CT64200,
62    CHIPS_CT64300
63} CHIPSType;
64
65/* Clock related */
66typedef struct {
67    unsigned char msr;		/* Dot Clock Related */
68    unsigned char fcr;
69    unsigned char xr02;
70    unsigned char xr03;
71    unsigned char xr33;
72    unsigned char xr54;
73    unsigned char fr03;
74    int Clock;
75    int FPClock;
76} CHIPSClockReg, *CHIPSClockPtr;
77
78typedef struct {
79    unsigned int ProbedClk;
80    unsigned int Max;		/* Memory Clock Related */
81    unsigned int Clk;
82    unsigned char M;
83    unsigned char N;
84    unsigned char P;
85    unsigned char PSN;
86    unsigned char xrCC;
87    unsigned char xrCD;
88    unsigned char xrCE;
89} CHIPSMemClockReg, *CHIPSMemClockPtr;
90
91#define TYPE_HW 0x01
92#define TYPE_PROGRAMMABLE 0x02
93#define GET_TYPE 0x0F
94#define OLD_STYLE 0x10
95#define NEW_STYLE 0x20
96#define HiQV_STYLE 0x30
97#define WINGINE_1_STYLE 0x40        /* 64300: external clock; 4 clocks    */
98#define WINGINE_2_STYLE 0x50        /* 64300: internal clock; 2 hw-clocks */
99#define GET_STYLE 0xF0
100#define LCD_TEXT_CLK_FREQ 25000	    /* lcd textclock if TYPE_PROGRAMMABLE */
101#define CRT_TEXT_CLK_FREQ 28322     /* crt textclock if TYPE_PROGRAMMABLE */
102#define Fref 14318180               /* The reference clock in Hertz       */
103
104/* The capability flags for the C&T chipsets */
105#define ChipsLinearSupport	0x00000001
106#define ChipsAccelSupport	0x00000002
107#define ChipsFullMMIOSupport	0x00000004
108#define ChipsMMIOSupport	0x00000008
109#define ChipsHDepthSupport	0x00000010
110#define ChipsDPMSSupport	0x00000020
111#define ChipsTMEDSupport	0x00000040
112#define ChipsGammaSupport	0x00000080
113#define ChipsVideoSupport	0x00000100
114#define ChipsDualChannelSupport	0x00000200
115#define ChipsDualRefresh	0x00000400
116#define Chips64BitMemory	0x00000800
117
118/* Options flags for the C&T chipsets */
119#define ChipsHWCursor		0x00001000
120#define ChipsShadowFB		0x00002000
121#define ChipsUseNewFB		0x00008000
122
123/* Architecture type flags */
124#define ChipsHiQV		0x00010000
125#define ChipsWingine		0x00020000
126#define IS_Wingine(x)		((x->Flags) & ChipsWingine)
127#define IS_HiQV(x)		((x->Flags) & ChipsHiQV)
128
129/* Acceleration flags for the C&T chipsets */
130#define ChipsColorTransparency	0x0100000
131#define ChipsImageReadSupport	0x0200000
132
133/* Overlay Transparency Key */
134#define TRANSPARENCY_KEY 255
135
136/* Flag Bus Types */
137#define ChipsUnknown	0
138#define ChipsISA	1
139#define ChipsVLB	2
140#define ChipsPCI	3
141#define ChipsCPUDirect	4
142#define ChipsPIB	5
143#define ChipsMCB	6
144
145/* Macro's to select the 32 bit acceleration registers */
146#define DR(x) cPtr->Regs32[x]	/* For CT655xx naming scheme  */
147#define MR(x) cPtr->Regs32[x]	/* CT655xx MMIO naming scheme */
148#define BR(x) cPtr->Regs32[x]	/* For HiQV naming scheme     */
149#define MMIOmeml(x) *(CARD32 *)(cPtr->MMIOBase + (x))
150#if 0
151#define MMIOmemw(x) *(CARD16 *)(cPtr->MMIOBase + (x))
152#endif
153/* Monitor or flat panel type flags */
154#define ChipsCRT	0x0010
155#define ChipsLCD	0x1000
156#define ChipsLCDProbed	0x2000
157#define ChipsTFT	0x0100
158#define ChipsDS		0x0200
159#define ChipsDD		0x0400
160#define ChipsSS		0x0800
161#define IS_STN(x)	((x) & 0xE00)
162
163/* Dual channel register enable masks */
164#define IOSS_MASK	0xE0
165#define IOSS_BOTH	0x13
166#define IOSS_PIPE_A	0x11
167#define IOSS_PIPE_B	0x1E
168#define MSS_MASK	0xF0
169#define MSS_BOTH	0x0B
170#define MSS_PIPE_A	0x02
171#define MSS_PIPE_B	0x05
172/* Aggregate value of MSS shadow bits -GHB */
173#define MSS_SHADOW  0x07
174
175/* Storage for the registers of the C&T chipsets */
176typedef struct {
177	unsigned char XR[0xFF];
178	unsigned char CR[0x80];
179	unsigned char FR[0x80];
180	unsigned char MR[0x80];
181	CHIPSClockReg Clock;
182} CHIPSRegRec, *CHIPSRegPtr;
183
184/* Storage for the flat panel size */
185typedef struct {
186    int HDisplay;
187    int HRetraceStart;
188    int HRetraceEnd;
189    int HTotal;
190    int VDisplay;
191    int VRetraceStart;
192    int VTotal;
193} CHIPSPanelSizeRec, *CHIPSPanelSizePtr;
194
195/* Some variables needed in the XAA acceleration */
196typedef struct {
197    /* General variable */
198    unsigned int CommandFlags;
199    unsigned int BytesPerPixel;
200    unsigned int BitsPerPixel;
201    unsigned int FbOffset;
202    unsigned int PitchInBytes;
203    unsigned int ScratchAddress;
204    /* 64k for color expansion and imagewrites */
205    unsigned char * BltDataWindow;
206    /* Hardware cursor address */
207    unsigned int CursorAddress;
208    Bool UseHWCursor;
209    /* Boundaries of the pixmap cache */
210    unsigned int CacheStart;
211    unsigned int CacheEnd;
212    /* Storage for pattern mask */
213    int planemask;
214    /* Storage for foreground and background color */
215    int fgColor;
216    int bgColor;
217    /* For the 8x8 pattern fills */
218    int patternyrot;
219    /* For cached stipple fills */
220    int SlotWidth;
221    /* Variables for the 24bpp fill */
222    unsigned char fgpixel;
223    unsigned char bgpixel;
224    unsigned char xorpixel;
225    Bool fastfill;
226    Bool rgb24equal;
227    int fillindex;
228    unsigned int width24bpp;
229    unsigned int color24bpp;
230    unsigned int rop24bpp;
231} CHIPSACLRec, *CHIPSACLPtr;
232#define CHIPSACLPTR(p)	&((CHIPSPtr)((p)->driverPrivate))->Accel
233
234/* Storage for some register values that are messed up by suspend/resumes */
235typedef struct {
236    unsigned char xr02;
237    unsigned char xr03;
238    unsigned char xr14;
239    unsigned char xr15;
240    unsigned char vgaIOBaseFlag;
241} CHIPSSuspendHackRec, *CHIPSSuspendHackPtr;
242
243/* The functions to access the C&T extended registers */
244typedef struct _CHIPSRec *CHIPSPtr;
245typedef CARD8 (*chipsReadXRPtr)(CHIPSPtr cPtr, CARD8 index);
246typedef void (*chipsWriteXRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
247typedef CARD8 (*chipsReadFRPtr)(CHIPSPtr cPtr, CARD8 index);
248typedef void (*chipsWriteFRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
249typedef CARD8 (*chipsReadMRPtr)(CHIPSPtr cPtr, CARD8 index);
250typedef void (*chipsWriteMRPtr)(CHIPSPtr cPtr, CARD8 index, CARD8 value);
251typedef CARD8 (*chipsReadMSSPtr)(CHIPSPtr cPtr);
252typedef void (*chipsWriteMSSPtr)(CHIPSPtr cPtr, vgaHWPtr hwp, CARD8 value);
253typedef CARD8 (*chipsReadIOSSPtr)(CHIPSPtr cPtr);
254typedef void (*chipsWriteIOSSPtr)(CHIPSPtr cPtr, CARD8 value);
255
256/* The privates of the C&T driver */
257#define CHIPSPTR(p)	((CHIPSPtr)((p)->driverPrivate))
258
259
260typedef struct {
261    int			lastInstance;
262    int			refCount;
263    CARD32		masterFbAddress;
264    long		masterFbMapSize;
265    CARD32		slaveFbAddress;
266    long		slaveFbMapSize;
267    int			mastervideoRam;
268    int			slavevideoRam;
269    Bool		masterOpen;
270    Bool		slaveOpen;
271    Bool		masterActive;
272    Bool		slaveActive;
273} CHIPSEntRec, *CHIPSEntPtr;
274
275
276typedef struct _CHIPSRec {
277    pciVideoPtr		PciInfo;
278#ifndef XSERVER_LIBPCIACCESS
279    PCITAG		PciTag;
280#endif
281    int			Chipset;
282    EntityInfoPtr       pEnt;
283    unsigned long	PIOBase;
284    unsigned long	IOAddress;
285    unsigned long	FbAddress;
286    unsigned int	IOBase;
287    unsigned char *	FbBase;
288    unsigned char *	MMIOBase;
289    unsigned char *	MMIOBaseVGA;
290    unsigned char *	MMIOBasePipeA;
291    unsigned char *	MMIOBasePipeB;
292    long		FbMapSize;
293    unsigned char *	ShadowPtr;
294    int			ShadowPitch;
295    int                 Rotate;
296    void		(*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y);
297    int                 FbOffset16;
298    int                 FbSize16;
299    OptionInfoPtr	Options;
300    CHIPSPanelSizeRec	PanelSize;
301    int			FrameBufferSize;
302    Bool		SyncResetIgn;
303    Bool		UseMMIO;
304    Bool		UseFullMMIO;
305    Bool		UseDualChannel;
306    int			Monitor;
307    int			MinClock;
308    int			MaxClock;
309    CHIPSClockReg	SaveClock;		/* Storage for ClockSelect */
310    CHIPSMemClockReg	MemClock;
311    unsigned char	ClockType;
312    unsigned char	CRTClk[4];
313    unsigned char       FPClk[4];
314    int                 FPclock;
315    int                 FPclkInx;
316    int                 CRTclkInx;
317    Bool                FPClkModified;
318    int			ClockMulFactor;
319    int			Rounding;
320    CHIPSSuspendHackRec	SuspendHack;
321    CARD32		PanelType;
322    CHIPSRegRec		ModeReg;
323    CHIPSRegRec		SavedReg;
324    CHIPSRegRec		SavedReg2;
325    vgaRegRec		VgaSavedReg2;
326    unsigned int *	Regs32;
327    unsigned int	Flags;
328    CARD32		Bus;
329#ifdef HAVE_XAA_H
330    XAAInfoRecPtr	AccelInfoRec;
331#endif
332    xf86CursorInfoPtr	CursorInfoRec;
333    CHIPSACLRec		Accel;
334    unsigned int	HWCursorContents;
335    Bool		HWCursorShown;
336    DGAModePtr		DGAModes;
337    int			numDGAModes;
338    Bool		DGAactive;
339    int			DGAViewportStatus;
340    CloseScreenProcPtr	CloseScreen;
341    ScreenBlockHandlerProcPtr BlockHandler;
342    void		(*VideoTimerCallback)(ScrnInfoPtr, Time);
343    int			videoKey;
344    XF86VideoAdaptorPtr	adaptor;
345    int			OverlaySkewX;
346    int			OverlaySkewY;
347    int			VideoZoomMax;
348    Bool		SecondCrtc;
349    CHIPSEntPtr		entityPrivate;
350    unsigned char	storeMSS;
351    unsigned char	storeIOSS;
352#ifdef __arm__
353#ifdef __NetBSD__
354    int			TVMode;
355#endif
356    int			Bank;
357#endif
358    unsigned char       ddc_mask;
359    I2CBusPtr           I2C;
360    vbeInfoPtr          pVbe;
361    chipsReadXRPtr	readXR;
362    chipsWriteXRPtr	writeXR;
363    chipsReadFRPtr	readFR;
364    chipsWriteFRPtr	writeFR;
365    chipsReadMRPtr	readMR;
366    chipsWriteMRPtr	writeMR;
367    chipsReadMSSPtr	readMSS;
368    chipsWriteMSSPtr	writeMSS;
369    chipsReadIOSSPtr	readIOSS;
370    chipsWriteIOSSPtr	writeIOSS;
371    Bool cursorDelay;
372    unsigned int viewportMask;
373    Bool dualEndianAp;
374} CHIPSRec;
375
376typedef struct _CHIPSi2c {
377  unsigned char i2cClockBit;
378  unsigned char i2cDataBit;
379  CHIPSPtr cPtr;
380} CHIPSI2CRec, *CHIPSI2CPtr;
381
382/* External variables */
383extern int ChipsAluConv[];
384extern int ChipsAluConv2[];
385extern int ChipsAluConv3[];
386extern unsigned int ChipsReg32[];
387extern unsigned int ChipsReg32HiQV[];
388
389/* Prototypes */
390
391void CHIPSAdjustFrame(ADJUST_FRAME_ARGS_DECL);
392Bool CHIPSSwitchMode(SWITCH_MODE_ARGS_DECL);
393
394/* video */
395void CHIPSInitVideo(ScreenPtr pScreen);
396void CHIPSResetVideo(ScrnInfoPtr pScrn);
397
398/* banking */
399int CHIPSSetRead(ScreenPtr pScreen, int bank);
400int CHIPSSetWrite(ScreenPtr pScreen, int bank);
401int CHIPSSetReadWrite(ScreenPtr pScreen, int bank);
402int CHIPSSetReadPlanar(ScreenPtr pScreen, int bank);
403int CHIPSSetWritePlanar(ScreenPtr pScreen, int bank);
404int CHIPSSetReadWritePlanar(ScreenPtr pScreen, int bank);
405int CHIPSWINSetRead(ScreenPtr pScreen, int bank);
406int CHIPSWINSetWrite(ScreenPtr pScreen, int bank);
407int CHIPSWINSetReadWrite(ScreenPtr pScreen, int bank);
408int CHIPSWINSetReadPlanar(ScreenPtr pScreen, int bank);
409int CHIPSWINSetWritePlanar(ScreenPtr pScreen, int bank);
410int CHIPSWINSetReadWritePlanar(ScreenPtr pScreen, int bank);
411int CHIPSHiQVSetReadWrite(ScreenPtr pScreen, int bank);
412int CHIPSHiQVSetReadWritePlanar(ScreenPtr pScreen, int bank);
413
414/* acceleration */
415Bool CHIPSAccelInit(ScreenPtr pScreen);
416void CHIPSSync(ScrnInfoPtr pScrn);
417Bool CHIPSMMIOAccelInit(ScreenPtr pScreen);
418void CHIPSMMIOSync(ScrnInfoPtr pScrn);
419Bool CHIPSHiQVAccelInit(ScreenPtr pScreen);
420void CHIPSHiQVSync(ScrnInfoPtr pScrn);
421Bool CHIPSCursorInit(ScreenPtr pScreen);
422
423/* register access functions */
424void CHIPSSetStdExtFuncs(CHIPSPtr cPtr);
425void CHIPSSetMmioExtFuncs(CHIPSPtr cPtr);
426void CHIPSHWSetMmioFuncs(ScrnInfoPtr pScrn, CARD8 *base, int offset);
427
428/* ddc */
429extern void chips_ddc1(ScrnInfoPtr pScrn);
430extern Bool chips_i2cInit(ScrnInfoPtr pScrn);
431
432/* dga */
433Bool CHIPSDGAInit(ScreenPtr pScreen);
434
435/* shadow fb */
436void     chipsRefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
437void     chipsRefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
438void     chipsRefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
439void     chipsRefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
440void     chipsRefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
441void     chipsPointerMoved(SCRN_ARG_TYPE arg, int x, int y);
442
443#if X_BYTE_ORDER == X_BIG_ENDIAN
444# define BE_SWAP_APRETURE(pScrn,cPtr) \
445           ((pScrn->bitsPerPixel == 16) && cPtr->dualEndianAp)
446#endif
447
448/*
449 * Some macros for switching display channels. NOTE... It appears that we
450 * can't write to both display channels at the same time, and so the options
451 * MSS_BOTH and IOSS_BOTH should not be used. Need to get around this by set
452 * dual channel mode to pipe A by default and handling multiple channel writes
453 * in ModeInit..
454 */
455
456#define DUALOPEN \
457    {									      \
458        /* Set the IOSS/MSS registers to point to the right register set */   \
459	if (xf86IsEntityShared(pScrn->entityList[0])) { 		      \
460	    if (cPtr->SecondCrtc == TRUE) {				      \
461		cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
462					IOSS_PIPE_B));			      \
463		cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &      \
464					MSS_MASK) | MSS_PIPE_B));	      \
465		cPtrEnt->slaveOpen = TRUE;				      \
466		cPtrEnt->slaveActive = TRUE;				      \
467		cPtrEnt->masterActive = FALSE;				      \
468	    } else {							      \
469		cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
470					IOSS_PIPE_A));			      \
471		cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &      \
472					MSS_MASK) | MSS_PIPE_A));	      \
473		cPtrEnt->masterOpen = TRUE;				      \
474		cPtrEnt->masterActive = TRUE;				      \
475		cPtrEnt->slaveActive = FALSE;				      \
476	    }								      \
477	} else {							      \
478	    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) | 	      \
479					IOSS_PIPE_A));			      \
480	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &	      \
481					MSS_MASK) | MSS_PIPE_A));	      \
482	}								      \
483    }
484
485#define DUALREOPEN							      \
486    {									      \
487	if (xf86IsEntityShared(pScrn->entityList[0])) { 		      \
488	    if (cPtr->SecondCrtc == TRUE) {				      \
489		if (! cPtrEnt->slaveActive) {				      \
490		    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |    \
491					IOSS_PIPE_B));			      \
492		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &  \
493					MSS_MASK) | MSS_PIPE_B));	      \
494		    cPtrEnt->slaveOpen = TRUE;				      \
495		    cPtrEnt->slaveActive = TRUE;			      \
496		    cPtrEnt->masterActive = FALSE;			      \
497		}							      \
498	    } else {							      \
499		if (! cPtrEnt->masterActive) {				      \
500		    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |    \
501					IOSS_PIPE_A));			      \
502		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &  \
503					MSS_MASK) | MSS_PIPE_A));	      \
504		    cPtrEnt->masterOpen = TRUE;				      \
505		    cPtrEnt->masterActive = TRUE;			      \
506		    cPtrEnt->slaveActive = FALSE;			      \
507		}							      \
508	    }								      \
509	}								      \
510    }
511
512#define DUALCLOSE							      \
513    {									      \
514	if (! xf86IsEntityShared(pScrn->entityList[0])) {		      \
515	    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
516			       IOSS_PIPE_A));				      \
517	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &	      \
518				MSS_MASK) | MSS_PIPE_A));		      \
519	    chipsHWCursorOff(cPtr, pScrn);				      \
520	    chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg,		      \
521				&cPtr->SavedReg, TRUE);			      \
522	    chipsLock(pScrn);						      \
523	    cPtr->writeIOSS(cPtr, ((cPtr->storeIOSS & IOSS_MASK) |	      \
524			       IOSS_PIPE_B));				      \
525	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), ((cPtr->storeMSS &	      \
526				MSS_MASK) | MSS_PIPE_B)); 		      \
527	    chipsHWCursorOff(cPtr, pScrn);				      \
528	    chipsRestore(pScrn, &cPtr->VgaSavedReg2, &cPtr->SavedReg2, TRUE); \
529	    cPtr->writeIOSS(cPtr, cPtr->storeIOSS);			      \
530	    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS);	      \
531	    chipsLock(pScrn);						      \
532	} else {							      \
533	    chipsHWCursorOff(cPtr, pScrn);				      \
534	    chipsRestore(pScrn, &(VGAHWPTR(pScrn))->SavedReg, &cPtr->SavedReg,\
535					TRUE);				      \
536	    if (cPtr->SecondCrtc == TRUE) {				      \
537		cPtrEnt->slaveActive = FALSE;				      \
538		cPtrEnt->slaveOpen = FALSE;				      \
539		if (! cPtrEnt->masterActive) {				      \
540		    cPtr->writeIOSS(cPtr, cPtr->storeIOSS);		      \
541		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS);    \
542		    chipsLock(pScrn);					      \
543		}							      \
544	    } else {							      \
545		cPtrEnt->masterActive = FALSE;				      \
546		cPtrEnt->masterOpen = FALSE;				      \
547		if (! cPtrEnt->slaveActive) {				      \
548		    cPtr->writeIOSS(cPtr, cPtr->storeIOSS);		      \
549		    cPtr->writeMSS(cPtr, VGAHWPTR(pScrn), cPtr->storeMSS);    \
550		    chipsLock(pScrn);					      \
551		}							      \
552	    }								      \
553	}								      \
554    }
555
556
557/* To aid debugging of 32 bit register access we make the following defines */
558/*
559#define DEBUG
560#define CT_HW_DEBUG
561*/
562#if defined(DEBUG) & defined(CT_HW_DEBUG)
563#define HW_DEBUG(x) {usleep(500000); ErrorF("Register/Address: 0x%X\n",x);}
564#else
565#define HW_DEBUG(x)
566#endif
567#endif
568