1 2/************************************************************************** 3 4Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 5All Rights Reserved. 6 7Permission is hereby granted, free of charge, to any person obtaining a 8copy of this software and associated documentation files (the 9"Software"), to deal in the Software without restriction, including 10without limitation the rights to use, copy, modify, merge, publish, 11distribute, sub license, and/or sell copies of the Software, and to 12permit persons to whom the Software is furnished to do so, subject to 13the following conditions: 14 15The above copyright notice and this permission notice (including the 16next paragraph) shall be included in all copies or substantial portions 17of the Software. 18 19THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 23ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 27**************************************************************************/ 28 29/* 30 * Authors: 31 * Kevin E. Martin <kevin@precisioninsight.com> 32 * 33 */ 34 35/* I/O register offsets */ 36#define SRX 0x3C4 37#define GRX 0x3CE 38#define ARX 0x3C0 39#define XRX 0x3D6 40#define MRX 0x3D2 41 42/* VGA Color Palette Registers */ 43#define DACMASK 0x3C6 44#define DACSTATE 0x3C7 45#define DACRX 0x3C7 46#define DACWX 0x3C8 47#define DACDATA 0x3C9 48 49/* CRT Controller Registers (CRX) */ 50#define START_ADDR_HI 0x0C 51#define START_ADDR_LO 0x0D 52#define VERT_SYNC_END 0x11 53#define EXT_VERT_TOTAL 0x30 54#define EXT_VERT_DISPLAY 0x31 55#define EXT_VERT_SYNC_START 0x32 56#define EXT_VERT_BLANK_START 0x33 57#define EXT_HORIZ_TOTAL 0x35 58#define EXT_HORIZ_BLANK 0x39 59#define EXT_START_ADDR 0x40 60#define EXT_START_ADDR_ENABLE 0x80 61#define EXT_OFFSET 0x41 62#define EXT_START_ADDR_HI 0x42 63#define INTERLACE_CNTL 0x70 64#define INTERLACE_ENABLE 0x80 65#define INTERLACE_DISABLE 0x00 66 67/* Miscellaneous Output Register */ 68#define MSR_R 0x3CC 69#define MSR_W 0x3C2 70#define IO_ADDR_SELECT 0x01 71 72#define MDA_BASE 0x3B0 73#define CGA_BASE 0x3D0 74 75/* System Configuration Extension Registers (XRX) */ 76#define IO_CTNL 0x09 77#define EXTENDED_ATTR_CNTL 0x02 78#define EXTENDED_CRTC_CNTL 0x01 79 80#define ADDRESS_MAPPING 0x0A 81#define PACKED_MODE_ENABLE 0x04 82#define LINEAR_MODE_ENABLE 0x02 83#define PAGE_MAPPING_ENABLE 0x01 84 85#define BITBLT_CNTL 0x20 86#define COLEXP_MODE 0x30 87#define COLEXP_8BPP 0x00 88#define COLEXP_16BPP 0x10 89#define COLEXP_24BPP 0x20 90#define COLEXP_RESERVED 0x30 91#define CHIP_RESET 0x02 92#define BITBLT_STATUS 0x01 93 94#define DISPLAY_CNTL 0x40 95#define VGA_WRAP_MODE 0x02 96#define VGA_WRAP_AT_256KB 0x00 97#define VGA_NO_WRAP 0x02 98#define GUI_MODE 0x01 99#define STANDARD_VGA_MODE 0x00 100#define HIRES_MODE 0x01 101 102#define DRAM_ROW_TYPE 0x50 103#define DRAM_ROW_0 0x07 104#define DRAM_ROW_0_SDRAM 0x00 105#define DRAM_ROW_0_EMPTY 0x07 106#define DRAM_ROW_1 0x38 107#define DRAM_ROW_1_SDRAM 0x00 108#define DRAM_ROW_1_EMPTY 0x38 109#define DRAM_ROW_CNTL_LO 0x51 110#define DRAM_CAS_LATENCY 0x10 111#define DRAM_RAS_TIMING 0x08 112#define DRAM_RAS_PRECHARGE 0x04 113#define DRAM_ROW_CNTL_HI 0x52 114#define DRAM_EXT_CNTL 0x53 115#define DRAM_REFRESH_RATE 0x03 116#define DRAM_REFRESH_DISABLE 0x00 117#define DRAM_REFRESH_60HZ 0x01 118#define DRAM_REFRESH_FAST_TEST 0x02 119#define DRAM_REFRESH_RESERVED 0x03 120#define DRAM_TIMING 0x54 121#define DRAM_ROW_BNDRY_0 0x55 122#define DRAM_ROW_BNDRY_1 0x56 123 124#define DPMS_SYNC_SELECT 0x61 125#define VSYNC_CNTL 0x08 126#define VSYNC_ON 0x00 127#define VSYNC_OFF 0x08 128#define HSYNC_CNTL 0x02 129#define HSYNC_ON 0x00 130#define HSYNC_OFF 0x02 131 132#define PIXPIPE_CONFIG_0 0x80 133#define DAC_8_BIT 0x80 134#define DAC_6_BIT 0x00 135#define HW_CURSOR_ENABLE 0x10 136#define EXTENDED_PALETTE 0x01 137 138#define PIXPIPE_CONFIG_1 0x81 139#define DISPLAY_COLOR_MODE 0x0F 140#define DISPLAY_VGA_MODE 0x00 141#define DISPLAY_8BPP_MODE 0x02 142#define DISPLAY_15BPP_MODE 0x04 143#define DISPLAY_16BPP_MODE 0x05 144#define DISPLAY_24BPP_MODE 0x06 145#define DISPLAY_32BPP_MODE 0x07 146 147#define PIXPIPE_CONFIG_2 0x82 148#define DISPLAY_GAMMA_ENABLE 0x08 149#define DISPLAY_GAMMA_DISABLE 0x00 150#define OVERLAY_GAMMA_ENABLE 0x04 151#define OVERLAY_GAMMA_DISABLE 0x00 152 153#define CURSOR_CONTROL 0xA0 154#define CURSOR_ORIGIN_SCREEN 0x00 155#define CURSOR_ORIGIN_DISPLAY 0x10 156#define CURSOR_MODE 0x07 157#define CURSOR_MODE_DISABLE 0x00 158#define CURSOR_MODE_32_4C_AX 0x01 159#define CURSOR_MODE_128_2C 0x02 160#define CURSOR_MODE_128_1C 0x03 161#define CURSOR_MODE_64_3C 0x04 162#define CURSOR_MODE_64_4C_AX 0x05 163#define CURSOR_MODE_64_4C 0x06 164#define CURSOR_MODE_RESERVED 0x07 165#define CURSOR_BASEADDR_LO 0xA2 166#define CURSOR_BASEADDR_HI 0xA3 167#define CURSOR_X_LO 0xA4 168#define CURSOR_X_HI 0xA5 169#define CURSOR_X_POS 0x00 170#define CURSOR_X_NEG 0x80 171#define CURSOR_Y_LO 0xA6 172#define CURSOR_Y_HI 0xA7 173#define CURSOR_Y_POS 0x00 174#define CURSOR_Y_NEG 0x80 175 176#define VCLK2_VCO_M 0xC8 177#define VCLK2_VCO_N 0xC9 178#define VCLK2_VCO_MN_MSBS 0xCA 179#define VCO_N_MSBS 0x30 180#define VCO_M_MSBS 0x03 181#define VCLK2_VCO_DIV_SEL 0xCB 182#define POST_DIV_SELECT 0x70 183#define POST_DIV_1 0x00 184#define POST_DIV_2 0x10 185#define POST_DIV_4 0x20 186#define POST_DIV_8 0x30 187#define POST_DIV_16 0x40 188#define POST_DIV_32 0x50 189#define VCO_LOOP_DIV_BY_4M 0x00 190#define VCO_LOOP_DIV_BY_16M 0x04 191#define REF_CLK_DIV_BY_5 0x02 192#define REF_DIV_4 0x00 193#define REF_DIV_1 0x01 194 195#define PLL_CNTL 0xCE 196#define PLL_MEMCLK_SEL 0x03 197#define PLL_MEMCLK__66667KHZ 0x00 198#define PLL_MEMCLK__75000KHZ 0x01 199#define PLL_MEMCLK__88889KHZ 0x02 200#define PLL_MEMCLK_100000KHZ 0x03 201 202/* Multimedia Extension Registers (MRX) */ 203#define ACQ_CNTL_1 0x02 204#define ACQ_CNTL_2 0x03 205#define FRAME_CAP_MODE 0x01 206#define CONT_CAP_MODE 0x00 207#define SINGLE_CAP_MODE 0x01 208#define ACQ_CNTL_3 0x04 209#define COL_KEY_CNTL_1 0x3C 210#define BLANK_DISP_OVERLAY 0x20 211 212/* FIFOs */ 213#define LP_FIFO 0x1000 214#define HP_FIFO 0x2000 215#define INSTPNT 0x3040 216#define LP_FIFO_COUNT 0x3040 217#define HP_FIFO_COUNT 0x3041 218 219/* FIFO Commands */ 220#define CLIENT 0xE0000000 221#define CLIENT_2D 0x60000000 222 223/* Command Parser Mode Register */ 224#define COMPARS 0x3038 225#define TWO_D_INST_DISABLE 0x08 226#define THREE_D_INST_DISABLE 0x04 227#define STATE_VAR_UPDATE_DISABLE 0x02 228#define PAL_STIP_DISABLE 0x01 229 230/* Interrupt Control Registers */ 231#define IER 0x3030 232#define IIR 0x3032 233#define IMR 0x3034 234#define ISR 0x3036 235#define VMIINTB_EVENT 0x2000 236#define GPIO4_INT 0x1000 237#define DISP_FLIP_EVENT 0x0800 238#define DVD_PORT_DMA 0x0400 239#define DISP_VBLANK 0x0200 240#define FIFO_EMPTY_DMA_DONE 0x0100 241#define INST_PARSER_ERROR 0x0080 242#define USER_DEFINED 0x0040 243#define BREAKPOINT 0x0020 244#define DISP_HORIZ_COUNT 0x0010 245#define DISP_VSYNC 0x0008 246#define CAPTURE_HORIZ_COUNT 0x0004 247#define CAPTURE_VSYNC 0x0002 248#define THREE_D_PIPE_FLUSHED 0x0001 249 250/* FIFO Watermark and Burst Length Control Register */ 251#define FWATER_BLC 0x00006000 252#define LMI_BURST_LENGTH 0x7F000000 253#define LMI_FIFO_WATERMARK 0x003F0000 254#define AGP_BURST_LENGTH 0x00007F00 255#define AGP_FIFO_WATERMARK 0x0000003F 256 257/* BitBLT Registers */ 258#define SRC_DST_PITCH 0x00040000 259#define DST_PITCH 0x1FFF0000 260#define SRC_PITCH 0x00001FFF 261#define COLEXP_BG_COLOR 0x00040004 262#define COLEXP_FG_COLOR 0x00040008 263#define MONO_SRC_CNTL 0x0004000C 264#define MONO_USE_COLEXP 0x00000000 265#define MONO_USE_SRCEXP 0x08000000 266#define MONO_DATA_ALIGN 0x07000000 267#define MONO_BIT_ALIGN 0x01000000 268#define MONO_BYTE_ALIGN 0x02000000 269#define MONO_WORD_ALIGN 0x03000000 270#define MONO_DWORD_ALIGN 0x04000000 271#define MONO_QWORD_ALIGN 0x05000000 272#define MONO_SRC_INIT_DSCRD 0x003F0000 273#define MONO_SRC_RIGHT_CLIP 0x00003F00 274#define MONO_SRC_LEFT_CLIP 0x0000003F 275#define BITBLT_CONTROL 0x00040010 276#define BLTR_STATUS 0x80000000 277#define DYN_DEPTH 0x03000000 278#define DYN_DEPTH_8BPP 0x00000000 279#define DYN_DEPTH_16BPP 0x01000000 280#define DYN_DEPTH_24BPP 0x02000000 281#define DYN_DEPTH_32BPP 0x03000000 /* Not implemented on the i740 */ 282#define DYN_DEPTH_ENABLE 0x00800000 283#define PAT_VERT_ALIGN 0x00700000 284#define SOLID_PAT_SELECT 0x00080000 285#define PAT_IS_IN_COLOR 0x00000000 286#define PAT_IS_MONO 0x00040000 287#define MONO_PAT_TRANSP 0x00020000 288#define COLOR_TRANSP_ROP 0x00000000 289#define COLOR_TRANSP_DST 0x00008000 290#define COLOR_TRANSP_EQ 0x00000000 291#define COLOR_TRANSP_NOT_EQ 0x00010000 292#define COLOR_TRANSP_ENABLE 0x00004000 293#define MONO_SRC_TRANSP 0x00002000 294#define SRC_IS_IN_COLOR 0x00000000 295#define SRC_IS_MONO 0x00001000 296#define SRC_USE_SRC_ADDR 0x00000000 297#define SRC_USE_BLTDATA 0x00000400 298#define BLT_TOP_TO_BOT 0x00000000 299#define BLT_BOT_TO_TOP 0x00000200 300#define BLT_LEFT_TO_RIGHT 0x00000000 301#define BLT_RIGHT_TO_LEFT 0x00000100 302#define BLT_ROP 0x000000FF 303#define BLT_PAT_ADDR 0x00040014 304#define BLT_SRC_ADDR 0x00040018 305#define BLT_DST_ADDR 0x0004001C 306#define BLT_DST_H_W 0x00040020 307#define BLT_DST_HEIGHT 0x1FFF0000 308#define BLT_DST_WIDTH 0x00001FFF 309#define SRCEXP_BG_COLOR 0x00040024 310#define SRCEXP_FG_COLOR 0x00040028 311#define BLTDATA 0x00050000 312 313typedef struct { 314 unsigned int cmd; 315 unsigned int BR00; 316 unsigned int BR01; 317 unsigned int BR02; 318 unsigned int BR03; 319 unsigned int BR04; 320 unsigned int BR05; 321 unsigned int BR06; 322 unsigned int BR07; 323 unsigned int BR09; 324 unsigned int BR0A; 325 unsigned int BR08; 326} GFX2DOPREG_BLTER_FULL_LOAD; 327