1#ifndef INTEL_DRIVER_H 2#define INTEL_DRIVER_H 3 4struct xf86_platform_device; 5 6#define INTEL_VERSION 4000 7#define INTEL_NAME "intel" 8#define INTEL_DRIVER_NAME "intel" 9 10#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR 11#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR 12#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL 13 14#define PCI_CHIP_I810 0x7121 15#define PCI_CHIP_I810_DC100 0x7123 16#define PCI_CHIP_I810_E 0x7125 17#define PCI_CHIP_I815 0x1132 18 19#define PCI_CHIP_I830_M 0x3577 20#define PCI_CHIP_845_G 0x2562 21#define PCI_CHIP_I854 0x358E 22#define PCI_CHIP_I855_GM 0x3582 23#define PCI_CHIP_I865_G 0x2572 24 25#define PCI_CHIP_I915_G 0x2582 26#define PCI_CHIP_I915_GM 0x2592 27#define PCI_CHIP_E7221_G 0x258A 28#define PCI_CHIP_I945_G 0x2772 29#define PCI_CHIP_I945_GM 0x27A2 30#define PCI_CHIP_I945_GME 0x27AE 31#define PCI_CHIP_PINEVIEW_M 0xA011 32#define PCI_CHIP_PINEVIEW_G 0xA001 33#define PCI_CHIP_Q35_G 0x29B2 34#define PCI_CHIP_G33_G 0x29C2 35#define PCI_CHIP_Q33_G 0x29D2 36 37#define PCI_CHIP_G35_G 0x2982 38#define PCI_CHIP_I965_Q 0x2992 39#define PCI_CHIP_I965_G 0x29A2 40#define PCI_CHIP_I946_GZ 0x2972 41#define PCI_CHIP_I965_GM 0x2A02 42#define PCI_CHIP_I965_GME 0x2A12 43#define PCI_CHIP_GM45_GM 0x2A42 44#define PCI_CHIP_G45_E_G 0x2E02 45#define PCI_CHIP_G45_G 0x2E22 46#define PCI_CHIP_Q45_G 0x2E12 47#define PCI_CHIP_G41_G 0x2E32 48#define PCI_CHIP_B43_G 0x2E42 49#define PCI_CHIP_B43_G1 0x2E92 50 51#define PCI_CHIP_IRONLAKE_D_G 0x0042 52#define PCI_CHIP_IRONLAKE_M_G 0x0046 53 54#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 55#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 56#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 57#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 58#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 59#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 60#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A 61 62#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 63#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 64#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152 65#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162 66#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a 67#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a 68 69#define PCI_CHIP_HASWELL_D_GT1 0x0402 70#define PCI_CHIP_HASWELL_D_GT2 0x0412 71#define PCI_CHIP_HASWELL_D_GT3 0x0422 72#define PCI_CHIP_HASWELL_M_GT1 0x0406 73#define PCI_CHIP_HASWELL_M_GT2 0x0416 74#define PCI_CHIP_HASWELL_M_GT3 0x0426 75#define PCI_CHIP_HASWELL_S_GT1 0x040A 76#define PCI_CHIP_HASWELL_S_GT2 0x041A 77#define PCI_CHIP_HASWELL_S_GT3 0x042A 78#define PCI_CHIP_HASWELL_B_GT1 0x040B 79#define PCI_CHIP_HASWELL_B_GT2 0x041B 80#define PCI_CHIP_HASWELL_B_GT3 0x042B 81#define PCI_CHIP_HASWELL_E_GT1 0x040E 82#define PCI_CHIP_HASWELL_E_GT2 0x041E 83#define PCI_CHIP_HASWELL_E_GT3 0x042E 84 85#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02 86#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12 87#define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22 88#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 89#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 90#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 91#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A 92#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A 93#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A 94#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B 95#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B 96#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B 97#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E 98#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E 99#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E 100 101#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02 102#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12 103#define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22 104#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 105#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 106#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 107#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A 108#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A 109#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A 110#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B 111#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B 112#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B 113#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E 114#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E 115#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E 116 117struct intel_device_info { 118 int gen; 119}; 120struct intel_device; 121 122int intel_entity_get_devid(int index); 123 124int intel_open_device(int entity_num, 125 const struct pci_device *pci, 126 struct xf86_platform_device *dev); 127int __intel_peek_fd(ScrnInfoPtr scrn); 128struct intel_device *intel_get_device(ScrnInfoPtr scrn, int *fd); 129int intel_has_render_node(struct intel_device *dev); 130const char *intel_get_client_name(struct intel_device *dev); 131int intel_get_client_fd(struct intel_device *dev); 132int intel_get_device_id(struct intel_device *dev); 133int intel_get_master(struct intel_device *dev); 134int intel_put_master(struct intel_device *dev); 135void intel_put_device(struct intel_device *dev); 136 137void intel_detect_chipset(ScrnInfoPtr scrn, struct intel_device *dev); 138 139#define IS_DEFAULT_ACCEL_METHOD(x) ({ \ 140 enum { NOACCEL, SNA, UXA } default_accel_method__ = DEFAULT_ACCEL_METHOD; \ 141 default_accel_method__ == x; \ 142}) 143 144#define hosted() (0) 145 146#endif /* INTEL_DRIVER_H */ 147