1428d7b3dSmrg/* 2428d7b3dSmrg * Copyright © 2014 Keith Packard 3428d7b3dSmrg * 4428d7b3dSmrg * Permission to use, copy, modify, distribute, and sell this software and its 5428d7b3dSmrg * documentation for any purpose is hereby granted without fee, provided that 6428d7b3dSmrg * the above copyright notice appear in all copies and that both that copyright 7428d7b3dSmrg * notice and this permission notice appear in supporting documentation, and 8428d7b3dSmrg * that the name of the copyright holders not be used in advertising or 9428d7b3dSmrg * publicity pertaining to distribution of the software without specific, 10428d7b3dSmrg * written prior permission. The copyright holders make no representations 11428d7b3dSmrg * about the suitability of this software for any purpose. It is provided "as 12428d7b3dSmrg * is" without express or implied warranty. 13428d7b3dSmrg * 14428d7b3dSmrg * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15428d7b3dSmrg * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16428d7b3dSmrg * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17428d7b3dSmrg * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18428d7b3dSmrg * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19428d7b3dSmrg * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20428d7b3dSmrg * OF THIS SOFTWARE. 21428d7b3dSmrg */ 22428d7b3dSmrg 23428d7b3dSmrg#ifndef _INTEL_UXA_H_ 24428d7b3dSmrg#define _INTEL_UXA_H_ 25428d7b3dSmrg 26428d7b3dSmrg#include "intel_video.h" 27428d7b3dSmrg#include "uxa.h" 28428d7b3dSmrg 29428d7b3dSmrgstruct intel_uxa_pixmap { 30428d7b3dSmrg dri_bo *bo; 31428d7b3dSmrg 32428d7b3dSmrg struct list batch; 33428d7b3dSmrg 34428d7b3dSmrg uint8_t tiling; 35428d7b3dSmrg int8_t busy :2; 36428d7b3dSmrg uint8_t dirty :1; 37428d7b3dSmrg uint8_t offscreen :1; 38428d7b3dSmrg uint8_t pinned :5; 39428d7b3dSmrg#define PIN_SCANOUT 0x1 40428d7b3dSmrg#define PIN_DRI2 0x2 41428d7b3dSmrg#define PIN_DRI3 0x4 42428d7b3dSmrg#define PIN_PRIME 0x8 43428d7b3dSmrg}; 44428d7b3dSmrg 45428d7b3dSmrg#if HAS_DEVPRIVATEKEYREC 46428d7b3dSmrgextern DevPrivateKeyRec uxa_pixmap_index; 47428d7b3dSmrg#else 48428d7b3dSmrgextern int uxa_pixmap_index; 49428d7b3dSmrg#endif 50428d7b3dSmrg 51428d7b3dSmrgstatic inline struct intel_uxa_pixmap *intel_uxa_get_pixmap_private(PixmapPtr pixmap) 52428d7b3dSmrg{ 53428d7b3dSmrg#if HAS_DEVPRIVATEKEYREC 54428d7b3dSmrg return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index); 55428d7b3dSmrg#else 56428d7b3dSmrg return dixLookupPrivate(&pixmap->devPrivates, &uxa_pixmap_index); 57428d7b3dSmrg#endif 58428d7b3dSmrg} 59428d7b3dSmrg 60428d7b3dSmrgstatic inline Bool intel_uxa_pixmap_is_busy(struct intel_uxa_pixmap *priv) 61428d7b3dSmrg{ 62428d7b3dSmrg if (priv->busy == -1) 63428d7b3dSmrg priv->busy = drm_intel_bo_busy(priv->bo); 64428d7b3dSmrg return priv->busy; 65428d7b3dSmrg} 66428d7b3dSmrg 67428d7b3dSmrgstatic inline void intel_uxa_set_pixmap_private(PixmapPtr pixmap, struct intel_uxa_pixmap *intel) 68428d7b3dSmrg{ 69428d7b3dSmrg dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel); 70428d7b3dSmrg} 71428d7b3dSmrg 72428d7b3dSmrgstatic inline Bool intel_uxa_pixmap_is_dirty(PixmapPtr pixmap) 73428d7b3dSmrg{ 74428d7b3dSmrg return pixmap && intel_uxa_get_pixmap_private(pixmap)->dirty; 75428d7b3dSmrg} 76428d7b3dSmrg 77428d7b3dSmrgstatic inline Bool intel_uxa_pixmap_tiled(PixmapPtr pixmap) 78428d7b3dSmrg{ 79428d7b3dSmrg return intel_uxa_get_pixmap_private(pixmap)->tiling != I915_TILING_NONE; 80428d7b3dSmrg} 81428d7b3dSmrg 82428d7b3dSmrgdri_bo *intel_uxa_get_pixmap_bo(PixmapPtr pixmap); 83428d7b3dSmrgvoid intel_uxa_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo); 84428d7b3dSmrg 85428d7b3dSmrgBool intel_uxa_init(ScreenPtr pScreen); 86428d7b3dSmrgBool intel_uxa_create_screen_resources(ScreenPtr pScreen); 87428d7b3dSmrgvoid intel_uxa_block_handler(intel_screen_private *intel); 88428d7b3dSmrg 89428d7b3dSmrgstatic inline Bool intel_uxa_pixmap_is_offscreen(PixmapPtr pixmap) 90428d7b3dSmrg{ 91428d7b3dSmrg struct intel_uxa_pixmap *priv = intel_uxa_get_pixmap_private(pixmap); 92428d7b3dSmrg return priv && priv->offscreen; 93428d7b3dSmrg} 94428d7b3dSmrg 95428d7b3dSmrg/* Batchbuffer support macros and functions */ 96428d7b3dSmrg#include "intel_batchbuffer.h" 97428d7b3dSmrg 98428d7b3dSmrg/* I830 specific functions */ 99428d7b3dSmrgextern void IntelEmitInvarientState(ScrnInfoPtr scrn); 100428d7b3dSmrgextern void I830EmitInvarientState(ScrnInfoPtr scrn); 101428d7b3dSmrgextern void I915EmitInvarientState(ScrnInfoPtr scrn); 102428d7b3dSmrg 103428d7b3dSmrgextern void I830EmitFlush(ScrnInfoPtr scrn); 104428d7b3dSmrg 105428d7b3dSmrg/* i830_render.c */ 106428d7b3dSmrgBool i830_check_composite(int op, 107428d7b3dSmrg PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 108428d7b3dSmrg int width, int height); 109428d7b3dSmrgBool i830_check_composite_target(PixmapPtr pixmap); 110428d7b3dSmrgBool i830_check_composite_texture(ScreenPtr screen, PicturePtr picture); 111428d7b3dSmrgBool i830_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 112428d7b3dSmrg PicturePtr dest, PixmapPtr sourcecPixmap, 113428d7b3dSmrg PixmapPtr maskPixmap, PixmapPtr destPixmap); 114428d7b3dSmrgvoid i830_composite(PixmapPtr dest, int srcX, int srcY, 115428d7b3dSmrg int maskX, int maskY, int dstX, int dstY, int w, int h); 116428d7b3dSmrgvoid i830_vertex_flush(intel_screen_private *intel); 117428d7b3dSmrg 118428d7b3dSmrg/* i915_render.c */ 119428d7b3dSmrgBool i915_check_composite(int op, 120428d7b3dSmrg PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 121428d7b3dSmrg int width, int height); 122428d7b3dSmrgBool i915_check_composite_target(PixmapPtr pixmap); 123428d7b3dSmrgBool i915_check_composite_texture(ScreenPtr screen, PicturePtr picture); 124428d7b3dSmrgBool i915_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 125428d7b3dSmrg PicturePtr dest, PixmapPtr sourcecPixmap, 126428d7b3dSmrg PixmapPtr maskPixmap, PixmapPtr destPixmap); 127428d7b3dSmrgvoid i915_composite(PixmapPtr dest, int srcX, int srcY, 128428d7b3dSmrg int maskX, int maskY, int dstX, int dstY, int w, int h); 129428d7b3dSmrgvoid i915_vertex_flush(intel_screen_private *intel); 130428d7b3dSmrgvoid i915_batch_commit_notify(intel_screen_private *intel); 131428d7b3dSmrgvoid i830_batch_commit_notify(intel_screen_private *intel); 132428d7b3dSmrg/* i965_render.c */ 133428d7b3dSmrgunsigned int gen4_render_state_size(ScrnInfoPtr scrn); 134428d7b3dSmrgvoid gen4_render_state_init(ScrnInfoPtr scrn); 135428d7b3dSmrgvoid gen4_render_state_cleanup(ScrnInfoPtr scrn); 136428d7b3dSmrgBool i965_check_composite(int op, 137428d7b3dSmrg PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 138428d7b3dSmrg int width, int height); 139428d7b3dSmrgBool i965_check_composite_texture(ScreenPtr screen, PicturePtr picture); 140428d7b3dSmrgBool i965_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 141428d7b3dSmrg PicturePtr dest, PixmapPtr sourcecPixmap, 142428d7b3dSmrg PixmapPtr maskPixmap, PixmapPtr destPixmap); 143428d7b3dSmrgvoid i965_composite(PixmapPtr dest, int srcX, int srcY, 144428d7b3dSmrg int maskX, int maskY, int dstX, int dstY, int w, int h); 145428d7b3dSmrg 146428d7b3dSmrgvoid i965_vertex_flush(intel_screen_private *intel); 147428d7b3dSmrgvoid i965_batch_flush(intel_screen_private *intel); 148428d7b3dSmrgvoid i965_batch_commit_notify(intel_screen_private *intel); 149428d7b3dSmrg 150428d7b3dSmrg/* i965_3d.c */ 151428d7b3dSmrgvoid gen6_upload_invariant_states(intel_screen_private *intel); 152428d7b3dSmrgvoid gen6_upload_viewport_state_pointers(intel_screen_private *intel, 153428d7b3dSmrg drm_intel_bo *cc_vp_bo); 154428d7b3dSmrgvoid gen7_upload_viewport_state_pointers(intel_screen_private *intel, 155428d7b3dSmrg drm_intel_bo *cc_vp_bo); 156428d7b3dSmrgvoid gen6_upload_urb(intel_screen_private *intel); 157428d7b3dSmrgvoid gen7_upload_urb(intel_screen_private *intel); 158428d7b3dSmrgvoid gen6_upload_cc_state_pointers(intel_screen_private *intel, 159428d7b3dSmrg drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, 160428d7b3dSmrg drm_intel_bo *depth_stencil_bo, 161428d7b3dSmrg uint32_t blend_offset); 162428d7b3dSmrgvoid gen7_upload_cc_state_pointers(intel_screen_private *intel, 163428d7b3dSmrg drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, 164428d7b3dSmrg drm_intel_bo *depth_stencil_bo, 165428d7b3dSmrg uint32_t blend_offset); 166428d7b3dSmrgvoid gen6_upload_sampler_state_pointers(intel_screen_private *intel, 167428d7b3dSmrg drm_intel_bo *sampler_bo); 168428d7b3dSmrgvoid gen7_upload_sampler_state_pointers(intel_screen_private *intel, 169428d7b3dSmrg drm_intel_bo *sampler_bo); 170428d7b3dSmrgvoid gen7_upload_bypass_states(intel_screen_private *intel); 171428d7b3dSmrgvoid gen6_upload_gs_state(intel_screen_private *intel); 172428d7b3dSmrgvoid gen6_upload_vs_state(intel_screen_private *intel); 173428d7b3dSmrgvoid gen6_upload_clip_state(intel_screen_private *intel); 174428d7b3dSmrgvoid gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); 175428d7b3dSmrgvoid gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); 176428d7b3dSmrgvoid gen6_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); 177428d7b3dSmrgvoid gen7_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); 178428d7b3dSmrgvoid gen6_upload_depth_buffer_state(intel_screen_private *intel); 179428d7b3dSmrgvoid gen7_upload_depth_buffer_state(intel_screen_private *intel); 180428d7b3dSmrg 181428d7b3dSmrgBool intel_uxa_transform_is_affine(PictTransformPtr t); 182428d7b3dSmrg 183428d7b3dSmrgBool 184428d7b3dSmrgintel_uxa_get_transformed_coordinates(int x, int y, PictTransformPtr transform, 185428d7b3dSmrg float *x_out, float *y_out); 186428d7b3dSmrg 187428d7b3dSmrgBool 188428d7b3dSmrgintel_uxa_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, 189428d7b3dSmrg float *x_out, float *y_out, float *z_out); 190428d7b3dSmrg 191428d7b3dSmrgstatic inline void 192428d7b3dSmrgintel_uxa_debug_fallback(ScrnInfoPtr scrn, const char *format, ...) _X_ATTRIBUTE_PRINTF(2, 3); 193428d7b3dSmrg 194428d7b3dSmrgstatic inline void 195428d7b3dSmrgintel_uxa_debug_fallback(ScrnInfoPtr scrn, const char *format, ...) 196428d7b3dSmrg{ 197428d7b3dSmrg intel_screen_private *intel = intel_get_screen_private(scrn); 198428d7b3dSmrg va_list ap; 199428d7b3dSmrg 200428d7b3dSmrg va_start(ap, format); 201428d7b3dSmrg if (intel->fallback_debug) { 202428d7b3dSmrg xf86DrvMsg(scrn->scrnIndex, X_INFO, "fallback: "); 203428d7b3dSmrg LogVMessageVerb(X_INFO, 1, format, ap); 204428d7b3dSmrg } 205428d7b3dSmrg va_end(ap); 206428d7b3dSmrg} 207428d7b3dSmrg 208428d7b3dSmrgstatic inline Bool 209428d7b3dSmrgintel_uxa_check_pitch_2d(PixmapPtr pixmap) 210428d7b3dSmrg{ 211428d7b3dSmrg uint32_t pitch = intel_pixmap_pitch(pixmap); 212428d7b3dSmrg if (pitch > KB(32)) { 213428d7b3dSmrg ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 214428d7b3dSmrg intel_uxa_debug_fallback(scrn, "pitch exceeds 2d limit 32K\n"); 215428d7b3dSmrg return FALSE; 216428d7b3dSmrg } 217428d7b3dSmrg return TRUE; 218428d7b3dSmrg} 219428d7b3dSmrg 220428d7b3dSmrg/* For pre-965 chip only, as they have 8KB limit for 3D */ 221428d7b3dSmrgstatic inline Bool 222428d7b3dSmrgintel_uxa_check_pitch_3d(PixmapPtr pixmap) 223428d7b3dSmrg{ 224428d7b3dSmrg uint32_t pitch = intel_pixmap_pitch(pixmap); 225428d7b3dSmrg if (pitch > KB(8)) { 226428d7b3dSmrg ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 227428d7b3dSmrg intel_uxa_debug_fallback(scrn, "pitch exceeds 3d limit 8K\n"); 228428d7b3dSmrg return FALSE; 229428d7b3dSmrg } 230428d7b3dSmrg return TRUE; 231428d7b3dSmrg} 232428d7b3dSmrg 233428d7b3dSmrg/** 234428d7b3dSmrg * Little wrapper around drm_intel_bo_reloc to return the initial value you 235428d7b3dSmrg * should stuff into the relocation entry. 236428d7b3dSmrg * 237428d7b3dSmrg * If only we'd done this before settling on the library API. 238428d7b3dSmrg */ 239428d7b3dSmrgstatic inline uint32_t 240428d7b3dSmrgintel_uxa_emit_reloc(drm_intel_bo * bo, uint32_t offset, 241428d7b3dSmrg drm_intel_bo * target_bo, uint32_t target_offset, 242428d7b3dSmrg uint32_t read_domains, uint32_t write_domain) 243428d7b3dSmrg{ 244428d7b3dSmrg drm_intel_bo_emit_reloc(bo, offset, target_bo, target_offset, 245428d7b3dSmrg read_domains, write_domain); 246428d7b3dSmrg 247428d7b3dSmrg return target_bo->offset + target_offset; 248428d7b3dSmrg} 249428d7b3dSmrg 250428d7b3dSmrgstatic inline drm_intel_bo *intel_uxa_bo_alloc_for_data(intel_screen_private *intel, 251428d7b3dSmrg const void *data, 252428d7b3dSmrg unsigned int size, 253428d7b3dSmrg const char *name) 254428d7b3dSmrg{ 255428d7b3dSmrg drm_intel_bo *bo; 256428d7b3dSmrg int ret; 257428d7b3dSmrg 258428d7b3dSmrg bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096); 259428d7b3dSmrg assert(bo); 260428d7b3dSmrg 261428d7b3dSmrg ret = drm_intel_bo_subdata(bo, 0, size, data); 262428d7b3dSmrg assert(ret == 0); 263428d7b3dSmrg 264428d7b3dSmrg return bo; 265428d7b3dSmrg (void)ret; 266428d7b3dSmrg} 267428d7b3dSmrg 268428d7b3dSmrgvoid intel_uxa_debug_flush(ScrnInfoPtr scrn); 269428d7b3dSmrg 270428d7b3dSmrg 271428d7b3dSmrgBool intel_uxa_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, 272428d7b3dSmrg int num_bos); 273428d7b3dSmrg 274428d7b3dSmrgXF86VideoAdaptorPtr intel_uxa_video_setup_image_textured(ScreenPtr screen); 275428d7b3dSmrg 276428d7b3dSmrgvoid I915DisplayVideoTextured(ScrnInfoPtr scrn, 277428d7b3dSmrg intel_adaptor_private *adaptor_priv, 278428d7b3dSmrg int id, RegionPtr dstRegion, short width, 279428d7b3dSmrg short height, int video_pitch, int video_pitch2, 280428d7b3dSmrg short src_w, short src_h, 281428d7b3dSmrg short drw_w, short drw_h, PixmapPtr pixmap); 282428d7b3dSmrg 283428d7b3dSmrgvoid I965DisplayVideoTextured(ScrnInfoPtr scrn, 284428d7b3dSmrg intel_adaptor_private *adaptor_priv, 285428d7b3dSmrg int id, RegionPtr dstRegion, short width, 286428d7b3dSmrg short height, int video_pitch, int video_pitch2, 287428d7b3dSmrg short src_w, short src_h, 288428d7b3dSmrg short drw_w, short drw_h, PixmapPtr pixmap); 289428d7b3dSmrg 290428d7b3dSmrgvoid Gen6DisplayVideoTextured(ScrnInfoPtr scrn, 291428d7b3dSmrg intel_adaptor_private *adaptor_priv, 292428d7b3dSmrg int id, RegionPtr dstRegion, short width, 293428d7b3dSmrg short height, int video_pitch, int video_pitch2, 294428d7b3dSmrg short src_w, short src_h, 295428d7b3dSmrg short drw_w, short drw_h, PixmapPtr pixmap); 296428d7b3dSmrg 297428d7b3dSmrgvoid i965_free_video(ScrnInfoPtr scrn); 298428d7b3dSmrg 299428d7b3dSmrg#endif /* _INTEL_UXA_H_ */ 300