1428d7b3dSmrg/************************************************************************** 2428d7b3dSmrg * 3428d7b3dSmrg * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4428d7b3dSmrg * All Rights Reserved. 5428d7b3dSmrg * 6428d7b3dSmrg * Permission is hereby granted, free of charge, to any person obtaining a 7428d7b3dSmrg * copy of this software and associated documentation files (the 8428d7b3dSmrg * "Software"), to deal in the Software without restriction, including 9428d7b3dSmrg * without limitation the rights to use, copy, modify, merge, publish, 10428d7b3dSmrg * distribute, sub license, and/or sell copies of the Software, and to 11428d7b3dSmrg * permit persons to whom the Software is furnished to do so, subject to 12428d7b3dSmrg * the following conditions: 13428d7b3dSmrg * 14428d7b3dSmrg * The above copyright notice and this permission notice (including the 15428d7b3dSmrg * next paragraph) shall be included in all copies or substantial portions 16428d7b3dSmrg * of the Software. 17428d7b3dSmrg * 18428d7b3dSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19428d7b3dSmrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20428d7b3dSmrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21428d7b3dSmrg * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22428d7b3dSmrg * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23428d7b3dSmrg * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24428d7b3dSmrg * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25428d7b3dSmrg * 26428d7b3dSmrg **************************************************************************/ 27428d7b3dSmrg 28428d7b3dSmrg#ifndef _I915_REG_H_ 29428d7b3dSmrg#define _I915_REG_H_ 30428d7b3dSmrg 31428d7b3dSmrg#define I915_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) 32428d7b3dSmrg 33428d7b3dSmrg#define CMD_3D (0x3<<29) 34428d7b3dSmrg 35428d7b3dSmrg#define PRIM3D (CMD_3D | (0x1f<<24)) 36428d7b3dSmrg#define PRIM3D_INDIRECT_SEQUENTIAL ((1<<23) | (0<<17)) 37428d7b3dSmrg#define PRIM3D_TRILIST (PRIM3D | (0x0<<18)) 38428d7b3dSmrg#define PRIM3D_TRISTRIP (PRIM3D | (0x1<<18)) 39428d7b3dSmrg#define PRIM3D_TRISTRIP_RVRSE (PRIM3D | (0x2<<18)) 40428d7b3dSmrg#define PRIM3D_TRIFAN (PRIM3D | (0x3<<18)) 41428d7b3dSmrg#define PRIM3D_POLY (PRIM3D | (0x4<<18)) 42428d7b3dSmrg#define PRIM3D_LINELIST (PRIM3D | (0x5<<18)) 43428d7b3dSmrg#define PRIM3D_LINESTRIP (PRIM3D | (0x6<<18)) 44428d7b3dSmrg#define PRIM3D_RECTLIST (PRIM3D | (0x7<<18)) 45428d7b3dSmrg#define PRIM3D_POINTLIST (PRIM3D | (0x8<<18)) 46428d7b3dSmrg#define PRIM3D_DIB (PRIM3D | (0x9<<18)) 47428d7b3dSmrg#define PRIM3D_CLEAR_RECT (PRIM3D | (0xa<<18)) 48428d7b3dSmrg#define PRIM3D_ZONE_INIT (PRIM3D | (0xd<<18)) 49428d7b3dSmrg#define PRIM3D_MASK (0x1f<<18) 50428d7b3dSmrg 51428d7b3dSmrg/* p137 */ 52428d7b3dSmrg#define _3DSTATE_AA_CMD (CMD_3D | (0x06<<24)) 53428d7b3dSmrg#define AA_LINE_ECAAR_WIDTH_ENABLE (1<<16) 54428d7b3dSmrg#define AA_LINE_ECAAR_WIDTH_0_5 0 55428d7b3dSmrg#define AA_LINE_ECAAR_WIDTH_1_0 (1<<14) 56428d7b3dSmrg#define AA_LINE_ECAAR_WIDTH_2_0 (2<<14) 57428d7b3dSmrg#define AA_LINE_ECAAR_WIDTH_4_0 (3<<14) 58428d7b3dSmrg#define AA_LINE_REGION_WIDTH_ENABLE (1<<8) 59428d7b3dSmrg#define AA_LINE_REGION_WIDTH_0_5 0 60428d7b3dSmrg#define AA_LINE_REGION_WIDTH_1_0 (1<<6) 61428d7b3dSmrg#define AA_LINE_REGION_WIDTH_2_0 (2<<6) 62428d7b3dSmrg#define AA_LINE_REGION_WIDTH_4_0 (3<<6) 63428d7b3dSmrg 64428d7b3dSmrg/* 3DSTATE_BACKFACE_STENCIL_OPS, p138*/ 65428d7b3dSmrg#define _3DSTATE_BACKFACE_STENCIL_OPS (CMD_3D | (0x8<<24)) 66428d7b3dSmrg#define BFO_ENABLE_STENCIL_REF (1<<23) 67428d7b3dSmrg#define BFO_STENCIL_REF_SHIFT 15 68428d7b3dSmrg#define BFO_STENCIL_REF_MASK (0xff<<15) 69428d7b3dSmrg#define BFO_ENABLE_STENCIL_FUNCS (1<<14) 70428d7b3dSmrg#define BFO_STENCIL_TEST_SHIFT 11 71428d7b3dSmrg#define BFO_STENCIL_TEST_MASK (0x7<<11) 72428d7b3dSmrg#define BFO_STENCIL_FAIL_SHIFT 8 73428d7b3dSmrg#define BFO_STENCIL_FAIL_MASK (0x7<<8) 74428d7b3dSmrg#define BFO_STENCIL_PASS_Z_FAIL_SHIFT 5 75428d7b3dSmrg#define BFO_STENCIL_PASS_Z_FAIL_MASK (0x7<<5) 76428d7b3dSmrg#define BFO_STENCIL_PASS_Z_PASS_SHIFT 2 77428d7b3dSmrg#define BFO_STENCIL_PASS_Z_PASS_MASK (0x7<<2) 78428d7b3dSmrg#define BFO_ENABLE_STENCIL_TWO_SIDE (1<<1) 79428d7b3dSmrg#define BFO_STENCIL_TWO_SIDE (1<<0) 80428d7b3dSmrg 81428d7b3dSmrg/* 3DSTATE_BACKFACE_STENCIL_MASKS, p140 */ 82428d7b3dSmrg#define _3DSTATE_BACKFACE_STENCIL_MASKS (CMD_3D | (0x9<<24)) 83428d7b3dSmrg#define BFM_ENABLE_STENCIL_TEST_MASK (1<<17) 84428d7b3dSmrg#define BFM_ENABLE_STENCIL_WRITE_MASK (1<<16) 85428d7b3dSmrg#define BFM_STENCIL_TEST_MASK_SHIFT 8 86428d7b3dSmrg#define BFM_STENCIL_TEST_MASK_MASK (0xff<<8) 87428d7b3dSmrg#define BFM_STENCIL_WRITE_MASK_SHIFT 0 88428d7b3dSmrg#define BFM_STENCIL_WRITE_MASK_MASK (0xff<<0) 89428d7b3dSmrg 90428d7b3dSmrg/* 3DSTATE_BIN_CONTROL p141 */ 91428d7b3dSmrg 92428d7b3dSmrg/* p143 */ 93428d7b3dSmrg#define _3DSTATE_BUF_INFO_CMD (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1) 94428d7b3dSmrg/* Dword 1 */ 95428d7b3dSmrg#define BUF_3D_ID_COLOR_BACK (0x3<<24) 96428d7b3dSmrg#define BUF_3D_ID_DEPTH (0x7<<24) 97428d7b3dSmrg#define BUF_3D_USE_FENCE (1<<23) 98428d7b3dSmrg#define BUF_3D_TILED_SURFACE (1<<22) 99428d7b3dSmrg#define BUF_3D_TILE_WALK_X 0 100428d7b3dSmrg#define BUF_3D_TILE_WALK_Y (1<<21) 101428d7b3dSmrg#define BUF_3D_PITCH(x) (((x)/4)<<2) 102428d7b3dSmrg/* Dword 2 */ 103428d7b3dSmrg#define BUF_3D_ADDR(x) ((x) & ~0x3) 104428d7b3dSmrg 105428d7b3dSmrg/* 3DSTATE_CHROMA_KEY */ 106428d7b3dSmrg 107428d7b3dSmrg/* 3DSTATE_CLEAR_PARAMETERS, p150 */ 108428d7b3dSmrg#define _3DSTATE_CLEAR_PARAMETERS (CMD_3D | (0x1d<<24) | (0x9c<<16) | 5) 109428d7b3dSmrg/* Dword 1 */ 110428d7b3dSmrg#define CLEARPARAM_CLEAR_RECT (1 << 16) 111428d7b3dSmrg#define CLEARPARAM_ZONE_INIT (0 << 16) 112428d7b3dSmrg#define CLEARPARAM_WRITE_COLOR (1 << 2) 113428d7b3dSmrg#define CLEARPARAM_WRITE_DEPTH (1 << 1) 114428d7b3dSmrg#define CLEARPARAM_WRITE_STENCIL (1 << 0) 115428d7b3dSmrg 116428d7b3dSmrg/* 3DSTATE_CONSTANT_BLEND_COLOR, p153 */ 117428d7b3dSmrg#define _3DSTATE_CONST_BLEND_COLOR_CMD (CMD_3D | (0x1d<<24) | (0x88<<16)) 118428d7b3dSmrg 119428d7b3dSmrg/* 3DSTATE_COORD_SET_BINDINGS, p154 */ 120428d7b3dSmrg#define _3DSTATE_COORD_SET_BINDINGS (CMD_3D | (0x16<<24)) 121428d7b3dSmrg#define CSB_TCB(iunit, eunit) ((eunit)<<(iunit*3)) 122428d7b3dSmrg 123428d7b3dSmrg/* p156 */ 124428d7b3dSmrg#define _3DSTATE_DFLT_DIFFUSE_CMD (CMD_3D | (0x1d<<24) | (0x99<<16)) 125428d7b3dSmrg 126428d7b3dSmrg/* p157 */ 127428d7b3dSmrg#define _3DSTATE_DFLT_SPEC_CMD (CMD_3D | (0x1d<<24) | (0x9a<<16)) 128428d7b3dSmrg 129428d7b3dSmrg/* p158 */ 130428d7b3dSmrg#define _3DSTATE_DFLT_Z_CMD (CMD_3D | (0x1d<<24) | (0x98<<16)) 131428d7b3dSmrg 132428d7b3dSmrg/* 3DSTATE_DEPTH_OFFSET_SCALE, p159 */ 133428d7b3dSmrg#define _3DSTATE_DEPTH_OFFSET_SCALE (CMD_3D | (0x1d<<24) | (0x97<<16)) 134428d7b3dSmrg/* scale in dword 1 */ 135428d7b3dSmrg 136428d7b3dSmrg/* The depth subrectangle is not supported, but must be disabled. */ 137428d7b3dSmrg/* 3DSTATE_DEPTH_SUBRECT_DISABLE, p160 */ 138428d7b3dSmrg#define _3DSTATE_DEPTH_SUBRECT_DISABLE (CMD_3D | (0x1c<<24) | (0x11<<19) | (1 << 1) | (0 << 0)) 139428d7b3dSmrg 140428d7b3dSmrg/* p161 */ 141428d7b3dSmrg#define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16)) 142428d7b3dSmrg/* Dword 1 */ 143428d7b3dSmrg#define TEX_DEFAULT_COLOR_OGL (0<<30) 144428d7b3dSmrg#define TEX_DEFAULT_COLOR_D3D (1<<30) 145428d7b3dSmrg#define ZR_EARLY_DEPTH (1<<29) 146428d7b3dSmrg#define LOD_PRECLAMP_OGL (1<<28) 147428d7b3dSmrg#define LOD_PRECLAMP_D3D (0<<28) 148428d7b3dSmrg#define DITHER_FULL_ALWAYS (0<<26) 149428d7b3dSmrg#define DITHER_FULL_ON_FB_BLEND (1<<26) 150428d7b3dSmrg#define DITHER_CLAMPED_ALWAYS (2<<26) 151428d7b3dSmrg#define LINEAR_GAMMA_BLEND_32BPP (1<<25) 152428d7b3dSmrg#define DEBUG_DISABLE_ENH_DITHER (1<<24) 153428d7b3dSmrg#define DSTORG_HORT_BIAS(x) ((x)<<20) 154428d7b3dSmrg#define DSTORG_VERT_BIAS(x) ((x)<<16) 155428d7b3dSmrg#define COLOR_4_2_2_CHNL_WRT_ALL 0 156428d7b3dSmrg#define COLOR_4_2_2_CHNL_WRT_Y (1<<12) 157428d7b3dSmrg#define COLOR_4_2_2_CHNL_WRT_CR (2<<12) 158428d7b3dSmrg#define COLOR_4_2_2_CHNL_WRT_CB (3<<12) 159428d7b3dSmrg#define COLOR_4_2_2_CHNL_WRT_CRCB (4<<12) 160428d7b3dSmrg#define COLR_BUF_8BIT 0 161428d7b3dSmrg#define COLR_BUF_RGB555 (1<<8) 162428d7b3dSmrg#define COLR_BUF_RGB565 (2<<8) 163428d7b3dSmrg#define COLR_BUF_ARGB8888 (3<<8) 164428d7b3dSmrg#define COLR_BUF_ARGB4444 (8<<8) 165428d7b3dSmrg#define COLR_BUF_ARGB1555 (9<<8) 166428d7b3dSmrg#define COLR_BUF_ARGB2AAA (0xa<<8) 167428d7b3dSmrg#define DEPTH_FRMT_16_FIXED 0 168428d7b3dSmrg#define DEPTH_FRMT_16_FLOAT (1<<2) 169428d7b3dSmrg#define DEPTH_FRMT_24_FIXED_8_OTHER (2<<2) 170428d7b3dSmrg#define VERT_LINE_STRIDE_1 (1<<1) 171428d7b3dSmrg#define VERT_LINE_STRIDE_0 (0<<1) 172428d7b3dSmrg#define VERT_LINE_STRIDE_OFS_1 1 173428d7b3dSmrg#define VERT_LINE_STRIDE_OFS_0 0 174428d7b3dSmrg 175428d7b3dSmrg/* p166 */ 176428d7b3dSmrg#define _3DSTATE_DRAW_RECT_CMD (CMD_3D|(0x1d<<24)|(0x80<<16)|3) 177428d7b3dSmrg/* Dword 1 */ 178428d7b3dSmrg#define DRAW_RECT_DIS_DEPTH_OFS (1<<30) 179428d7b3dSmrg#define DRAW_DITHER_OFS_X(x) ((x)<<26) 180428d7b3dSmrg#define DRAW_DITHER_OFS_Y(x) ((x)<<24) 181428d7b3dSmrg/* Dword 2 */ 182428d7b3dSmrg#define DRAW_YMIN(x) ((x)<<16) 183428d7b3dSmrg#define DRAW_XMIN(x) (x) 184428d7b3dSmrg/* Dword 3 */ 185428d7b3dSmrg#define DRAW_YMAX(x) ((x)<<16) 186428d7b3dSmrg#define DRAW_XMAX(x) (x) 187428d7b3dSmrg/* Dword 4 */ 188428d7b3dSmrg#define DRAW_YORG(x) ((x)<<16) 189428d7b3dSmrg#define DRAW_XORG(x) (x) 190428d7b3dSmrg 191428d7b3dSmrg/* 3DSTATE_FILTER_COEFFICIENTS_4X4, p170 */ 192428d7b3dSmrg 193428d7b3dSmrg/* 3DSTATE_FILTER_COEFFICIENTS_6X5, p172 */ 194428d7b3dSmrg 195428d7b3dSmrg/* _3DSTATE_FOG_COLOR, p173 */ 196428d7b3dSmrg#define _3DSTATE_FOG_COLOR_CMD (CMD_3D|(0x15<<24)) 197428d7b3dSmrg#define FOG_COLOR_RED(x) ((x)<<16) 198428d7b3dSmrg#define FOG_COLOR_GREEN(x) ((x)<<8) 199428d7b3dSmrg#define FOG_COLOR_BLUE(x) (x) 200428d7b3dSmrg 201428d7b3dSmrg/* _3DSTATE_FOG_MODE, p174 */ 202428d7b3dSmrg#define _3DSTATE_FOG_MODE_CMD (CMD_3D|(0x1d<<24)|(0x89<<16)|2) 203428d7b3dSmrg/* Dword 1 */ 204428d7b3dSmrg#define FMC1_FOGFUNC_MODIFY_ENABLE (1<<31) 205428d7b3dSmrg#define FMC1_FOGFUNC_VERTEX (0<<28) 206428d7b3dSmrg#define FMC1_FOGFUNC_PIXEL_EXP (1<<28) 207428d7b3dSmrg#define FMC1_FOGFUNC_PIXEL_EXP2 (2<<28) 208428d7b3dSmrg#define FMC1_FOGFUNC_PIXEL_LINEAR (3<<28) 209428d7b3dSmrg#define FMC1_FOGFUNC_MASK (3<<28) 210428d7b3dSmrg#define FMC1_FOGINDEX_MODIFY_ENABLE (1<<27) 211428d7b3dSmrg#define FMC1_FOGINDEX_Z (0<<25) 212428d7b3dSmrg#define FMC1_FOGINDEX_W (1<<25) 213428d7b3dSmrg#define FMC1_C1_C2_MODIFY_ENABLE (1<<24) 214428d7b3dSmrg#define FMC1_DENSITY_MODIFY_ENABLE (1<<23) 215428d7b3dSmrg#define FMC1_C1_ONE (1<<13) 216428d7b3dSmrg#define FMC1_C1_MASK (0xffff<<4) 217428d7b3dSmrg/* Dword 2 */ 218428d7b3dSmrg#define FMC2_C2_ONE (1<<16) 219428d7b3dSmrg/* Dword 3 */ 220428d7b3dSmrg#define FMC3_D_ONE (1<<16) 221428d7b3dSmrg 222428d7b3dSmrg/* _3DSTATE_INDEPENDENT_ALPHA_BLEND, p177 */ 223428d7b3dSmrg#define _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD (CMD_3D|(0x0b<<24)) 224428d7b3dSmrg#define IAB_MODIFY_ENABLE (1<<23) 225428d7b3dSmrg#define IAB_ENABLE (1<<22) 226428d7b3dSmrg#define IAB_MODIFY_FUNC (1<<21) 227428d7b3dSmrg#define IAB_FUNC_SHIFT 16 228428d7b3dSmrg#define IAB_MODIFY_SRC_FACTOR (1<<11) 229428d7b3dSmrg#define IAB_SRC_FACTOR_SHIFT 6 230428d7b3dSmrg#define IAB_SRC_FACTOR_MASK (BLENDFACT_MASK<<6) 231428d7b3dSmrg#define IAB_MODIFY_DST_FACTOR (1<<5) 232428d7b3dSmrg#define IAB_DST_FACTOR_SHIFT 0 233428d7b3dSmrg#define IAB_DST_FACTOR_MASK (BLENDFACT_MASK<<0) 234428d7b3dSmrg 235428d7b3dSmrg#define BLENDFACT_ZERO 0x01 236428d7b3dSmrg#define BLENDFACT_ONE 0x02 237428d7b3dSmrg#define BLENDFACT_SRC_COLR 0x03 238428d7b3dSmrg#define BLENDFACT_INV_SRC_COLR 0x04 239428d7b3dSmrg#define BLENDFACT_SRC_ALPHA 0x05 240428d7b3dSmrg#define BLENDFACT_INV_SRC_ALPHA 0x06 241428d7b3dSmrg#define BLENDFACT_DST_ALPHA 0x07 242428d7b3dSmrg#define BLENDFACT_INV_DST_ALPHA 0x08 243428d7b3dSmrg#define BLENDFACT_DST_COLR 0x09 244428d7b3dSmrg#define BLENDFACT_INV_DST_COLR 0x0a 245428d7b3dSmrg#define BLENDFACT_SRC_ALPHA_SATURATE 0x0b 246428d7b3dSmrg#define BLENDFACT_CONST_COLOR 0x0c 247428d7b3dSmrg#define BLENDFACT_INV_CONST_COLOR 0x0d 248428d7b3dSmrg#define BLENDFACT_CONST_ALPHA 0x0e 249428d7b3dSmrg#define BLENDFACT_INV_CONST_ALPHA 0x0f 250428d7b3dSmrg#define BLENDFACT_MASK 0x0f 251428d7b3dSmrg 252428d7b3dSmrg#define BLENDFUNC_ADD 0x0 253428d7b3dSmrg#define BLENDFUNC_SUBTRACT 0x1 254428d7b3dSmrg#define BLENDFUNC_REVERSE_SUBTRACT 0x2 255428d7b3dSmrg#define BLENDFUNC_MIN 0x3 256428d7b3dSmrg#define BLENDFUNC_MAX 0x4 257428d7b3dSmrg#define BLENDFUNC_MASK 0x7 258428d7b3dSmrg 259428d7b3dSmrg/* 3DSTATE_LOAD_INDIRECT, p180 */ 260428d7b3dSmrg 261428d7b3dSmrg#define _3DSTATE_LOAD_INDIRECT (CMD_3D|(0x1d<<24)|(0x7<<16)) 262428d7b3dSmrg#define LI0_STATE_STATIC_INDIRECT (0x01<<8) 263428d7b3dSmrg#define LI0_STATE_DYNAMIC_INDIRECT (0x02<<8) 264428d7b3dSmrg#define LI0_STATE_SAMPLER (0x04<<8) 265428d7b3dSmrg#define LI0_STATE_MAP (0x08<<8) 266428d7b3dSmrg#define LI0_STATE_PROGRAM (0x10<<8) 267428d7b3dSmrg#define LI0_STATE_CONSTANTS (0x20<<8) 268428d7b3dSmrg 269428d7b3dSmrg#define SIS0_BUFFER_ADDRESS(x) ((x)&~0x3) 270428d7b3dSmrg#define SIS0_FORCE_LOAD (1<<1) 271428d7b3dSmrg#define SIS0_BUFFER_VALID (1<<0) 272428d7b3dSmrg#define SIS1_BUFFER_LENGTH(x) ((x)&0xff) 273428d7b3dSmrg 274428d7b3dSmrg#define DIS0_BUFFER_ADDRESS(x) ((x)&~0x3) 275428d7b3dSmrg#define DIS0_BUFFER_RESET (1<<1) 276428d7b3dSmrg#define DIS0_BUFFER_VALID (1<<0) 277428d7b3dSmrg 278428d7b3dSmrg#define SSB0_BUFFER_ADDRESS(x) ((x)&~0x3) 279428d7b3dSmrg#define SSB0_FORCE_LOAD (1<<1) 280428d7b3dSmrg#define SSB0_BUFFER_VALID (1<<0) 281428d7b3dSmrg#define SSB1_BUFFER_LENGTH(x) ((x)&0xff) 282428d7b3dSmrg 283428d7b3dSmrg#define MSB0_BUFFER_ADDRESS(x) ((x)&~0x3) 284428d7b3dSmrg#define MSB0_FORCE_LOAD (1<<1) 285428d7b3dSmrg#define MSB0_BUFFER_VALID (1<<0) 286428d7b3dSmrg#define MSB1_BUFFER_LENGTH(x) ((x)&0xff) 287428d7b3dSmrg 288428d7b3dSmrg#define PSP0_BUFFER_ADDRESS(x) ((x)&~0x3) 289428d7b3dSmrg#define PSP0_FORCE_LOAD (1<<1) 290428d7b3dSmrg#define PSP0_BUFFER_VALID (1<<0) 291428d7b3dSmrg#define PSP1_BUFFER_LENGTH(x) ((x)&0xff) 292428d7b3dSmrg 293428d7b3dSmrg#define PSC0_BUFFER_ADDRESS(x) ((x)&~0x3) 294428d7b3dSmrg#define PSC0_FORCE_LOAD (1<<1) 295428d7b3dSmrg#define PSC0_BUFFER_VALID (1<<0) 296428d7b3dSmrg#define PSC1_BUFFER_LENGTH(x) ((x)&0xff) 297428d7b3dSmrg 298428d7b3dSmrg/* _3DSTATE_RASTERIZATION_RULES */ 299428d7b3dSmrg#define _3DSTATE_RASTER_RULES_CMD (CMD_3D|(0x07<<24)) 300428d7b3dSmrg#define ENABLE_POINT_RASTER_RULE (1<<15) 301428d7b3dSmrg#define OGL_POINT_RASTER_RULE (1<<13) 302428d7b3dSmrg#define ENABLE_TEXKILL_3D_4D (1<<10) 303428d7b3dSmrg#define TEXKILL_3D (0<<9) 304428d7b3dSmrg#define TEXKILL_4D (1<<9) 305428d7b3dSmrg#define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8) 306428d7b3dSmrg#define ENABLE_TRI_FAN_PROVOKE_VRTX (1<<5) 307428d7b3dSmrg#define LINE_STRIP_PROVOKE_VRTX(x) ((x)<<6) 308428d7b3dSmrg#define TRI_FAN_PROVOKE_VRTX(x) ((x)<<3) 309428d7b3dSmrg 310428d7b3dSmrg/* _3DSTATE_SCISSOR_ENABLE, p256 */ 311428d7b3dSmrg#define _3DSTATE_SCISSOR_ENABLE_CMD (CMD_3D|(0x1c<<24)|(0x10<<19)) 312428d7b3dSmrg#define ENABLE_SCISSOR_RECT ((1<<1) | 1) 313428d7b3dSmrg#define DISABLE_SCISSOR_RECT (1<<1) 314428d7b3dSmrg 315428d7b3dSmrg/* _3DSTATE_SCISSOR_RECTANGLE_0, p257 */ 316428d7b3dSmrg#define _3DSTATE_SCISSOR_RECT_0_CMD (CMD_3D|(0x1d<<24)|(0x81<<16)|1) 317428d7b3dSmrg/* Dword 1 */ 318428d7b3dSmrg#define SCISSOR_RECT_0_YMIN(x) ((x)<<16) 319428d7b3dSmrg#define SCISSOR_RECT_0_XMIN(x) (x) 320428d7b3dSmrg/* Dword 2 */ 321428d7b3dSmrg#define SCISSOR_RECT_0_YMAX(x) ((x)<<16) 322428d7b3dSmrg#define SCISSOR_RECT_0_XMAX(x) (x) 323428d7b3dSmrg 324428d7b3dSmrg/* p189 */ 325428d7b3dSmrg#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 ((0x3<<29)|(0x1d<<24)|(0x04<<16)) 326428d7b3dSmrg#define I1_LOAD_S(n) (1<<(4+n)) 327428d7b3dSmrg 328428d7b3dSmrg#define S0_VB_OFFSET_MASK 0xffffffc 329428d7b3dSmrg#define S0_AUTO_CACHE_INV_DISABLE (1<<0) 330428d7b3dSmrg 331428d7b3dSmrg#define S1_VERTEX_WIDTH_SHIFT 24 332428d7b3dSmrg#define S1_VERTEX_WIDTH_MASK (0x3f<<24) 333428d7b3dSmrg#define S1_VERTEX_PITCH_SHIFT 16 334428d7b3dSmrg#define S1_VERTEX_PITCH_MASK (0x3f<<16) 335428d7b3dSmrg 336428d7b3dSmrg#define TEXCOORDFMT_2D 0x0 337428d7b3dSmrg#define TEXCOORDFMT_3D 0x1 338428d7b3dSmrg#define TEXCOORDFMT_4D 0x2 339428d7b3dSmrg#define TEXCOORDFMT_1D 0x3 340428d7b3dSmrg#define TEXCOORDFMT_2D_16 0x4 341428d7b3dSmrg#define TEXCOORDFMT_4D_16 0x5 342428d7b3dSmrg#define TEXCOORDFMT_NOT_PRESENT 0xf 343428d7b3dSmrg#define S2_TEXCOORD_FMT0_MASK 0xf 344428d7b3dSmrg#define S2_TEXCOORD_FMT1_SHIFT 4 345428d7b3dSmrg#define S2_TEXCOORD_FMT(unit, type) ((type)<<(unit*4)) 346428d7b3dSmrg#define S2_TEXCOORD_NONE (~0) 347428d7b3dSmrg 348428d7b3dSmrg#define TEXCOORD_WRAP_SHORTEST_TCX 8 349428d7b3dSmrg#define TEXCOORD_WRAP_SHORTEST_TCY 4 350428d7b3dSmrg#define TEXCOORD_WRAP_SHORTEST_TCZ 2 351428d7b3dSmrg#define TEXCOORD_PERSPECTIVE_DISABLE 1 352428d7b3dSmrg 353428d7b3dSmrg#define S3_WRAP_SHORTEST_TCX(unit) (TEXCOORD_WRAP_SHORTEST_TCX << ((unit) * 4)) 354428d7b3dSmrg#define S3_WRAP_SHORTEST_TCY(unit) (TEXCOORD_WRAP_SHORTEST_TCY << ((unit) * 4)) 355428d7b3dSmrg#define S3_WRAP_SHORTEST_TCZ(unit) (TEXCOORD_WRAP_SHORTEST_TCZ << ((unit) * 4)) 356428d7b3dSmrg#define S3_PERSPECTIVE_DISABLE(unit) (TEXCOORD_PERSPECTIVE_DISABLE << ((unit) * 4)) 357428d7b3dSmrg 358428d7b3dSmrg/* S3 not interesting */ 359428d7b3dSmrg 360428d7b3dSmrg#define S4_POINT_WIDTH_SHIFT 23 361428d7b3dSmrg#define S4_POINT_WIDTH_MASK (0x1ff<<23) 362428d7b3dSmrg#define S4_LINE_WIDTH_SHIFT 19 363428d7b3dSmrg#define S4_LINE_WIDTH_ONE (0x2<<19) 364428d7b3dSmrg#define S4_LINE_WIDTH_MASK (0xf<<19) 365428d7b3dSmrg#define S4_FLATSHADE_ALPHA (1<<18) 366428d7b3dSmrg#define S4_FLATSHADE_FOG (1<<17) 367428d7b3dSmrg#define S4_FLATSHADE_SPECULAR (1<<16) 368428d7b3dSmrg#define S4_FLATSHADE_COLOR (1<<15) 369428d7b3dSmrg#define S4_CULLMODE_BOTH (0<<13) 370428d7b3dSmrg#define S4_CULLMODE_NONE (1<<13) 371428d7b3dSmrg#define S4_CULLMODE_CW (2<<13) 372428d7b3dSmrg#define S4_CULLMODE_CCW (3<<13) 373428d7b3dSmrg#define S4_CULLMODE_MASK (3<<13) 374428d7b3dSmrg#define S4_VFMT_POINT_WIDTH (1<<12) 375428d7b3dSmrg#define S4_VFMT_SPEC_FOG (1<<11) 376428d7b3dSmrg#define S4_VFMT_COLOR (1<<10) 377428d7b3dSmrg#define S4_VFMT_DEPTH_OFFSET (1<<9) 378428d7b3dSmrg#define S4_VFMT_XYZ (1<<6) 379428d7b3dSmrg#define S4_VFMT_XYZW (2<<6) 380428d7b3dSmrg#define S4_VFMT_XY (3<<6) 381428d7b3dSmrg#define S4_VFMT_XYW (4<<6) 382428d7b3dSmrg#define S4_VFMT_XYZW_MASK (7<<6) 383428d7b3dSmrg#define S4_FORCE_DEFAULT_DIFFUSE (1<<5) 384428d7b3dSmrg#define S4_FORCE_DEFAULT_SPECULAR (1<<4) 385428d7b3dSmrg#define S4_LOCAL_DEPTH_OFFSET_ENABLE (1<<3) 386428d7b3dSmrg#define S4_VFMT_FOG_PARAM (1<<2) 387428d7b3dSmrg#define S4_SPRITE_POINT_ENABLE (1<<1) 388428d7b3dSmrg#define S4_LINE_ANTIALIAS_ENABLE (1<<0) 389428d7b3dSmrg 390428d7b3dSmrg#define S4_VFMT_MASK (S4_VFMT_POINT_WIDTH | \ 391428d7b3dSmrg S4_VFMT_SPEC_FOG | \ 392428d7b3dSmrg S4_VFMT_COLOR | \ 393428d7b3dSmrg S4_VFMT_DEPTH_OFFSET | \ 394428d7b3dSmrg S4_VFMT_XYZW_MASK | \ 395428d7b3dSmrg S4_VFMT_FOG_PARAM) 396428d7b3dSmrg 397428d7b3dSmrg#define S5_WRITEDISABLE_ALPHA (1<<31) 398428d7b3dSmrg#define S5_WRITEDISABLE_RED (1<<30) 399428d7b3dSmrg#define S5_WRITEDISABLE_GREEN (1<<29) 400428d7b3dSmrg#define S5_WRITEDISABLE_BLUE (1<<28) 401428d7b3dSmrg#define S5_WRITEDISABLE_MASK (0xf<<28) 402428d7b3dSmrg#define S5_FORCE_DEFAULT_POINT_SIZE (1<<27) 403428d7b3dSmrg#define S5_LAST_PIXEL_ENABLE (1<<26) 404428d7b3dSmrg#define S5_GLOBAL_DEPTH_OFFSET_ENABLE (1<<25) 405428d7b3dSmrg#define S5_FOG_ENABLE (1<<24) 406428d7b3dSmrg#define S5_STENCIL_REF_SHIFT 16 407428d7b3dSmrg#define S5_STENCIL_REF_MASK (0xff<<16) 408428d7b3dSmrg#define S5_STENCIL_TEST_FUNC_SHIFT 13 409428d7b3dSmrg#define S5_STENCIL_TEST_FUNC_MASK (0x7<<13) 410428d7b3dSmrg#define S5_STENCIL_FAIL_SHIFT 10 411428d7b3dSmrg#define S5_STENCIL_FAIL_MASK (0x7<<10) 412428d7b3dSmrg#define S5_STENCIL_PASS_Z_FAIL_SHIFT 7 413428d7b3dSmrg#define S5_STENCIL_PASS_Z_FAIL_MASK (0x7<<7) 414428d7b3dSmrg#define S5_STENCIL_PASS_Z_PASS_SHIFT 4 415428d7b3dSmrg#define S5_STENCIL_PASS_Z_PASS_MASK (0x7<<4) 416428d7b3dSmrg#define S5_STENCIL_WRITE_ENABLE (1<<3) 417428d7b3dSmrg#define S5_STENCIL_TEST_ENABLE (1<<2) 418428d7b3dSmrg#define S5_COLOR_DITHER_ENABLE (1<<1) 419428d7b3dSmrg#define S5_LOGICOP_ENABLE (1<<0) 420428d7b3dSmrg 421428d7b3dSmrg#define S6_ALPHA_TEST_ENABLE (1<<31) 422428d7b3dSmrg#define S6_ALPHA_TEST_FUNC_SHIFT 28 423428d7b3dSmrg#define S6_ALPHA_TEST_FUNC_MASK (0x7<<28) 424428d7b3dSmrg#define S6_ALPHA_REF_SHIFT 20 425428d7b3dSmrg#define S6_ALPHA_REF_MASK (0xff<<20) 426428d7b3dSmrg#define S6_DEPTH_TEST_ENABLE (1<<19) 427428d7b3dSmrg#define S6_DEPTH_TEST_FUNC_SHIFT 16 428428d7b3dSmrg#define S6_DEPTH_TEST_FUNC_MASK (0x7<<16) 429428d7b3dSmrg#define S6_CBUF_BLEND_ENABLE (1<<15) 430428d7b3dSmrg#define S6_CBUF_BLEND_FUNC_SHIFT 12 431428d7b3dSmrg#define S6_CBUF_BLEND_FUNC_MASK (0x7<<12) 432428d7b3dSmrg#define S6_CBUF_SRC_BLEND_FACT_SHIFT 8 433428d7b3dSmrg#define S6_CBUF_SRC_BLEND_FACT_MASK (0xf<<8) 434428d7b3dSmrg#define S6_CBUF_DST_BLEND_FACT_SHIFT 4 435428d7b3dSmrg#define S6_CBUF_DST_BLEND_FACT_MASK (0xf<<4) 436428d7b3dSmrg#define S6_DEPTH_WRITE_ENABLE (1<<3) 437428d7b3dSmrg#define S6_COLOR_WRITE_ENABLE (1<<2) 438428d7b3dSmrg#define S6_TRISTRIP_PV_SHIFT 0 439428d7b3dSmrg#define S6_TRISTRIP_PV_MASK (0x3<<0) 440428d7b3dSmrg 441428d7b3dSmrg#define S7_DEPTH_OFFSET_CONST_MASK ~0 442428d7b3dSmrg 443428d7b3dSmrg/* 3DSTATE_MAP_DEINTERLACER_PARAMETERS */ 444428d7b3dSmrg/* 3DSTATE_MAP_PALETTE_LOAD_32, p206 */ 445428d7b3dSmrg 446428d7b3dSmrg/* _3DSTATE_MODES_4, p218 */ 447428d7b3dSmrg#define _3DSTATE_MODES_4_CMD (CMD_3D|(0x0d<<24)) 448428d7b3dSmrg#define ENABLE_LOGIC_OP_FUNC (1<<23) 449428d7b3dSmrg#define LOGIC_OP_FUNC(x) ((x)<<18) 450428d7b3dSmrg#define LOGICOP_MASK (0xf<<18) 451428d7b3dSmrg#define LOGICOP_COPY 0xc 452428d7b3dSmrg#define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00)) 453428d7b3dSmrg#define ENABLE_STENCIL_TEST_MASK (1<<17) 454428d7b3dSmrg#define STENCIL_TEST_MASK(x) ((x)<<8) 455428d7b3dSmrg#define MODE4_ENABLE_STENCIL_WRITE_MASK ((1<<16)|(0x00ff)) 456428d7b3dSmrg#define ENABLE_STENCIL_WRITE_MASK (1<<16) 457428d7b3dSmrg#define STENCIL_WRITE_MASK(x) ((x)&0xff) 458428d7b3dSmrg 459428d7b3dSmrg/* _3DSTATE_MODES_5, p220 */ 460428d7b3dSmrg#define _3DSTATE_MODES_5_CMD (CMD_3D|(0x0c<<24)) 461428d7b3dSmrg#define PIPELINE_FLUSH_RENDER_CACHE (1<<18) 462428d7b3dSmrg#define PIPELINE_FLUSH_TEXTURE_CACHE (1<<16) 463428d7b3dSmrg 464428d7b3dSmrg/* p221 */ 465428d7b3dSmrg#define _3DSTATE_PIXEL_SHADER_CONSTANTS (CMD_3D|(0x1d<<24)|(0x6<<16)) 466428d7b3dSmrg#define PS1_REG(n) (1<<(n)) 467428d7b3dSmrg#define PS2_CONST_X(n) (n) 468428d7b3dSmrg#define PS3_CONST_Y(n) (n) 469428d7b3dSmrg#define PS4_CONST_Z(n) (n) 470428d7b3dSmrg#define PS5_CONST_W(n) (n) 471428d7b3dSmrg 472428d7b3dSmrg/* p222 */ 473428d7b3dSmrg 474428d7b3dSmrg#define I915_MAX_TEX_INDIRECT 4 475428d7b3dSmrg#define I915_MAX_TEX_INSN 32 476428d7b3dSmrg#define I915_MAX_ALU_INSN 64 477428d7b3dSmrg#define I915_MAX_DECL_INSN 27 478428d7b3dSmrg#define I915_MAX_TEMPORARY 16 479428d7b3dSmrg 480428d7b3dSmrg/* Each instruction is 3 dwords long, though most don't require all 481428d7b3dSmrg * this space. Maximum of 123 instructions. Smaller maxes per insn 482428d7b3dSmrg * type. 483428d7b3dSmrg */ 484428d7b3dSmrg#define _3DSTATE_PIXEL_SHADER_PROGRAM (CMD_3D|(0x1d<<24)|(0x5<<16)) 485428d7b3dSmrg 486428d7b3dSmrg#define REG_TYPE_R 0 /* temporary regs, no need to 487428d7b3dSmrg * dcl, must be written before 488428d7b3dSmrg * read -- Preserved between 489428d7b3dSmrg * phases. 490428d7b3dSmrg */ 491428d7b3dSmrg#define REG_TYPE_T 1 /* Interpolated values, must be 492428d7b3dSmrg * dcl'ed before use. 493428d7b3dSmrg * 494428d7b3dSmrg * 0..7: texture coord, 495428d7b3dSmrg * 8: diffuse spec, 496428d7b3dSmrg * 9: specular color, 497428d7b3dSmrg * 10: fog parameter in w. 498428d7b3dSmrg */ 499428d7b3dSmrg#define REG_TYPE_CONST 2 /* Restriction: only one const 500428d7b3dSmrg * can be referenced per 501428d7b3dSmrg * instruction, though it may be 502428d7b3dSmrg * selected for multiple inputs. 503428d7b3dSmrg * Constants not initialized 504428d7b3dSmrg * default to zero. 505428d7b3dSmrg */ 506428d7b3dSmrg#define REG_TYPE_S 3 /* sampler */ 507428d7b3dSmrg#define REG_TYPE_OC 4 /* output color (rgba) */ 508428d7b3dSmrg#define REG_TYPE_OD 5 /* output depth (w), xyz are 509428d7b3dSmrg * temporaries. If not written, 510428d7b3dSmrg * interpolated depth is used? 511428d7b3dSmrg */ 512428d7b3dSmrg#define REG_TYPE_U 6 /* unpreserved temporaries */ 513428d7b3dSmrg#define REG_TYPE_MASK 0x7 514428d7b3dSmrg#define REG_NR_MASK 0xf 515428d7b3dSmrg 516428d7b3dSmrg/* REG_TYPE_T: 517428d7b3dSmrg */ 518428d7b3dSmrg#define T_TEX0 0 519428d7b3dSmrg#define T_TEX1 1 520428d7b3dSmrg#define T_TEX2 2 521428d7b3dSmrg#define T_TEX3 3 522428d7b3dSmrg#define T_TEX4 4 523428d7b3dSmrg#define T_TEX5 5 524428d7b3dSmrg#define T_TEX6 6 525428d7b3dSmrg#define T_TEX7 7 526428d7b3dSmrg#define T_DIFFUSE 8 527428d7b3dSmrg#define T_SPECULAR 9 528428d7b3dSmrg#define T_FOG_W 10 /* interpolated fog is in W coord */ 529428d7b3dSmrg 530428d7b3dSmrg/* Arithmetic instructions */ 531428d7b3dSmrg 532428d7b3dSmrg/* .replicate_swizzle == selection and replication of a particular 533428d7b3dSmrg * scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww 534428d7b3dSmrg */ 535428d7b3dSmrg#define A0_NOP (0x0<<24) /* no operation */ 536428d7b3dSmrg#define A0_ADD (0x1<<24) /* dst = src0 + src1 */ 537428d7b3dSmrg#define A0_MOV (0x2<<24) /* dst = src0 */ 538428d7b3dSmrg#define A0_MUL (0x3<<24) /* dst = src0 * src1 */ 539428d7b3dSmrg#define A0_MAD (0x4<<24) /* dst = src0 * src1 + src2 */ 540428d7b3dSmrg#define A0_DP2ADD (0x5<<24) /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */ 541428d7b3dSmrg#define A0_DP3 (0x6<<24) /* dst.xyzw = src0.xyz dot src1.xyz */ 542428d7b3dSmrg#define A0_DP4 (0x7<<24) /* dst.xyzw = src0.xyzw dot src1.xyzw */ 543428d7b3dSmrg#define A0_FRC (0x8<<24) /* dst = src0 - floor(src0) */ 544428d7b3dSmrg#define A0_RCP (0x9<<24) /* dst.xyzw = 1/(src0.replicate_swizzle) */ 545428d7b3dSmrg#define A0_RSQ (0xa<<24) /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */ 546428d7b3dSmrg#define A0_EXP (0xb<<24) /* dst.xyzw = exp2(src0.replicate_swizzle) */ 547428d7b3dSmrg#define A0_LOG (0xc<<24) /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */ 548428d7b3dSmrg#define A0_CMP (0xd<<24) /* dst = (src0 >= 0.0) ? src1 : src2 */ 549428d7b3dSmrg#define A0_MIN (0xe<<24) /* dst = (src0 < src1) ? src0 : src1 */ 550428d7b3dSmrg#define A0_MAX (0xf<<24) /* dst = (src0 >= src1) ? src0 : src1 */ 551428d7b3dSmrg#define A0_FLR (0x10<<24) /* dst = floor(src0) */ 552428d7b3dSmrg#define A0_MOD (0x11<<24) /* dst = src0 fmod 1.0 */ 553428d7b3dSmrg#define A0_TRC (0x12<<24) /* dst = int(src0) */ 554428d7b3dSmrg#define A0_SGE (0x13<<24) /* dst = src0 >= src1 ? 1.0 : 0.0 */ 555428d7b3dSmrg#define A0_SLT (0x14<<24) /* dst = src0 < src1 ? 1.0 : 0.0 */ 556428d7b3dSmrg#define A0_DEST_SATURATE (1<<22) 557428d7b3dSmrg#define A0_DEST_TYPE_SHIFT 19 558428d7b3dSmrg/* Allow: R, OC, OD, U */ 559428d7b3dSmrg#define A0_DEST_NR_SHIFT 14 560428d7b3dSmrg/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ 561428d7b3dSmrg#define A0_DEST_CHANNEL_X (1<<10) 562428d7b3dSmrg#define A0_DEST_CHANNEL_Y (2<<10) 563428d7b3dSmrg#define A0_DEST_CHANNEL_Z (4<<10) 564428d7b3dSmrg#define A0_DEST_CHANNEL_W (8<<10) 565428d7b3dSmrg#define A0_DEST_CHANNEL_ALL (0xf<<10) 566428d7b3dSmrg#define A0_DEST_CHANNEL_SHIFT 10 567428d7b3dSmrg#define A0_SRC0_TYPE_SHIFT 7 568428d7b3dSmrg#define A0_SRC0_NR_SHIFT 2 569428d7b3dSmrg 570428d7b3dSmrg#define A0_DEST_CHANNEL_XY (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y) 571428d7b3dSmrg#define A0_DEST_CHANNEL_XYZ (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z) 572428d7b3dSmrg 573428d7b3dSmrg#define SRC_X 0 574428d7b3dSmrg#define SRC_Y 1 575428d7b3dSmrg#define SRC_Z 2 576428d7b3dSmrg#define SRC_W 3 577428d7b3dSmrg#define SRC_ZERO 4 578428d7b3dSmrg#define SRC_ONE 5 579428d7b3dSmrg 580428d7b3dSmrg#define A1_SRC0_CHANNEL_X_NEGATE (1<<31) 581428d7b3dSmrg#define A1_SRC0_CHANNEL_X_SHIFT 28 582428d7b3dSmrg#define A1_SRC0_CHANNEL_Y_NEGATE (1<<27) 583428d7b3dSmrg#define A1_SRC0_CHANNEL_Y_SHIFT 24 584428d7b3dSmrg#define A1_SRC0_CHANNEL_Z_NEGATE (1<<23) 585428d7b3dSmrg#define A1_SRC0_CHANNEL_Z_SHIFT 20 586428d7b3dSmrg#define A1_SRC0_CHANNEL_W_NEGATE (1<<19) 587428d7b3dSmrg#define A1_SRC0_CHANNEL_W_SHIFT 16 588428d7b3dSmrg#define A1_SRC1_TYPE_SHIFT 13 589428d7b3dSmrg#define A1_SRC1_NR_SHIFT 8 590428d7b3dSmrg#define A1_SRC1_CHANNEL_X_NEGATE (1<<7) 591428d7b3dSmrg#define A1_SRC1_CHANNEL_X_SHIFT 4 592428d7b3dSmrg#define A1_SRC1_CHANNEL_Y_NEGATE (1<<3) 593428d7b3dSmrg#define A1_SRC1_CHANNEL_Y_SHIFT 0 594428d7b3dSmrg 595428d7b3dSmrg#define A2_SRC1_CHANNEL_Z_NEGATE (1<<31) 596428d7b3dSmrg#define A2_SRC1_CHANNEL_Z_SHIFT 28 597428d7b3dSmrg#define A2_SRC1_CHANNEL_W_NEGATE (1<<27) 598428d7b3dSmrg#define A2_SRC1_CHANNEL_W_SHIFT 24 599428d7b3dSmrg#define A2_SRC2_TYPE_SHIFT 21 600428d7b3dSmrg#define A2_SRC2_NR_SHIFT 16 601428d7b3dSmrg#define A2_SRC2_CHANNEL_X_NEGATE (1<<15) 602428d7b3dSmrg#define A2_SRC2_CHANNEL_X_SHIFT 12 603428d7b3dSmrg#define A2_SRC2_CHANNEL_Y_NEGATE (1<<11) 604428d7b3dSmrg#define A2_SRC2_CHANNEL_Y_SHIFT 8 605428d7b3dSmrg#define A2_SRC2_CHANNEL_Z_NEGATE (1<<7) 606428d7b3dSmrg#define A2_SRC2_CHANNEL_Z_SHIFT 4 607428d7b3dSmrg#define A2_SRC2_CHANNEL_W_NEGATE (1<<3) 608428d7b3dSmrg#define A2_SRC2_CHANNEL_W_SHIFT 0 609428d7b3dSmrg 610428d7b3dSmrg/* Texture instructions */ 611428d7b3dSmrg#define T0_TEXLD (0x15<<24) /* Sample texture using predeclared 612428d7b3dSmrg * sampler and address, and output 613428d7b3dSmrg * filtered texel data to destination 614428d7b3dSmrg * register */ 615428d7b3dSmrg#define T0_TEXLDP (0x16<<24) /* Same as texld but performs a 616428d7b3dSmrg * perspective divide of the texture 617428d7b3dSmrg * coordinate .xyz values by .w before 618428d7b3dSmrg * sampling. */ 619428d7b3dSmrg#define T0_TEXLDB (0x17<<24) /* Same as texld but biases the 620428d7b3dSmrg * computed LOD by w. Only S4.6 two's 621428d7b3dSmrg * comp is used. This implies that a 622428d7b3dSmrg * float to fixed conversion is 623428d7b3dSmrg * done. */ 624428d7b3dSmrg#define T0_TEXKILL (0x18<<24) /* Does not perform a sampling 625428d7b3dSmrg * operation. Simply kills the pixel 626428d7b3dSmrg * if any channel of the address 627428d7b3dSmrg * register is < 0.0. */ 628428d7b3dSmrg#define T0_DEST_TYPE_SHIFT 19 629428d7b3dSmrg/* Allow: R, OC, OD, U */ 630428d7b3dSmrg/* Note: U (unpreserved) regs do not retain their values between 631428d7b3dSmrg * phases (cannot be used for feedback) 632428d7b3dSmrg * 633428d7b3dSmrg * Note: oC and OD registers can only be used as the destination of a 634428d7b3dSmrg * texture instruction once per phase (this is an implementation 635428d7b3dSmrg * restriction). 636428d7b3dSmrg */ 637428d7b3dSmrg#define T0_DEST_NR_SHIFT 14 638428d7b3dSmrg/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ 639428d7b3dSmrg#define T0_SAMPLER_NR_SHIFT 0 /* This field ignored for TEXKILL */ 640428d7b3dSmrg#define T0_SAMPLER_NR_MASK (0xf<<0) 641428d7b3dSmrg 642428d7b3dSmrg#define T1_ADDRESS_REG_TYPE_SHIFT 24 /* Reg to use as texture coord */ 643428d7b3dSmrg/* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */ 644428d7b3dSmrg#define T1_ADDRESS_REG_NR_SHIFT 17 645428d7b3dSmrg#define T2_MBZ 0 646428d7b3dSmrg 647428d7b3dSmrg/* Declaration instructions */ 648428d7b3dSmrg#define D0_DCL (0x19<<24) /* Declare a t (interpolated attrib) 649428d7b3dSmrg * register or an s (sampler) 650428d7b3dSmrg * register. */ 651428d7b3dSmrg#define D0_SAMPLE_TYPE_SHIFT 22 652428d7b3dSmrg#define D0_SAMPLE_TYPE_2D (0x0<<22) 653428d7b3dSmrg#define D0_SAMPLE_TYPE_CUBE (0x1<<22) 654428d7b3dSmrg#define D0_SAMPLE_TYPE_VOLUME (0x2<<22) 655428d7b3dSmrg#define D0_SAMPLE_TYPE_MASK (0x3<<22) 656428d7b3dSmrg 657428d7b3dSmrg#define D0_TYPE_SHIFT 19 658428d7b3dSmrg/* Allow: T, S */ 659428d7b3dSmrg#define D0_NR_SHIFT 14 660428d7b3dSmrg/* Allow T: 0..10, S: 0..15 */ 661428d7b3dSmrg#define D0_CHANNEL_X (1<<10) 662428d7b3dSmrg#define D0_CHANNEL_Y (2<<10) 663428d7b3dSmrg#define D0_CHANNEL_Z (4<<10) 664428d7b3dSmrg#define D0_CHANNEL_W (8<<10) 665428d7b3dSmrg#define D0_CHANNEL_ALL (0xf<<10) 666428d7b3dSmrg#define D0_CHANNEL_NONE (0<<10) 667428d7b3dSmrg 668428d7b3dSmrg#define D0_CHANNEL_XY (D0_CHANNEL_X|D0_CHANNEL_Y) 669428d7b3dSmrg#define D0_CHANNEL_XYZ (D0_CHANNEL_XY|D0_CHANNEL_Z) 670428d7b3dSmrg 671428d7b3dSmrg/* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse 672428d7b3dSmrg * or specular declarations. 673428d7b3dSmrg * 674428d7b3dSmrg * For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw) 675428d7b3dSmrg * 676428d7b3dSmrg * Must be zero for S (sampler) dcls 677428d7b3dSmrg */ 678428d7b3dSmrg#define D1_MBZ 0 679428d7b3dSmrg#define D2_MBZ 0 680428d7b3dSmrg 681428d7b3dSmrg/* p207. 682428d7b3dSmrg * The DWORD count is 3 times the number of bits set in MS1_MAPMASK_MASK 683428d7b3dSmrg */ 684428d7b3dSmrg#define _3DSTATE_MAP_STATE (CMD_3D|(0x1d<<24)|(0x0<<16)) 685428d7b3dSmrg 686428d7b3dSmrg#define MS1_MAPMASK_SHIFT 0 687428d7b3dSmrg#define MS1_MAPMASK_MASK (0x8fff<<0) 688428d7b3dSmrg 689428d7b3dSmrg#define MS2_UNTRUSTED_SURFACE (1<<31) 690428d7b3dSmrg#define MS2_ADDRESS_MASK 0xfffffffc 691428d7b3dSmrg#define MS2_VERTICAL_LINE_STRIDE (1<<1) 692428d7b3dSmrg#define MS2_VERTICAL_OFFSET (1<<1) 693428d7b3dSmrg 694428d7b3dSmrg#define MS3_HEIGHT_SHIFT 21 695428d7b3dSmrg#define MS3_WIDTH_SHIFT 10 696428d7b3dSmrg#define MS3_PALETTE_SELECT (1<<9) 697428d7b3dSmrg#define MS3_MAPSURF_FORMAT_SHIFT 7 698428d7b3dSmrg#define MS3_MAPSURF_FORMAT_MASK (0x7<<7) 699428d7b3dSmrg#define MAPSURF_8BIT (1<<7) 700428d7b3dSmrg#define MAPSURF_16BIT (2<<7) 701428d7b3dSmrg#define MAPSURF_32BIT (3<<7) 702428d7b3dSmrg#define MAPSURF_422 (5<<7) 703428d7b3dSmrg#define MAPSURF_COMPRESSED (6<<7) 704428d7b3dSmrg#define MAPSURF_4BIT_INDEXED (7<<7) 705428d7b3dSmrg#define MS3_MT_FORMAT_MASK (0x7 << 3) 706428d7b3dSmrg#define MS3_MT_FORMAT_SHIFT 3 707428d7b3dSmrg#define MT_4BIT_IDX_ARGB8888 (7<<3) /* SURFACE_4BIT_INDEXED */ 708428d7b3dSmrg#define MT_8BIT_I8 (0<<3) /* SURFACE_8BIT */ 709428d7b3dSmrg#define MT_8BIT_L8 (1<<3) 710428d7b3dSmrg#define MT_8BIT_A8 (4<<3) 711428d7b3dSmrg#define MT_8BIT_MONO8 (5<<3) 712428d7b3dSmrg#define MT_16BIT_RGB565 (0<<3) /* SURFACE_16BIT */ 713428d7b3dSmrg#define MT_16BIT_ARGB1555 (1<<3) 714428d7b3dSmrg#define MT_16BIT_ARGB4444 (2<<3) 715428d7b3dSmrg#define MT_16BIT_AY88 (3<<3) 716428d7b3dSmrg#define MT_16BIT_88DVDU (5<<3) 717428d7b3dSmrg#define MT_16BIT_BUMP_655LDVDU (6<<3) 718428d7b3dSmrg#define MT_16BIT_I16 (7<<3) 719428d7b3dSmrg#define MT_16BIT_L16 (8<<3) 720428d7b3dSmrg#define MT_16BIT_A16 (9<<3) 721428d7b3dSmrg#define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */ 722428d7b3dSmrg#define MT_32BIT_ABGR8888 (1<<3) 723428d7b3dSmrg#define MT_32BIT_XRGB8888 (2<<3) 724428d7b3dSmrg#define MT_32BIT_XBGR8888 (3<<3) 725428d7b3dSmrg#define MT_32BIT_QWVU8888 (4<<3) 726428d7b3dSmrg#define MT_32BIT_AXVU8888 (5<<3) 727428d7b3dSmrg#define MT_32BIT_LXVU8888 (6<<3) 728428d7b3dSmrg#define MT_32BIT_XLVU8888 (7<<3) 729428d7b3dSmrg#define MT_32BIT_ARGB2101010 (8<<3) 730428d7b3dSmrg#define MT_32BIT_ABGR2101010 (9<<3) 731428d7b3dSmrg#define MT_32BIT_AWVU2101010 (0xA<<3) 732428d7b3dSmrg#define MT_32BIT_GR1616 (0xB<<3) 733428d7b3dSmrg#define MT_32BIT_VU1616 (0xC<<3) 734428d7b3dSmrg#define MT_32BIT_xI824 (0xD<<3) 735428d7b3dSmrg#define MT_32BIT_xA824 (0xE<<3) 736428d7b3dSmrg#define MT_32BIT_xL824 (0xF<<3) 737428d7b3dSmrg#define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */ 738428d7b3dSmrg#define MT_422_YCRCB_NORMAL (1<<3) 739428d7b3dSmrg#define MT_422_YCRCB_SWAPUV (2<<3) 740428d7b3dSmrg#define MT_422_YCRCB_SWAPUVY (3<<3) 741428d7b3dSmrg#define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ 742428d7b3dSmrg#define MT_COMPRESS_DXT2_3 (1<<3) 743428d7b3dSmrg#define MT_COMPRESS_DXT4_5 (2<<3) 744428d7b3dSmrg#define MT_COMPRESS_FXT1 (3<<3) 745428d7b3dSmrg#define MT_COMPRESS_DXT1_RGB (4<<3) 746428d7b3dSmrg#define MS3_USE_FENCE_REGS (1<<2) 747428d7b3dSmrg#define MS3_TILED_SURFACE (1<<1) 748428d7b3dSmrg#define MS3_TILE_WALK (1<<0) 749428d7b3dSmrg 750428d7b3dSmrg/* The pitch is the pitch measured in DWORDS, minus 1 */ 751428d7b3dSmrg#define MS4_PITCH_SHIFT 21 752428d7b3dSmrg#define MS4_CUBE_FACE_ENA_NEGX (1<<20) 753428d7b3dSmrg#define MS4_CUBE_FACE_ENA_POSX (1<<19) 754428d7b3dSmrg#define MS4_CUBE_FACE_ENA_NEGY (1<<18) 755428d7b3dSmrg#define MS4_CUBE_FACE_ENA_POSY (1<<17) 756428d7b3dSmrg#define MS4_CUBE_FACE_ENA_NEGZ (1<<16) 757428d7b3dSmrg#define MS4_CUBE_FACE_ENA_POSZ (1<<15) 758428d7b3dSmrg#define MS4_CUBE_FACE_ENA_MASK (0x3f<<15) 759428d7b3dSmrg#define MS4_MAX_LOD_SHIFT 9 760428d7b3dSmrg#define MS4_MAX_LOD_MASK (0x3f<<9) 761428d7b3dSmrg#define MS4_MIP_LAYOUT_LEGACY (0<<8) 762428d7b3dSmrg#define MS4_MIP_LAYOUT_BELOW_LPT (0<<8) 763428d7b3dSmrg#define MS4_MIP_LAYOUT_RIGHT_LPT (1<<8) 764428d7b3dSmrg#define MS4_VOLUME_DEPTH_SHIFT 0 765428d7b3dSmrg#define MS4_VOLUME_DEPTH_MASK (0xff<<0) 766428d7b3dSmrg 767428d7b3dSmrg/* p244. 768428d7b3dSmrg * The DWORD count is 3 times the number of bits set in SS1_MAPMASK_MASK. 769428d7b3dSmrg */ 770428d7b3dSmrg#define _3DSTATE_SAMPLER_STATE (CMD_3D|(0x1d<<24)|(0x1<<16)) 771428d7b3dSmrg 772428d7b3dSmrg#define SS1_MAPMASK_SHIFT 0 773428d7b3dSmrg#define SS1_MAPMASK_MASK (0x8fff<<0) 774428d7b3dSmrg 775428d7b3dSmrg#define SS2_REVERSE_GAMMA_ENABLE (1<<31) 776428d7b3dSmrg#define SS2_PACKED_TO_PLANAR_ENABLE (1<<30) 777428d7b3dSmrg#define SS2_COLORSPACE_CONVERSION (1<<29) 778428d7b3dSmrg#define SS2_CHROMAKEY_SHIFT 27 779428d7b3dSmrg#define SS2_BASE_MIP_LEVEL_SHIFT 22 780428d7b3dSmrg#define SS2_BASE_MIP_LEVEL_MASK (0x1f<<22) 781428d7b3dSmrg#define SS2_MIP_FILTER_SHIFT 20 782428d7b3dSmrg#define SS2_MIP_FILTER_MASK (0x3<<20) 783428d7b3dSmrg#define MIPFILTER_NONE 0 784428d7b3dSmrg#define MIPFILTER_NEAREST 1 785428d7b3dSmrg#define MIPFILTER_LINEAR 3 786428d7b3dSmrg#define SS2_MAG_FILTER_SHIFT 17 787428d7b3dSmrg#define SS2_MAG_FILTER_MASK (0x7<<17) 788428d7b3dSmrg#define FILTER_NEAREST 0 789428d7b3dSmrg#define FILTER_LINEAR 1 790428d7b3dSmrg#define FILTER_ANISOTROPIC 2 791428d7b3dSmrg#define FILTER_4X4_1 3 792428d7b3dSmrg#define FILTER_4X4_2 4 793428d7b3dSmrg#define FILTER_4X4_FLAT 5 794428d7b3dSmrg#define FILTER_6X5_MONO 6 /* XXX - check */ 795428d7b3dSmrg#define SS2_MIN_FILTER_SHIFT 14 796428d7b3dSmrg#define SS2_MIN_FILTER_MASK (0x7<<14) 797428d7b3dSmrg#define SS2_LOD_BIAS_SHIFT 5 798428d7b3dSmrg#define SS2_LOD_BIAS_ONE (0x10<<5) 799428d7b3dSmrg#define SS2_LOD_BIAS_MASK (0x1ff<<5) 800428d7b3dSmrg/* Shadow requires: 801428d7b3dSmrg * MT_X8{I,L,A}24 or MT_{I,L,A}16 texture format 802428d7b3dSmrg * FILTER_4X4_x MIN and MAG filters 803428d7b3dSmrg */ 804428d7b3dSmrg#define SS2_SHADOW_ENABLE (1<<4) 805428d7b3dSmrg#define SS2_MAX_ANISO_MASK (1<<3) 806428d7b3dSmrg#define SS2_MAX_ANISO_2 (0<<3) 807428d7b3dSmrg#define SS2_MAX_ANISO_4 (1<<3) 808428d7b3dSmrg#define SS2_SHADOW_FUNC_SHIFT 0 809428d7b3dSmrg#define SS2_SHADOW_FUNC_MASK (0x7<<0) 810428d7b3dSmrg/* SS2_SHADOW_FUNC values: see COMPAREFUNC_* */ 811428d7b3dSmrg 812428d7b3dSmrg#define SS3_MIN_LOD_SHIFT 24 813428d7b3dSmrg#define SS3_MIN_LOD_ONE (0x10<<24) 814428d7b3dSmrg#define SS3_MIN_LOD_MASK (0xff<<24) 815428d7b3dSmrg#define SS3_KILL_PIXEL_ENABLE (1<<17) 816428d7b3dSmrg#define SS3_TCX_ADDR_MODE_SHIFT 12 817428d7b3dSmrg#define SS3_TCX_ADDR_MODE_MASK (0x7<<12) 818428d7b3dSmrg#define TEXCOORDMODE_WRAP 0 819428d7b3dSmrg#define TEXCOORDMODE_MIRROR 1 820428d7b3dSmrg#define TEXCOORDMODE_CLAMP_EDGE 2 821428d7b3dSmrg#define TEXCOORDMODE_CUBE 3 822428d7b3dSmrg#define TEXCOORDMODE_CLAMP_BORDER 4 823428d7b3dSmrg#define TEXCOORDMODE_MIRROR_ONCE 5 824428d7b3dSmrg#define SS3_TCY_ADDR_MODE_SHIFT 9 825428d7b3dSmrg#define SS3_TCY_ADDR_MODE_MASK (0x7<<9) 826428d7b3dSmrg#define SS3_TCZ_ADDR_MODE_SHIFT 6 827428d7b3dSmrg#define SS3_TCZ_ADDR_MODE_MASK (0x7<<6) 828428d7b3dSmrg#define SS3_NORMALIZED_COORDS (1<<5) 829428d7b3dSmrg#define SS3_TEXTUREMAP_INDEX_SHIFT 1 830428d7b3dSmrg#define SS3_TEXTUREMAP_INDEX_MASK (0xf<<1) 831428d7b3dSmrg#define SS3_DEINTERLACER_ENABLE (1<<0) 832428d7b3dSmrg 833428d7b3dSmrg#define SS4_BORDER_COLOR_MASK (~0) 834428d7b3dSmrg 835428d7b3dSmrg/* 3DSTATE_SPAN_STIPPLE, p258 836428d7b3dSmrg */ 837428d7b3dSmrg#define _3DSTATE_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 838428d7b3dSmrg#define ST1_ENABLE (1<<16) 839428d7b3dSmrg#define ST1_MASK (0xffff) 840428d7b3dSmrg 841428d7b3dSmrg#define FLUSH_MAP_CACHE (1<<0) 842428d7b3dSmrg#define FLUSH_RENDER_CACHE (1<<1) 843428d7b3dSmrg 844428d7b3dSmrg#endif 845