1/* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Xiang Haihao <haihao.xiang@intel.com> 25 * 26 */ 27 28#ifndef _I915_STRUCTS_H 29#define _I915_STRUCTS_H 30 31#include <stdint.h> 32 33/* BLT */ 34#define CMD_2D 0x02 35#define OPC_COLOR_BLT (0x40) 36 37struct i915_color_blt { 38 struct { 39 unsigned length:5; 40 unsigned pad0:15; 41 unsigned bpp_mask:2; 42 unsigned opcode:7; 43 unsigned type:3; 44 } dw0; 45 46 struct { 47 unsigned pitch:16; 48 unsigned rop:8; 49 unsigned color_depth:2; 50 unsigned pad0:6; 51 } dw1; 52 53 struct { 54 unsigned width:16; 55 unsigned height:16; 56 } dw2; 57 58 struct { 59 unsigned address; 60 } dw3; 61 62 struct { 63 unsigned pattern; 64 } dw4; 65}; 66 67/* 3D_INSTRUCTION */ 68#define CMD_3D 0x03 69#define OPCODE_3D(x) (CMD_3D << 29 | (x) << 16) 70 71#define OPC_3DMPEG_MACROBLOCK_IPICTURE (0x01 + (0x1e << 5)) 72#define OPC_3DMPEG_SET_ORIGIN (0x10 + (0x1e << 5)) 73#define OPC_3DMPEG_MACROBLOCK (0x11 + (0x1e << 5)) 74#define OPC_3DMPEG_SLICE (0x12 + (0x1e << 5)) 75#define OPC_3DMPEG_QM_PALETTE_LOAD (0x13 + (0x1e << 5)) 76 77#define OPC_3DSTATE_SCISSOR_ENABLE (0x10 + (0x1c << 5)) 78 79#define OPC_3DSTATE_MAP_STATE (0x00 + (0x1d << 8)) 80#define OPC_3DSTATE_SAMPLER_STATE (0x01 + (0x1d << 8)) 81#define OPC_3DSTATE_LOAD_STATE_IMMEDIATE_1 (0x04 + (0x1d << 8)) 82#define OP_3D_LOAD_STATE_IMMEDIATE_1 OPCODE_3D(OPC_3DSTATE_LOAD_STATE_IMMEDIATE_1) 83#define OPC_3DSTATE_PIXEL_SHADER_PROGRAM (0x05 + (0x1d << 8)) 84#define OPC_3DSTATE_PIXEL_SHADER_CONSTANTS (0x06 + (0x1d << 8)) 85#define OPC_3DSTATE_LOAD_INDIRECT (0x07 + (0x1d << 8)) 86#define OP_3D_LOAD_INDIRECT OPCODE_3D(OPC_3DSTATE_LOAD_INDIRECT) 87 88#define OPC_3DSTATE_MODES_5 (0x0c) 89#define OPC_3DSTATE_COORD_SET_BINDINGS (0x16) 90#define OPC_3DPRIMITIVE (0x1f) 91 92#define OPC_3DSTATE_DRAWING_RECTANGLE (0x80 + (0x1d << 8)) 93#define OPC_3DSTATE_SCISSOR_RECTANGLE (0x81 + (0x1d << 8)) 94#define OPC_3DSTATE_DEST_BUFFER_VARIABLES (0x85 + (0x1d << 8)) 95#define OPC_3DSTATE_DEST_BUFFER_VARIABLES_MPEG (0x87 + (0x1d << 8)) 96#define OPC_3DSTATE_BUFFER_INFO (0x8e + (0x1d << 8)) 97 98/* 99 * 3DMPEG instructions 100 */ 101struct i915_3dmpeg_macroblock_header { 102 struct { 103 unsigned length:19; 104 unsigned opcode:10; 105 unsigned type:3; 106 } dw0; 107 108 struct { 109 unsigned mb_intra:1; 110 unsigned forward:1; 111 unsigned backward:1; 112 unsigned h263_4mv:1; 113 unsigned pad0:1; 114 unsigned dct_type:1; 115 unsigned pad1:2; 116 unsigned motion_type:2; 117 unsigned pad2:2; 118 unsigned vertical_field_select:4; 119 unsigned coded_block_pattern:6; 120 unsigned pad3:2; 121 unsigned skipped_macroblocks:7; 122 unsigned pad4:1; 123 } dw1; 124}; 125 126struct i915_3dmpeg_macroblock_0mv { 127 struct i915_3dmpeg_macroblock_header header; 128}; 129 130struct i915_3dmpeg_macroblock_1fbmv { 131 struct i915_3dmpeg_macroblock_header header; 132 unsigned dw2; 133 unsigned dw3; 134}; 135struct i915_3dmpeg_macroblock_2fbmv { 136 struct i915_3dmpeg_macroblock_header header; 137 unsigned dw2; 138 unsigned dw3; 139 unsigned dw4; 140 unsigned dw5; 141}; 142 143struct i915_3dmpeg_macroblock_5fmv { 144 struct i915_3dmpeg_macroblock_header header; 145 unsigned dw2; 146 unsigned dw3; 147 unsigned dw4; 148 unsigned dw5; 149 unsigned dw6; 150}; 151 152struct i915_3dmpeg_macroblock_ipicture { 153 struct { 154 unsigned pad0:5; 155 unsigned dct_type:1; 156 unsigned pad1:13; 157 unsigned opcode:10; 158 unsigned type:3; 159 } dw0; 160}; 161 162struct i915_3dmpeg_set_origin { 163 struct { 164 unsigned length:19; 165 unsigned opcode:10; 166 unsigned type:3; 167 } dw0; 168 169 struct { 170 unsigned v_origin:7; 171 unsigned pad0:1; 172 unsigned h_origin:7; 173 unsigned pad1:17; 174 } dw1; 175}; 176 177struct i915_3dmpeg_slice { 178 struct { 179 unsigned length:19; 180 unsigned opcode:10; 181 unsigned type:3; 182 } dw0; 183 184 struct { 185 unsigned fst_mb_bit_off:3; 186 unsigned pad0:5; 187 unsigned mb_count:7; 188 unsigned pad1:1; 189 unsigned v_position:7; 190 unsigned pad2:1; 191 unsigned h_position:7; 192 unsigned pad3:1; 193 } dw1; 194 195 struct { 196 unsigned length_minus_one:17; 197 unsigned pad0:7; 198 unsigned qt_scale_code:5; 199 unsigned pad1:3; 200 } dw2; 201}; 202 203struct i915_3dmpeg_qm_palette_load { 204 struct { 205 unsigned length:4; 206 unsigned pad0:15; 207 unsigned opcode:10; 208 unsigned type:3; 209 } dw0; 210 211 unsigned quantmatrix[16]; 212}; 213 214/* 215 * 3DSTATE instruction 216 */ 217#define BUFFERID_COLOR_BACK 3 218#define BUFFERID_COLOR_AUX 4 219#define BUFFERID_MC_INTRA_CORR 5 220#define BUFFERID_DEPTH 7 221 222#define TILEWALK_XMAJOR 0 223#define TILEWALK_YMAJOR 1 224 225struct i915_3dstate_buffer_info { 226 struct { 227 unsigned length:16; 228 unsigned opcode:13; 229 unsigned type:3; 230 } dw0; 231 232 struct { 233 unsigned pad0:2; 234 unsigned pitch:12; 235 unsigned pad1:7; 236 unsigned walk:1; 237 unsigned tiled_surface:1; 238 unsigned fence_regs:1; 239 unsigned buffer_id:4; 240 unsigned aux_id:1; 241 unsigned pad2:3; 242 } dw1; 243 244 struct { 245 unsigned pad0:2; 246 unsigned base_address:27; 247 unsigned pad1:3; 248 } dw2; 249}; 250 251#define COLORBUFFER_8BIT 0x00 252#define COLORBUFFER_X1R5G5B5 0x01 253#define COLORBUFFER_R5G6B5 0x02 254#define COLORBUFFER_A8R8G8B8 0x03 255#define COLORBUFFER_YCRCB_SWAP 0x04 256#define COLORBUFFER_YCRCB_NORMAL 0x05 257#define COLORBUFFER_YCRCB_SWAPUV 0x06 258#define COLORBUFFER_YCRCB_SWAPUVY 0x07 259#define COLORBUFFER_A4R4G4B4 0x08 260#define COLORBUFFER_A1R5G5B5 0x09 261#define COLORBUFFER_A2R10G10B10 0x0a 262 263struct i915_3dstate_dest_buffer_variables { 264 struct { 265 unsigned length:16; 266 unsigned opcode:13; 267 unsigned type:3; 268 } dw0; 269 270 struct { 271 unsigned v_ls_offset:1; 272 unsigned v_ls:1; 273 unsigned depth_fmt:2; 274 unsigned pad0:4; 275 unsigned color_fmt:4; 276 unsigned yuv422_select:3; 277 unsigned pad1:1; 278 unsigned dest_v_bias:4; 279 unsigned dest_h_bias:4; 280 unsigned dither_enhancement:1; 281 unsigned linear_gamma:1; 282 unsigned dither_pattern:2; 283 unsigned lod_preclamp:1; 284 unsigned edt_zone:1; /* early depth test in zone rendering */ 285 unsigned texture_default_color:1; 286 unsigned edt_classic:1; /* early depth test in classic mode */ 287 } dw1; 288}; 289 290#define MPEG_DECODE_MC 0 291#define MPEG_DECODE_VLD_IDCT_MC 1 292 293#define MPEG_I_PICTURE 1 294#define MPEG_P_PICTURE 2 295#define MPEG_B_PICTURE 3 296 297#define MC_SUB_1H 0 298#define MC_SUB_2H 1 299#define MC_SUB_4H 2 300 301#define MC_SUB_1V 0 302#define MC_SUB_2V 1 303 304struct i915_3dstate_dest_buffer_variables_mpeg { 305 struct { 306 unsigned length:16; 307 unsigned opcode:13; 308 unsigned type:3; 309 } dw0; 310 311 struct { 312 unsigned picture_width:7; 313 unsigned pad0:1; 314 unsigned v_subsample_factor:2; 315 unsigned h_subsample_factor:2; 316 unsigned tff:1; 317 unsigned mismatch:1; 318 unsigned pad1:1; 319 unsigned intra8:1; 320 unsigned abort_on_error:8; 321 unsigned pad2:4; 322 unsigned bidir_avrg_control:1; 323 unsigned rcontrol:1; 324 unsigned decode_mode:2; 325 } dw1; 326 327 struct { 328 unsigned pad0:1; 329 unsigned picture_coding_type:2; 330 unsigned pad1:2; 331 unsigned scan_order:1; 332 unsigned pad2:2; 333 unsigned q_scale_type:1; 334 unsigned concealment:1; 335 unsigned fpf_dct:1; 336 unsigned pad3:2; 337 unsigned intra_dc:2; 338 unsigned intra_vlc:1; 339 unsigned f_code00:4; 340 unsigned f_code01:4; 341 unsigned f_code10:4; 342 unsigned f_code11:4; 343 } dw2; 344}; 345 346struct i915_mc_static_indirect_state_buffer { 347 struct i915_3dstate_buffer_info dest_y; 348 struct i915_3dstate_buffer_info dest_u; 349 struct i915_3dstate_buffer_info dest_v; 350 struct i915_3dstate_dest_buffer_variables dest_buf; 351 struct i915_3dstate_dest_buffer_variables_mpeg dest_buf_mpeg; 352 struct i915_3dstate_buffer_info corr; 353}; 354 355#define MAP_MAP0 0x0001 356#define MAP_MAP1 0x0002 357#define MAP_MAP2 0x0004 358#define MAP_MAP3 0x0008 359#define MAP_MAP4 0x0010 360#define MAP_MAP5 0x0020 361#define MAP_MAP6 0x0040 362#define MAP_MAP7 0x0080 363#define MAP_MAP8 0x0100 364#define MAP_MAP9 0x0200 365#define MAP_MAP10 0x0400 366#define MAP_MAP11 0x0800 367#define MAP_MAP12 0x1000 368#define MAP_MAP13 0x2000 369#define MAP_MAP14 0x4000 370#define MAP_MAP15 0x8000 371 372struct texture_map { 373 struct { 374 unsigned v_ls_offset:1; 375 unsigned v_ls:1; 376 unsigned base_address:27; 377 unsigned pad0:2; 378 unsigned untrusted:1; 379 } tm0; 380 381 struct { 382 unsigned tile_walk:1; 383 unsigned tiled_surface:1; 384 unsigned utilize_fence_regs:1; 385 unsigned texel_fmt:4; 386 unsigned surface_fmt:3; 387 unsigned width:11; 388 unsigned height:11; 389 } tm1; 390 391 struct { 392 unsigned depth:8; 393 unsigned mipmap_layout:1; 394 unsigned max_lod:6; 395 unsigned cube_face:6; 396 unsigned pitch:11; 397 } tm2; 398}; 399 400struct i915_3dstate_map_state { 401 struct { 402 unsigned length:6; 403 unsigned pad0:9; 404 unsigned retain:1; 405 unsigned opcode:13; 406 unsigned type:3; 407 } dw0; 408 409 struct { 410 unsigned map_mask:16; 411 unsigned pad0:16; 412 } dw1; 413}; 414 415struct i915_mc_map_state { 416 struct i915_3dstate_map_state y_map; 417 struct texture_map y_forward; 418 struct texture_map y_backward; 419 struct i915_3dstate_map_state u_map; 420 struct texture_map u_forward; 421 struct texture_map u_backward; 422 struct i915_3dstate_map_state v_map; 423 struct texture_map v_forward; 424 struct texture_map v_backward; 425}; 426 427#define SAMPLER_SAMPLER0 0x0001 428#define SAMPLER_SAMPLER1 0x0002 429#define SAMPLER_SAMPLER2 0x0004 430#define SAMPLER_SAMPLER3 0x0008 431#define SAMPLER_SAMPLER4 0x0010 432#define SAMPLER_SAMPLER5 0x0020 433#define SAMPLER_SAMPLER6 0x0040 434#define SAMPLER_SAMPLER7 0x0080 435#define SAMPLER_SAMPLER8 0x0100 436#define SAMPLER_SAMPLER9 0x0200 437#define SAMPLER_SAMPLER10 0x0400 438#define SAMPLER_SAMPLER11 0x0800 439#define SAMPLER_SAMPLER12 0x1000 440#define SAMPLER_SAMPLER13 0x2000 441#define SAMPLER_SAMPLER14 0x4000 442#define SAMPLER_SAMPLER15 0x8000 443 444#define MIPFILTER_NONE 0 445#define MIPFILTER_NEAREST 1 446#define MIPFILTER_LINEAR 3 447 448#define MAPFILTER_NEAREST 0 449#define MAPFILTER_LINEAR 1 450#define MAPFILTER_ANISOTROPIC 2 451#define MAPFILTER_4X4_1 3 452#define MAPFILTER_4X4_2 4 453#define MAPFILTER_4X4_FLAT 5 454#define MAPFILTER_MONO 6 455 456#define ANISORATIO_2 0 457#define ANISORATIO_4 1 458 459#define PREFILTEROP_ALWAYS 0 460#define PREFILTEROP_NEVER 1 461#define PREFILTEROP_LESS 2 462#define PREFILTEROP_EQUAL 3 463#define PREFILTEROP_LEQUAL 4 464#define PREFILTEROP_GREATER 5 465#define PREFILTEROP_NOTEQUAL 6 466#define PREFILTEROP_GEQUAL 7 467 468#define TEXCOORDMODE_WRAP 0 469#define TEXCOORDMODE_MIRROR 1 470#define TEXCOORDMODE_CLAMP 2 471#define TEXCOORDMODE_CUBE 3 472#define TEXCOORDMODE_CLAMP_BORDER 4 473#define TEXCOORDMODE_MIRROR_ONCE 5 474 475struct texture_sampler { 476 struct { 477 unsigned shadow_function:3; 478 unsigned max_anisotropy:1; 479 unsigned shadow_enable:1; 480 unsigned lod_bias:9; 481 unsigned min_filter:3; 482 unsigned mag_filter:3; 483 unsigned mip_filter:2; 484 unsigned base_level:5; 485 unsigned chromakey_index:2; 486 unsigned color_conversion:1; 487 unsigned planar2packet:1; 488 unsigned reverse_gamma:1; 489 } ts0; 490 491 struct { 492 unsigned east_deinterlacer:1; 493 unsigned map_index:4; 494 unsigned normalized_coor:1; 495 unsigned tcz_control:3; 496 unsigned tcy_control:3; 497 unsigned tcx_control:3; 498 unsigned chromakey_enable:1; 499 unsigned keyed_texture_filter:1; 500 unsigned kill_pixel:1; 501 unsigned pad0:6; 502 unsigned min_lod:8; 503 } ts1; 504 505 struct { 506 unsigned default_color; 507 } ts2; 508}; 509 510struct i915_3dstate_sampler_state { 511 struct { 512 unsigned length:6; 513 unsigned pad0:10; 514 unsigned opcode:13; 515 unsigned type:3; 516 } dw0; 517 518 struct { 519 unsigned sampler_masker:16; 520 unsigned pad0:16; 521 } dw1; 522 /* we always use two samplers for mc */ 523 struct texture_sampler sampler0; 524 struct texture_sampler sampler1; 525}; 526 527struct arithmetic_inst { 528 struct { 529 unsigned pad0:2; 530 unsigned src0_reg:5; 531 unsigned src0_reg_t:3; 532 unsigned dest_channel_mask:4; 533 unsigned dest_reg:4; 534 unsigned pad1:1; 535 unsigned dest_reg_t:3; 536 unsigned dest_saturate:1; 537 unsigned pad2:1; 538 unsigned opcode:5; 539 unsigned pad3:3; 540 } dw0; 541 542 struct { 543 unsigned src1_y_select:3; 544 unsigned src1_y_negate:1; 545 unsigned src1_x_select:3; 546 unsigned src1_x_negate:1; 547 unsigned src1_reg:5; 548 unsigned src1_reg_t:3; 549 unsigned src0_w_select:3; 550 unsigned src0_w_negate:1; 551 unsigned src0_z_select:3; 552 unsigned src0_z_negate:1; 553 unsigned src0_y_select:3; 554 unsigned src0_y_negate:1; 555 unsigned src0_x_select:3; 556 unsigned src0_x_negate:1; 557 } dw1; 558 559 struct { 560 unsigned src2_w_select:3; 561 unsigned src2_w_negate:1; 562 unsigned src2_z_select:3; 563 unsigned src2_z_negate:1; 564 unsigned src2_y_select:3; 565 unsigned src2_y_negate:1; 566 unsigned src2_x_select:3; 567 unsigned src2_x_negate:1; 568 unsigned src2_reg:5; 569 unsigned src2_reg_t:3; 570 unsigned src1_w_select:3; 571 unsigned src1_w_negate:1; 572 unsigned src1_z_select:3; 573 unsigned src1_z_negate:1; 574 } dw2; 575}; 576 577struct texture_inst { 578 struct { 579 unsigned sampler_reg:4; 580 unsigned pad0:10; 581 unsigned dest_reg:4; 582 unsigned pad1:1; 583 unsigned dest_reg_t:3; 584 unsigned pad2:2; 585 unsigned opcode:5; 586 unsigned pad3:3; 587 } dw0; 588 589 struct { 590 unsigned pad0:16; 591 unsigned address_reg:5; 592 unsigned pad1:3; 593 unsigned address_reg_t:3; 594 unsigned pad2:5; 595 } dw1; 596 597 struct { 598 unsigned pad0; 599 } dw2; 600}; 601 602struct declaration_inst { 603 struct { 604 unsigned pad0:10; 605 unsigned decl_channel_mask:4; 606 unsigned decl_reg:4; 607 unsigned pad1:1; 608 unsigned decl_reg_t:2; 609 unsigned pad2:1; 610 unsigned sampler_type:2; 611 unsigned opcode:5; 612 unsigned pad3:3; 613 } dw0; 614 615 struct { 616 unsigned pad0; 617 } dw1; 618 619 struct { 620 unsigned pad0; 621 } dw2; 622}; 623 624union shader_inst { 625 struct arithmetic_inst a; 626 struct texture_inst t; 627 struct declaration_inst d; 628}; 629 630struct i915_3dstate_pixel_shader_header { 631 unsigned length:9; 632 unsigned pad0:6; 633 unsigned retain:1; 634 unsigned opcode:13; 635 unsigned type:3; 636}; 637 638struct i915_3dstate_pixel_shader_program { 639 struct i915_3dstate_pixel_shader_header shader0; 640 /* mov oC, c0.0000 */ 641 uint32_t inst0[3]; 642 643 struct i915_3dstate_pixel_shader_header shader1; 644 /* dcl t0.xy */ 645 /* dcl t1.xy */ 646 /* dcl_2D s0 */ 647 /* texld r0, t0, s0 */ 648 /* mov oC, r0 */ 649 uint32_t inst1[3 * 5]; 650 651 struct i915_3dstate_pixel_shader_header shader2; 652 /* dcl t2.xy */ 653 /* dcl t3.xy */ 654 /* dcl_2D s1 */ 655 /* texld r0, t2, s1 */ 656 /* mov oC, r0 */ 657 uint32_t inst2[3 * 5]; 658 659 struct i915_3dstate_pixel_shader_header shader3; 660 /* dcl t0.xy */ 661 /* dcl t1.xy */ 662 /* dcl t2.xy */ 663 /* dcl t3.xy */ 664 /* dcl_2D s0 */ 665 /* dcl_2D s1 */ 666 /* texld r0, t0, s0 */ 667 /* texld r0, t2, s1 */ 668 /* add r0, r0, r1 */ 669 /* mov oC, r0 */ 670 uint32_t inst3[3 * 10]; 671}; 672 673#define REG_CR0 0x00000001 674#define REG_CR1 0x00000002 675#define REG_CR2 0x00000004 676#define REG_CR3 0x00000008 677#define REG_CR4 0x00000010 678#define REG_CR5 0x00000020 679#define REG_CR6 0x00000040 680#define REG_CR7 0x00000080 681#define REG_CR8 0x00000100 682#define REG_CR9 0x00000200 683#define REG_CR10 0x00000400 684#define REG_CR11 0x00000800 685#define REG_CR12 0x00001000 686#define REG_CR13 0x00002000 687#define REG_CR14 0x00004000 688#define REG_CR15 0x00008000 689#define REG_CR16 0x00010000 690#define REG_CR17 0x00020000 691#define REG_CR18 0x00040000 692#define REG_CR19 0x00080000 693#define REG_CR20 0x00100000 694#define REG_CR21 0x00200000 695#define REG_CR22 0x00400000 696#define REG_CR23 0x00800000 697#define REG_CR24 0x01000000 698#define REG_CR25 0x02000000 699#define REG_CR26 0x04000000 700#define REG_CR27 0x08000000 701#define REG_CR28 0x10000000 702#define REG_CR29 0x20000000 703#define REG_CR30 0x40000000 704#define REG_CR31 0x80000000 705 706struct shader_constant { 707 float x; 708 float y; 709 float z; 710 float w; 711}; 712 713struct i915_3dstate_pixel_shader_constants { 714 struct { 715 unsigned length:8; 716 unsigned pad0:8; 717 unsigned opcode:13; 718 unsigned type:3; 719 } dw0; 720 721 struct { 722 unsigned reg_mask; 723 } dw1; 724 /* we only need one constant */ 725 struct shader_constant value; 726}; 727 728#define BLOCK_SIS 0x01 729#define BLOCK_DIS 0x02 730#define BLOCK_SSB 0x04 731#define BLOCK_MSB 0x08 732#define BLOCK_PSP 0x10 733#define BLOCK_PSC 0x20 734#define BLOCK_MASK_SHIFT 8 735 736typedef struct _state_ddword { 737 struct { 738 unsigned valid:1; 739 unsigned force:1; 740 unsigned buffer_address:30; 741 } dw0; 742 743 struct { 744 unsigned length:9; 745 unsigned pad0:23; 746 } dw1; 747} sis_state, msb_state; 748#define STATE_VALID 0x1 749#define STATE_FORCE 0x2 750 751struct i915_3dstate_load_indirect { 752 struct { 753 unsigned length:8; 754 unsigned block_mask:6; 755 unsigned mem_select:1; 756 unsigned pad0:1; 757 unsigned opcode:13; 758 unsigned type:3; 759 } dw0; 760}; 761 762#define OP_3D_LOAD_INDIRECT_GFX_ADDR (1 << 14) 763 764#define TEXCOORDFMT_2FP 0x00 765#define TEXCOORDFMT_3FP 0x01 766#define TEXCOORDFMT_4FP 0x02 767#define TEXCOORDFMT_1FP 0x03 768#define TEXCOORDFMT_2FP_16 0x04 769#define TEXCOORDFMT_4FP_16 0x05 770#define TEXCOORDFMT_NOT_PRESENT 0x0f 771struct s2_dword { 772 unsigned set0_texcoord_fmt:4; 773 unsigned set1_texcoord_fmt:4; 774 unsigned set2_texcoord_fmt:4; 775 unsigned set3_texcoord_fmt:4; 776 unsigned set4_texcoord_fmt:4; 777 unsigned set5_texcoord_fmt:4; 778 unsigned set6_texcoord_fmt:4; 779 unsigned set7_texcoord_fmt:4; 780}; 781 782#define S3_SET0_PCD (1 << 0*4) 783#define S3_SET1_PCD (1 << 1*4) 784#define S3_SET2_PCD (1 << 2*4) 785#define S3_SET3_PCD (1 << 3*4) 786#define S3_SET4_PCD (1 << 4*4) 787#define S3_SET5_PCD (1 << 5*4) 788#define S3_SET6_PCD (1 << 6*4) 789#define S3_SET7_PCD (1 << 7*4) 790 791#define VERTEXHAS_XYZ 1 792#define VERTEXHAS_XYZW 2 793#define VERTEXHAS_XY 3 794#define VERTEXHAS_XYW 4 795 796#define CULLMODE_BOTH 0 797#define CULLMODE_NONE 1 798#define CULLMODE_CW 2 799#define CULLMODE_CCW 3 800 801#define SHADEMODE_LINEAR 0 802#define SHADEMODE_FLAT 1 803struct s4_dword { 804 unsigned anti_aliasing_enable:1; 805 unsigned sprite_point_enable:1; 806 unsigned fog_parameter_present:1; 807 unsigned local_depth_offset_enable:1; 808 unsigned force_specular_diffuse_color:1; 809 unsigned force_default_diffuse_color:1; 810 unsigned position_mask:3; 811 unsigned local_depth_offset_present:1; 812 unsigned diffuse_color_presetn:1; 813 unsigned specular_color_fog_factor_present:1; 814 unsigned point_width_present:1; 815 unsigned cull_mode:2; 816 unsigned color_shade_mode:1; 817 unsigned specular_shade_mode:1; 818 unsigned fog_shade_mode:1; 819 unsigned alpha_shade_mode:1; 820 unsigned line_width:4; 821 unsigned point_width:9; 822}; 823 824struct s5_dword { 825 unsigned logic_op_enable:1; 826 unsigned color_dither_enable:1; 827 unsigned stencil_test_enable:1; 828 unsigned stencil_buffer_write_enable:1; 829 unsigned stencil_pass_depth_pass_op:3; 830 unsigned stencil_pass_depth_fail_op:3; 831 unsigned stencil_fail_op:3; 832 unsigned stencil_test_function:3; 833 unsigned stencil_reference_value:8; 834 unsigned fog_enable:1; 835 unsigned global_depth_offset_enable:1; 836 unsigned last_pixel_enable:1; 837 unsigned force_default_point_width:1; 838 unsigned color_buffer_component_write_disable:4; 839}; 840 841#define S6_COLOR_BUFFER_WRITE (1 << 2) 842#define S6_DST_BLEND_FACTOR_SHIFT 4 843#define S6_SRC_BLEND_FACTOR_SHIFT 8 844#define S6_DEPTH_TEST_ENABLE (1 << 19) 845 846struct s7_dword { 847 unsigned global_depth_offset_const; 848}; 849 850#define OP_3D_LOAD_STATE_IMM_LOAD_S0 (1 << 4) 851#define OP_3D_LOAD_STATE_IMM_LOAD_S1 (1 << 5) 852#define OP_3D_LOAD_STATE_IMM_LOAD_S2 (1 << 6) 853#define OP_3D_LOAD_STATE_IMM_LOAD_S3 (1 << 7) 854#define OP_3D_LOAD_STATE_IMM_LOAD_S4 (1 << 8) 855#define OP_3D_LOAD_STATE_IMM_LOAD_S5 (1 << 9) 856#define OP_3D_LOAD_STATE_IMM_LOAD_S6 (1 << 10) 857#define OP_3D_LOAD_STATE_IMM_LOAD_S7 (1 << 11) 858 859struct i915_3dstate_scissor_rectangle { 860 struct { 861 unsigned length:16; 862 unsigned opcode:13; 863 unsigned type:3; 864 } dw0; 865 866 struct { 867 unsigned min_x:16; 868 unsigned min_y:16; 869 } dw1; 870 871 struct { 872 unsigned max_x:16; 873 unsigned max_y:16; 874 } dw2; 875}; 876 877#define VERTEX_INLINE 0x00 878#define VERTEX_INDIRECT 0x01 879 880#define PRIM_TRILIST 0x00 881#define PRIM_TRISTRIP 0x01 882#define PRIM_TRISTRIP_REVERSE 0x02 883#define PRIM_TRIFAN 0x03 884#define PRIM_POLYGON 0x04 885#define PRIM_LINELIST 0x05 886#define PRIM_LINESTRIP 0x06 887#define PRIM_RECTLIST 0x07 888#define PRIM_POINTLIST 0x08 889#define PRIM_DIB 0x09 890#define PRIM_CLEAR_RECT 0x0a 891#define PRIM_ZONE_INIT 0x0d 892 893struct texture_coordinate_set { 894 unsigned tcx; 895 unsigned tcy; 896}; 897 898struct vertex_data { 899 unsigned x; 900 unsigned y; 901 struct texture_coordinate_set tc0; 902 struct texture_coordinate_set tc1; 903}; 904 905struct i915_3dprimitive { 906 union { 907 struct { 908 unsigned length:18; 909 unsigned prim:5; 910 unsigned vertex_location:1; 911 unsigned opcode:5; 912 unsigned type:3; 913 } inline_prim; 914 915 struct { 916 unsigned vertex_count:16; 917 unsigned pad0:1; 918 unsigned vertex_access_mode:1; 919 unsigned prim:5; 920 unsigned vertex_location:1; 921 unsigned opcode:5; 922 unsigned type:3; 923 } indirect_prim; 924 } dw0; 925}; 926#endif /*_I915_STRUCTS_H */ 927