1 /**************************************************************************
2 *
3 * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifndef BRW_STRUCTS_H
29#define BRW_STRUCTS_H
30
31/* Command packets:
32 */
33struct header
34{
35   unsigned int length:16;
36   unsigned int opcode:16;
37};
38
39
40union header_union
41{
42   struct header bits;
43   unsigned int dword;
44};
45
46struct brw_3d_control
47{
48   struct
49   {
50      unsigned int length:8;
51      unsigned int notify_enable:1;
52      unsigned int pad:3;
53      unsigned int wc_flush_enable:1;
54      unsigned int depth_stall_enable:1;
55      unsigned int operation:2;
56      unsigned int opcode:16;
57   } header;
58
59   struct
60   {
61      unsigned int pad:2;
62      unsigned int dest_addr_type:1;
63      unsigned int dest_addr:29;
64   } dest;
65
66   unsigned int dword2;
67   unsigned int dword3;
68};
69
70
71struct brw_3d_primitive
72{
73   struct
74   {
75      unsigned int length:8;
76      unsigned int pad:2;
77      unsigned int topology:5;
78      unsigned int indexed:1;
79      unsigned int opcode:16;
80   } header;
81
82   unsigned int verts_per_instance;
83   unsigned int start_vert_location;
84   unsigned int instance_count;
85   unsigned int start_instance_location;
86   unsigned int base_vert_location;
87};
88
89/* These seem to be passed around as function args, so it works out
90 * better to keep them as #defines:
91 */
92#define BRW_FLUSH_READ_CACHE           0x1
93#define BRW_FLUSH_STATE_CACHE          0x2
94#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4
95#define BRW_FLUSH_SNAPSHOT_COUNTERS    0x8
96
97struct brw_mi_flush
98{
99   unsigned int flags:4;
100   unsigned int pad:12;
101   unsigned int opcode:16;
102};
103
104struct brw_vf_statistics
105{
106   unsigned int statistics_enable:1;
107   unsigned int pad:15;
108   unsigned int opcode:16;
109};
110
111
112
113struct brw_binding_table_pointers
114{
115   struct header header;
116   unsigned int vs;
117   unsigned int gs;
118   unsigned int clp;
119   unsigned int sf;
120   unsigned int wm;
121};
122
123
124struct brw_blend_constant_color
125{
126   struct header header;
127   float blend_constant_color[4];
128};
129
130
131struct brw_depthbuffer
132{
133   union header_union header;
134
135   union {
136      struct {
137	 unsigned int pitch:18;
138	 unsigned int format:3;
139	 unsigned int pad:4;
140	 unsigned int depth_offset_disable:1;
141	 unsigned int tile_walk:1;
142	 unsigned int tiled_surface:1;
143	 unsigned int pad2:1;
144	 unsigned int surface_type:3;
145      } bits;
146      unsigned int dword;
147   } dword1;
148
149   unsigned int dword2_base_addr;
150
151   union {
152      struct {
153	 unsigned int pad:1;
154	 unsigned int mipmap_layout:1;
155	 unsigned int lod:4;
156	 unsigned int width:13;
157	 unsigned int height:13;
158      } bits;
159      unsigned int dword;
160   } dword3;
161
162   union {
163      struct {
164	 unsigned int pad:12;
165	 unsigned int min_array_element:9;
166	 unsigned int depth:11;
167      } bits;
168      unsigned int dword;
169   } dword4;
170};
171
172struct brw_drawrect
173{
174   struct header header;
175   unsigned int xmin:16;
176   unsigned int ymin:16;
177   unsigned int xmax:16;
178   unsigned int ymax:16;
179   unsigned int xorg:16;
180   unsigned int yorg:16;
181};
182
183
184
185
186struct brw_global_depth_offset_clamp
187{
188   struct header header;
189   float depth_offset_clamp;
190};
191
192struct brw_indexbuffer
193{
194   union {
195      struct
196      {
197	 unsigned int length:8;
198	 unsigned int index_format:2;
199	 unsigned int cut_index_enable:1;
200	 unsigned int pad:5;
201	 unsigned int opcode:16;
202      } bits;
203      unsigned int dword;
204
205   } header;
206
207   unsigned int buffer_start;
208   unsigned int buffer_end;
209};
210
211
212struct brw_line_stipple
213{
214   struct header header;
215
216   struct
217   {
218      unsigned int pattern:16;
219      unsigned int pad:16;
220   } bits0;
221
222   struct
223   {
224      unsigned int repeat_count:9;
225      unsigned int pad:7;
226      unsigned int inverse_repeat_count:16;
227   } bits1;
228};
229
230
231struct brw_pipelined_state_pointers
232{
233   struct header header;
234
235   struct {
236      unsigned int pad:5;
237      unsigned int offset:27;
238   } vs;
239
240   struct
241   {
242      unsigned int enable:1;
243      unsigned int pad:4;
244      unsigned int offset:27;
245   } gs;
246
247   struct
248   {
249      unsigned int enable:1;
250      unsigned int pad:4;
251      unsigned int offset:27;
252   } clp;
253
254   struct
255   {
256      unsigned int pad:5;
257      unsigned int offset:27;
258   } sf;
259
260   struct
261   {
262      unsigned int pad:5;
263      unsigned int offset:27;
264   } wm;
265
266   struct
267   {
268      unsigned int pad:5;
269      unsigned int offset:27; /* KW: check me! */
270   } cc;
271};
272
273
274struct brw_polygon_stipple_offset
275{
276   struct header header;
277
278   struct {
279      unsigned int y_offset:5;
280      unsigned int pad:3;
281      unsigned int x_offset:5;
282      unsigned int pad0:19;
283   } bits0;
284};
285
286
287
288struct brw_polygon_stipple
289{
290   struct header header;
291   unsigned int stipple[32];
292};
293
294
295
296struct brw_pipeline_select
297{
298   struct
299   {
300      unsigned int pipeline_select:1;
301      unsigned int pad:15;
302      unsigned int opcode:16;
303   } header;
304};
305
306
307struct brw_pipe_control
308{
309   struct
310   {
311      unsigned int length:8;
312      unsigned int notify_enable:1;
313      unsigned int pad:2;
314      unsigned int instruction_state_cache_flush_enable:1;
315      unsigned int write_cache_flush_enable:1;
316      unsigned int depth_stall_enable:1;
317      unsigned int post_sync_operation:2;
318
319      unsigned int opcode:16;
320   } header;
321
322   struct
323   {
324      unsigned int pad:2;
325      unsigned int dest_addr_type:1;
326      unsigned int dest_addr:29;
327   } bits1;
328
329   unsigned int data0;
330   unsigned int data1;
331};
332
333
334struct brw_urb_fence
335{
336   struct
337   {
338      unsigned int length:8;
339      unsigned int vs_realloc:1;
340      unsigned int gs_realloc:1;
341      unsigned int clp_realloc:1;
342      unsigned int sf_realloc:1;
343      unsigned int vfe_realloc:1;
344      unsigned int cs_realloc:1;
345      unsigned int pad:2;
346      unsigned int opcode:16;
347   } header;
348
349   struct
350   {
351      unsigned int vs_fence:10;
352      unsigned int gs_fence:10;
353      unsigned int clp_fence:10;
354      unsigned int pad:2;
355   } bits0;
356
357   struct
358   {
359      unsigned int sf_fence:10;
360      unsigned int vf_fence:10;
361      unsigned int cs_fence:10;
362      unsigned int pad:2;
363   } bits1;
364};
365
366struct brw_constant_buffer_state /* previously brw_command_streamer */
367{
368   struct header header;
369
370   struct
371   {
372      unsigned int nr_urb_entries:3;
373      unsigned int pad:1;
374      unsigned int urb_entry_size:5;
375      unsigned int pad0:23;
376   } bits0;
377};
378
379struct brw_constant_buffer
380{
381   struct
382   {
383      unsigned int length:8;
384      unsigned int valid:1;
385      unsigned int pad:7;
386      unsigned int opcode:16;
387   } header;
388
389   struct
390   {
391      unsigned int buffer_length:6;
392      unsigned int buffer_address:26;
393   } bits0;
394};
395
396struct brw_state_base_address
397{
398   struct header header;
399
400   struct
401   {
402      unsigned int modify_enable:1;
403      unsigned int pad:4;
404      unsigned int general_state_address:27;
405   } bits0;
406
407   struct
408   {
409      unsigned int modify_enable:1;
410      unsigned int pad:4;
411      unsigned int surface_state_address:27;
412   } bits1;
413
414   struct
415   {
416      unsigned int modify_enable:1;
417      unsigned int pad:4;
418      unsigned int indirect_object_state_address:27;
419   } bits2;
420
421   struct
422   {
423      unsigned int modify_enable:1;
424      unsigned int pad:11;
425      unsigned int general_state_upper_bound:20;
426   } bits3;
427
428   struct
429   {
430      unsigned int modify_enable:1;
431      unsigned int pad:11;
432      unsigned int indirect_object_state_upper_bound:20;
433   } bits4;
434};
435
436struct brw_state_prefetch
437{
438   struct header header;
439
440   struct
441   {
442      unsigned int prefetch_count:3;
443      unsigned int pad:3;
444      unsigned int prefetch_pointer:26;
445   } bits0;
446};
447
448struct brw_system_instruction_pointer
449{
450   struct header header;
451
452   struct
453   {
454      unsigned int pad:4;
455      unsigned int system_instruction_pointer:28;
456   } bits0;
457};
458
459
460
461
462/* State structs for the various fixed function units:
463 */
464
465
466struct thread0
467{
468   unsigned int pad0:1;
469   unsigned int grf_reg_count:3;
470   unsigned int pad1:2;
471   unsigned int kernel_start_pointer:26;
472};
473
474struct thread1
475{
476   unsigned int ext_halt_exception_enable:1;
477   unsigned int sw_exception_enable:1;
478   unsigned int mask_stack_exception_enable:1;
479   unsigned int timeout_exception_enable:1;
480   unsigned int illegal_op_exception_enable:1;
481   unsigned int pad0:3;
482   unsigned int depth_coef_urb_read_offset:6;	/* WM only */
483   unsigned int pad1:2;
484   unsigned int floating_point_mode:1;
485   unsigned int thread_priority:1;
486   unsigned int binding_table_entry_count:8;
487   unsigned int pad3:5;
488   unsigned int single_program_flow:1;
489};
490
491struct thread2
492{
493   unsigned int per_thread_scratch_space:4;
494   unsigned int pad0:6;
495   unsigned int scratch_space_base_pointer:22;
496};
497
498
499struct thread3
500{
501   unsigned int dispatch_grf_start_reg:4;
502   unsigned int urb_entry_read_offset:6;
503   unsigned int pad0:1;
504   unsigned int urb_entry_read_length:6;
505   unsigned int pad1:1;
506   unsigned int const_urb_entry_read_offset:6;
507   unsigned int pad2:1;
508   unsigned int const_urb_entry_read_length:6;
509   unsigned int pad3:1;
510};
511
512
513
514struct brw_clip_unit_state
515{
516   struct thread0 thread0;
517   struct thread1 thread1;
518   struct thread2 thread2;
519   struct thread3 thread3;
520
521   struct
522   {
523      unsigned int pad0:9;
524      unsigned int gs_output_stats:1; /* not always */
525      unsigned int stats_enable:1;
526      unsigned int nr_urb_entries:7;
527      unsigned int pad1:1;
528      unsigned int urb_entry_allocation_size:5;
529      unsigned int pad2:1;
530      unsigned int max_threads:6; 	/* may be less */
531      unsigned int pad3:1;
532   } thread4;
533
534   struct
535   {
536      unsigned int pad0:13;
537      unsigned int clip_mode:3;
538      unsigned int userclip_enable_flags:8;
539      unsigned int userclip_must_clip:1;
540      unsigned int pad1:1;
541      unsigned int guard_band_enable:1;
542      unsigned int viewport_z_clip_enable:1;
543      unsigned int viewport_xy_clip_enable:1;
544      unsigned int vertex_position_space:1;
545      unsigned int api_mode:1;
546      unsigned int pad2:1;
547   } clip5;
548
549   struct
550   {
551      unsigned int pad0:5;
552      unsigned int clipper_viewport_state_ptr:27;
553   } clip6;
554
555
556   float viewport_xmin;
557   float viewport_xmax;
558   float viewport_ymin;
559   float viewport_ymax;
560};
561
562
563
564struct brw_cc_unit_state
565{
566   struct
567   {
568      unsigned int pad0:3;
569      unsigned int bf_stencil_pass_depth_pass_op:3;
570      unsigned int bf_stencil_pass_depth_fail_op:3;
571      unsigned int bf_stencil_fail_op:3;
572      unsigned int bf_stencil_func:3;
573      unsigned int bf_stencil_enable:1;
574      unsigned int pad1:2;
575      unsigned int stencil_write_enable:1;
576      unsigned int stencil_pass_depth_pass_op:3;
577      unsigned int stencil_pass_depth_fail_op:3;
578      unsigned int stencil_fail_op:3;
579      unsigned int stencil_func:3;
580      unsigned int stencil_enable:1;
581   } cc0;
582
583
584   struct
585   {
586      unsigned int bf_stencil_ref:8;
587      unsigned int stencil_write_mask:8;
588      unsigned int stencil_test_mask:8;
589      unsigned int stencil_ref:8;
590   } cc1;
591
592
593   struct
594   {
595      unsigned int logicop_enable:1;
596      unsigned int pad0:10;
597      unsigned int depth_write_enable:1;
598      unsigned int depth_test_function:3;
599      unsigned int depth_test:1;
600      unsigned int bf_stencil_write_mask:8;
601      unsigned int bf_stencil_test_mask:8;
602   } cc2;
603
604
605   struct
606   {
607      unsigned int pad0:8;
608      unsigned int alpha_test_func:3;
609      unsigned int alpha_test:1;
610      unsigned int blend_enable:1;
611      unsigned int ia_blend_enable:1;
612      unsigned int pad1:1;
613      unsigned int alpha_test_format:1;
614      unsigned int pad2:16;
615   } cc3;
616
617   struct
618   {
619      unsigned int pad0:5;
620      unsigned int cc_viewport_state_offset:27;
621   } cc4;
622
623   struct
624   {
625      unsigned int pad0:2;
626      unsigned int ia_dest_blend_factor:5;
627      unsigned int ia_src_blend_factor:5;
628      unsigned int ia_blend_function:3;
629      unsigned int statistics_enable:1;
630      unsigned int logicop_func:4;
631      unsigned int pad1:11;
632      unsigned int dither_enable:1;
633   } cc5;
634
635   struct
636   {
637      unsigned int clamp_post_alpha_blend:1;
638      unsigned int clamp_pre_alpha_blend:1;
639      unsigned int clamp_range:2;
640      unsigned int pad0:11;
641      unsigned int y_dither_offset:2;
642      unsigned int x_dither_offset:2;
643      unsigned int dest_blend_factor:5;
644      unsigned int src_blend_factor:5;
645      unsigned int blend_function:3;
646   } cc6;
647
648   struct {
649      union {
650	 float f;
651	 unsigned char ub[4];
652      } alpha_ref;
653   } cc7;
654};
655
656
657
658struct brw_sf_unit_state
659{
660   struct thread0 thread0;
661   struct {
662      unsigned int pad0:7;
663      unsigned int sw_exception_enable:1;
664      unsigned int pad1:3;
665      unsigned int mask_stack_exception_enable:1;
666      unsigned int pad2:1;
667      unsigned int illegal_op_exception_enable:1;
668      unsigned int pad3:2;
669      unsigned int floating_point_mode:1;
670      unsigned int thread_priority:1;
671      unsigned int binding_table_entry_count:8;
672      unsigned int pad4:5;
673      unsigned int single_program_flow:1;
674   } sf1;
675
676   struct thread2 thread2;
677   struct thread3 thread3;
678
679   struct
680   {
681      unsigned int pad0:10;
682      unsigned int stats_enable:1;
683      unsigned int nr_urb_entries:7;
684      unsigned int pad1:1;
685      unsigned int urb_entry_allocation_size:5;
686      unsigned int pad2:1;
687      unsigned int max_threads:6;
688      unsigned int pad3:1;
689   } thread4;
690
691   struct
692   {
693      unsigned int front_winding:1;
694      unsigned int viewport_transform:1;
695      unsigned int pad0:3;
696      unsigned int sf_viewport_state_offset:27;
697   } sf5;
698
699   struct
700   {
701      unsigned int pad0:9;
702      unsigned int dest_org_vbias:4;
703      unsigned int dest_org_hbias:4;
704      unsigned int scissor:1;
705      unsigned int disable_2x2_trifilter:1;
706      unsigned int disable_zero_pix_trifilter:1;
707      unsigned int point_rast_rule:2;
708      unsigned int line_endcap_aa_region_width:2;
709      unsigned int line_width:4;
710      unsigned int fast_scissor_disable:1;
711      unsigned int cull_mode:2;
712      unsigned int aa_enable:1;
713   } sf6;
714
715   struct
716   {
717      unsigned int point_size:11;
718      unsigned int use_point_size_state:1;
719      unsigned int subpixel_precision:1;
720      unsigned int sprite_point:1;
721      unsigned int pad0:11;
722      unsigned int trifan_pv:2;
723      unsigned int linestrip_pv:2;
724      unsigned int tristrip_pv:2;
725      unsigned int line_last_pixel_enable:1;
726   } sf7;
727
728};
729
730
731struct brw_gs_unit_state
732{
733   struct thread0 thread0;
734   struct thread1 thread1;
735   struct thread2 thread2;
736   struct thread3 thread3;
737
738   struct
739   {
740      unsigned int pad0:10;
741      unsigned int stats_enable:1;
742      unsigned int nr_urb_entries:7;
743      unsigned int pad1:1;
744      unsigned int urb_entry_allocation_size:5;
745      unsigned int pad2:1;
746      unsigned int max_threads:1;
747      unsigned int pad3:6;
748   } thread4;
749
750   struct
751   {
752      unsigned int sampler_count:3;
753      unsigned int pad0:2;
754      unsigned int sampler_state_pointer:27;
755   } gs5;
756
757
758   struct
759   {
760      unsigned int max_vp_index:4;
761      unsigned int pad0:26;
762      unsigned int reorder_enable:1;
763      unsigned int pad1:1;
764   } gs6;
765};
766
767
768struct brw_vs_unit_state
769{
770   struct thread0 thread0;
771   struct thread1 thread1;
772   struct thread2 thread2;
773   struct thread3 thread3;
774
775   struct
776   {
777      unsigned int pad0:10;
778      unsigned int stats_enable:1;
779      unsigned int nr_urb_entries:7;
780      unsigned int pad1:1;
781      unsigned int urb_entry_allocation_size:5;
782      unsigned int pad2:1;
783      unsigned int max_threads:4;
784      unsigned int pad3:3;
785   } thread4;
786
787   struct
788   {
789      unsigned int sampler_count:3;
790      unsigned int pad0:2;
791      unsigned int sampler_state_pointer:27;
792   } vs5;
793
794   struct
795   {
796      unsigned int vs_enable:1;
797      unsigned int vert_cache_disable:1;
798      unsigned int pad0:30;
799   } vs6;
800};
801
802
803struct brw_wm_unit_state
804{
805   struct thread0 thread0;
806   struct thread1 thread1;
807   struct thread2 thread2;
808   struct thread3 thread3;
809
810   struct {
811      unsigned int stats_enable:1;
812      unsigned int pad0:1;
813      unsigned int sampler_count:3;
814      unsigned int sampler_state_pointer:27;
815   } wm4;
816
817   struct
818   {
819      unsigned int enable_8_pix:1;
820      unsigned int enable_16_pix:1;
821      unsigned int enable_32_pix:1;
822      unsigned int pad0:7;
823      unsigned int legacy_global_depth_bias:1;
824      unsigned int line_stipple:1;
825      unsigned int depth_offset:1;
826      unsigned int polygon_stipple:1;
827      unsigned int line_aa_region_width:2;
828      unsigned int line_endcap_aa_region_width:2;
829      unsigned int early_depth_test:1;
830      unsigned int thread_dispatch_enable:1;
831      unsigned int program_uses_depth:1;
832      unsigned int program_computes_depth:1;
833      unsigned int program_uses_killpixel:1;
834      unsigned int legacy_line_rast: 1;
835      unsigned int transposed_urb_read:1;
836      unsigned int max_threads:7;
837   } wm5;
838
839   float global_depth_offset_constant;
840   float global_depth_offset_scale;
841
842   struct {
843      unsigned int pad0:1;
844      unsigned int grf_reg_count_1:3;
845      unsigned int pad1:2;
846      unsigned int kernel_start_pointer_1:26;
847   } wm8;
848
849   struct {
850      unsigned int pad0:1;
851      unsigned int grf_reg_count_2:3;
852      unsigned int pad1:2;
853      unsigned int kernel_start_pointer_2:26;
854   } wm9;
855
856   struct {
857      unsigned int pad0:1;
858      unsigned int grf_reg_count_3:3;
859      unsigned int pad1:2;
860      unsigned int kernel_start_pointer_3:26;
861   } wm10;
862};
863
864/* The hardware supports two different modes for border color. The
865 * default (OpenGL) mode uses floating-point color channels, while the
866 * legacy mode uses 4 bytes.
867 *
868 * More significantly, the legacy mode respects the components of the
869 * border color for channels not present in the source, (whereas the
870 * default mode will ignore the border color's alpha channel and use
871 * alpha==1 for an RGB source, for example).
872 *
873 * The legacy mode matches the semantics specified by the Render
874 * extension.
875 */
876struct brw_sampler_default_border_color {
877   float color[4];
878};
879
880struct brw_sampler_legacy_border_color {
881   uint8_t color[4];
882};
883
884struct brw_sampler_state
885{
886
887   struct
888   {
889      unsigned int shadow_function:3;
890      unsigned int lod_bias:11;
891      unsigned int min_filter:3;
892      unsigned int mag_filter:3;
893      unsigned int mip_filter:2;
894      unsigned int base_level:5;
895      unsigned int pad:1;
896      unsigned int lod_preclamp:1;
897      unsigned int border_color_mode:1;
898      unsigned int pad0:1;
899      unsigned int disable:1;
900   } ss0;
901
902   struct
903   {
904      unsigned int r_wrap_mode:3;
905      unsigned int t_wrap_mode:3;
906      unsigned int s_wrap_mode:3;
907      unsigned int pad:3;
908      unsigned int max_lod:10;
909      unsigned int min_lod:10;
910   } ss1;
911
912
913   struct
914   {
915      unsigned int pad:5;
916      unsigned int border_color_pointer:27;
917   } ss2;
918
919   struct
920   {
921      unsigned int pad:19;
922      unsigned int max_aniso:3;
923      unsigned int chroma_key_mode:1;
924      unsigned int chroma_key_index:2;
925      unsigned int chroma_key_enable:1;
926      unsigned int monochrome_filter_width:3;
927      unsigned int monochrome_filter_height:3;
928   } ss3;
929};
930
931
932struct brw_clipper_viewport
933{
934   float xmin;
935   float xmax;
936   float ymin;
937   float ymax;
938};
939
940struct brw_cc_viewport
941{
942   float min_depth;
943   float max_depth;
944};
945
946struct brw_sf_viewport
947{
948   struct {
949      float m00;
950      float m11;
951      float m22;
952      float m30;
953      float m31;
954      float m32;
955   } viewport;
956
957   struct {
958      short xmin;
959      short ymin;
960      short xmax;
961      short ymax;
962   } scissor;
963};
964
965/* Documented in the subsystem/shared-functions/sampler chapter...
966 */
967struct brw_surface_state
968{
969   struct {
970      unsigned int cube_pos_z:1;
971      unsigned int cube_neg_z:1;
972      unsigned int cube_pos_y:1;
973      unsigned int cube_neg_y:1;
974      unsigned int cube_pos_x:1;
975      unsigned int cube_neg_x:1;
976      unsigned int pad:3;
977      unsigned int render_cache_read_mode:1;
978      unsigned int mipmap_layout_mode:1;
979      unsigned int vert_line_stride_ofs:1;
980      unsigned int vert_line_stride:1;
981      unsigned int color_blend:1;
982      unsigned int writedisable_blue:1;
983      unsigned int writedisable_green:1;
984      unsigned int writedisable_red:1;
985      unsigned int writedisable_alpha:1;
986      unsigned int surface_format:9;
987      unsigned int data_return_format:1;
988      unsigned int pad0:1;
989      unsigned int surface_type:3;
990   } ss0;
991
992   struct {
993      unsigned int base_addr;
994   } ss1;
995
996   struct {
997      unsigned int render_target_rotation:2;
998      unsigned int mip_count:4;
999      unsigned int width:13;
1000      unsigned int height:13;
1001   } ss2;
1002
1003   struct {
1004      unsigned int tile_walk:1;
1005      unsigned int tiled_surface:1;
1006      unsigned int pad:1;
1007      unsigned int pitch:18;
1008      unsigned int depth:11;
1009   } ss3;
1010
1011   struct {
1012      unsigned int pad:19;
1013      unsigned int min_array_elt:9;
1014      unsigned int min_lod:4;
1015   } ss4;
1016
1017   struct {
1018       unsigned int pad:20;
1019       unsigned int y_offset:4;
1020       unsigned int pad2:1;
1021       unsigned int x_offset:7;
1022   } ss5;
1023};
1024
1025
1026
1027struct brw_vertex_buffer_state
1028{
1029   struct {
1030      unsigned int pitch:11;
1031      unsigned int pad:15;
1032      unsigned int access_type:1;
1033      unsigned int vb_index:5;
1034   } vb0;
1035
1036   unsigned int start_addr;
1037   unsigned int max_index;
1038#if 1
1039   unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */
1040#endif
1041};
1042
1043#define BRW_VBP_MAX 17
1044
1045struct brw_vb_array_state {
1046   struct header header;
1047   struct brw_vertex_buffer_state vb[BRW_VBP_MAX];
1048};
1049
1050
1051struct brw_vertex_element_state
1052{
1053   struct
1054   {
1055      unsigned int src_offset:11;
1056      unsigned int pad:5;
1057      unsigned int src_format:9;
1058      unsigned int pad0:1;
1059      unsigned int valid:1;
1060      unsigned int vertex_buffer_index:5;
1061   } ve0;
1062
1063   struct
1064   {
1065      unsigned int dst_offset:8;
1066      unsigned int pad:8;
1067      unsigned int vfcomponent3:4;
1068      unsigned int vfcomponent2:4;
1069      unsigned int vfcomponent1:4;
1070      unsigned int vfcomponent0:4;
1071   } ve1;
1072};
1073
1074#define BRW_VEP_MAX 18
1075
1076struct brw_vertex_element_packet {
1077   struct header header;
1078   struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */
1079};
1080
1081
1082struct brw_urb_immediate {
1083   unsigned int opcode:4;
1084   unsigned int offset:6;
1085   unsigned int swizzle_control:2;
1086   unsigned int pad:1;
1087   unsigned int allocate:1;
1088   unsigned int used:1;
1089   unsigned int complete:1;
1090   unsigned int response_length:4;
1091   unsigned int msg_length:4;
1092   unsigned int msg_target:4;
1093   unsigned int pad1:3;
1094   unsigned int end_of_thread:1;
1095};
1096
1097/* Instruction format for the execution units:
1098 */
1099
1100struct brw_instruction
1101{
1102   struct
1103   {
1104      unsigned int opcode:7;
1105      unsigned int pad:1;
1106      unsigned int access_mode:1;
1107      unsigned int mask_control:1;
1108      unsigned int dependency_control:2;
1109      unsigned int compression_control:2;
1110      unsigned int thread_control:2;
1111      unsigned int predicate_control:4;
1112      unsigned int predicate_inverse:1;
1113      unsigned int execution_size:3;
1114      unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */
1115      unsigned int pad0:2;
1116      unsigned int debug_control:1;
1117      unsigned int saturate:1;
1118   } header;
1119
1120   union {
1121      struct
1122      {
1123	 unsigned int dest_reg_file:2;
1124	 unsigned int dest_reg_type:3;
1125	 unsigned int src0_reg_file:2;
1126	 unsigned int src0_reg_type:3;
1127	 unsigned int src1_reg_file:2;
1128	 unsigned int src1_reg_type:3;
1129	 unsigned int pad:1;
1130	 unsigned int dest_subreg_nr:5;
1131	 unsigned int dest_reg_nr:8;
1132	 unsigned int dest_horiz_stride:2;
1133	 unsigned int dest_address_mode:1;
1134      } da1;
1135
1136      struct
1137      {
1138	 unsigned int dest_reg_file:2;
1139	 unsigned int dest_reg_type:3;
1140	 unsigned int src0_reg_file:2;
1141	 unsigned int src0_reg_type:3;
1142	 unsigned int pad:6;
1143	 int dest_indirect_offset:10;	/* offset against the deref'd address reg */
1144	 unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */
1145	 unsigned int dest_horiz_stride:2;
1146	 unsigned int dest_address_mode:1;
1147      } ia1;
1148
1149      struct
1150      {
1151	 unsigned int dest_reg_file:2;
1152	 unsigned int dest_reg_type:3;
1153	 unsigned int src0_reg_file:2;
1154	 unsigned int src0_reg_type:3;
1155	 unsigned int src1_reg_file:2;
1156	 unsigned int src1_reg_type:3;
1157	 unsigned int pad0:1;
1158	 unsigned int dest_writemask:4;
1159	 unsigned int dest_subreg_nr:1;
1160	 unsigned int dest_reg_nr:8;
1161	 unsigned int pad1:2;
1162	 unsigned int dest_address_mode:1;
1163      } da16;
1164
1165      struct
1166      {
1167	 unsigned int dest_reg_file:2;
1168	 unsigned int dest_reg_type:3;
1169	 unsigned int src0_reg_file:2;
1170	 unsigned int src0_reg_type:3;
1171	 unsigned int pad0:6;
1172	 unsigned int dest_writemask:4;
1173	 int dest_indirect_offset:6;
1174	 unsigned int dest_subreg_nr:3;
1175	 unsigned int pad1:2;
1176	 unsigned int dest_address_mode:1;
1177      } ia16;
1178   } bits1;
1179
1180
1181   union {
1182      struct
1183      {
1184	 unsigned int src0_subreg_nr:5;
1185	 unsigned int src0_reg_nr:8;
1186	 unsigned int src0_abs:1;
1187	 unsigned int src0_negate:1;
1188	 unsigned int src0_address_mode:1;
1189	 unsigned int src0_horiz_stride:2;
1190	 unsigned int src0_width:3;
1191	 unsigned int src0_vert_stride:4;
1192	 unsigned int flag_reg_nr:1;
1193	 unsigned int pad:6;
1194      } da1;
1195
1196      struct
1197      {
1198	 int src0_indirect_offset:10;
1199	 unsigned int src0_subreg_nr:3;
1200	 unsigned int src0_abs:1;
1201	 unsigned int src0_negate:1;
1202	 unsigned int src0_address_mode:1;
1203	 unsigned int src0_horiz_stride:2;
1204	 unsigned int src0_width:3;
1205	 unsigned int src0_vert_stride:4;
1206	 unsigned int flag_reg_nr:1;
1207	 unsigned int pad:6;
1208      } ia1;
1209
1210      struct
1211      {
1212	 unsigned int src0_swz_x:2;
1213	 unsigned int src0_swz_y:2;
1214	 unsigned int src0_subreg_nr:1;
1215	 unsigned int src0_reg_nr:8;
1216	 unsigned int src0_abs:1;
1217	 unsigned int src0_negate:1;
1218	 unsigned int src0_address_mode:1;
1219	 unsigned int src0_swz_z:2;
1220	 unsigned int src0_swz_w:2;
1221	 unsigned int pad0:1;
1222	 unsigned int src0_vert_stride:4;
1223	 unsigned int flag_reg_nr:1;
1224	 unsigned int pad1:6;
1225      } da16;
1226
1227      struct
1228      {
1229	 unsigned int src0_swz_x:2;
1230	 unsigned int src0_swz_y:2;
1231	 int src0_indirect_offset:6;
1232	 unsigned int src0_subreg_nr:3;
1233	 unsigned int src0_abs:1;
1234	 unsigned int src0_negate:1;
1235	 unsigned int src0_address_mode:1;
1236	 unsigned int src0_swz_z:2;
1237	 unsigned int src0_swz_w:2;
1238	 unsigned int pad0:1;
1239	 unsigned int src0_vert_stride:4;
1240	 unsigned int flag_reg_nr:1;
1241	 unsigned int pad1:6;
1242      } ia16;
1243
1244   } bits2;
1245
1246   union
1247   {
1248      struct
1249      {
1250	 unsigned int src1_subreg_nr:5;
1251	 unsigned int src1_reg_nr:8;
1252	 unsigned int src1_abs:1;
1253	 unsigned int src1_negate:1;
1254	 unsigned int pad:1;
1255	 unsigned int src1_horiz_stride:2;
1256	 unsigned int src1_width:3;
1257	 unsigned int src1_vert_stride:4;
1258	 unsigned int pad0:7;
1259      } da1;
1260
1261      struct
1262      {
1263	 unsigned int src1_swz_x:2;
1264	 unsigned int src1_swz_y:2;
1265	 unsigned int src1_subreg_nr:1;
1266	 unsigned int src1_reg_nr:8;
1267	 unsigned int src1_abs:1;
1268	 unsigned int src1_negate:1;
1269	 unsigned int pad0:1;
1270	 unsigned int src1_swz_z:2;
1271	 unsigned int src1_swz_w:2;
1272	 unsigned int pad1:1;
1273	 unsigned int src1_vert_stride:4;
1274	 unsigned int pad2:7;
1275      } da16;
1276
1277      struct
1278      {
1279	 int  src1_indirect_offset:10;
1280	 unsigned int src1_subreg_nr:3;
1281	 unsigned int src1_abs:1;
1282	 unsigned int src1_negate:1;
1283	 unsigned int pad0:1;
1284	 unsigned int src1_horiz_stride:2;
1285	 unsigned int src1_width:3;
1286	 unsigned int src1_vert_stride:4;
1287	 unsigned int flag_reg_nr:1;
1288	 unsigned int pad1:6;
1289      } ia1;
1290
1291      struct
1292      {
1293	 unsigned int src1_swz_x:2;
1294	 unsigned int src1_swz_y:2;
1295	 int  src1_indirect_offset:6;
1296	 unsigned int src1_subreg_nr:3;
1297	 unsigned int src1_abs:1;
1298	 unsigned int src1_negate:1;
1299	 unsigned int pad0:1;
1300	 unsigned int src1_swz_z:2;
1301	 unsigned int src1_swz_w:2;
1302	 unsigned int pad1:1;
1303	 unsigned int src1_vert_stride:4;
1304	 unsigned int flag_reg_nr:1;
1305	 unsigned int pad2:6;
1306      } ia16;
1307
1308
1309      struct
1310      {
1311	 int  jump_count:16;	/* note: signed */
1312	 unsigned int  pop_count:4;
1313	 unsigned int  pad0:12;
1314      } if_else;
1315
1316      struct {
1317	 unsigned int function:4;
1318	 unsigned int int_type:1;
1319	 unsigned int precision:1;
1320	 unsigned int saturate:1;
1321	 unsigned int data_type:1;
1322	 unsigned int pad0:8;
1323	 unsigned int response_length:4;
1324	 unsigned int msg_length:4;
1325	 unsigned int msg_target:4;
1326	 unsigned int pad1:3;
1327	 unsigned int end_of_thread:1;
1328      } math;
1329
1330      struct {
1331	 unsigned int binding_table_index:8;
1332	 unsigned int sampler:4;
1333	 unsigned int return_format:2;
1334	 unsigned int msg_type:2;
1335	 unsigned int response_length:4;
1336	 unsigned int msg_length:4;
1337	 unsigned int msg_target:4;
1338	 unsigned int pad1:3;
1339	 unsigned int end_of_thread:1;
1340      } sampler;
1341
1342      struct brw_urb_immediate urb;
1343
1344      struct {
1345	 unsigned int binding_table_index:8;
1346	 unsigned int msg_control:4;
1347	 unsigned int msg_type:2;
1348	 unsigned int target_cache:2;
1349	 unsigned int response_length:4;
1350	 unsigned int msg_length:4;
1351	 unsigned int msg_target:4;
1352	 unsigned int pad1:3;
1353	 unsigned int end_of_thread:1;
1354      } dp_read;
1355
1356      struct {
1357	 unsigned int binding_table_index:8;
1358	 unsigned int msg_control:3;
1359	 unsigned int pixel_scoreboard_clear:1;
1360	 unsigned int msg_type:3;
1361	 unsigned int send_commit_msg:1;
1362	 unsigned int response_length:4;
1363	 unsigned int msg_length:4;
1364	 unsigned int msg_target:4;
1365	 unsigned int pad1:3;
1366	 unsigned int end_of_thread:1;
1367      } dp_write;
1368
1369      struct {
1370	 unsigned int pad:16;
1371	 unsigned int response_length:4;
1372	 unsigned int msg_length:4;
1373	 unsigned int msg_target:4;
1374	 unsigned int pad1:3;
1375	 unsigned int end_of_thread:1;
1376      } generic;
1377
1378      unsigned int ud;
1379   } bits3;
1380};
1381
1382/* media pipeline */
1383
1384struct brw_vfe_state {
1385    struct {
1386	unsigned int per_thread_scratch_space:4;
1387	unsigned int pad3:3;
1388	unsigned int extend_vfe_state_present:1;
1389	unsigned int pad2:2;
1390	unsigned int scratch_base:22;
1391    } vfe0;
1392
1393    struct {
1394	unsigned int debug_counter_control:2;
1395	unsigned int children_present:1;
1396	unsigned int vfe_mode:4;
1397	unsigned int pad2:2;
1398	unsigned int num_urb_entries:7;
1399	unsigned int urb_entry_alloc_size:9;
1400	unsigned int max_threads:7;
1401    } vfe1;
1402
1403    struct {
1404	unsigned int pad4:4;
1405	unsigned int interface_descriptor_base:28;
1406    } vfe2;
1407};
1408
1409struct brw_vld_state {
1410    struct {
1411	unsigned int pad6:6;
1412	unsigned int scan_order:1;
1413	unsigned int intra_vlc_format:1;
1414	unsigned int quantizer_scale_type:1;
1415	unsigned int concealment_motion_vector:1;
1416	unsigned int frame_predict_frame_dct:1;
1417	unsigned int top_field_first:1;
1418	unsigned int picture_structure:2;
1419	unsigned int intra_dc_precision:2;
1420	unsigned int f_code_0_0:4;
1421	unsigned int f_code_0_1:4;
1422	unsigned int f_code_1_0:4;
1423	unsigned int f_code_1_1:4;
1424    } vld0;
1425
1426    struct {
1427	unsigned int pad2:9;
1428	unsigned int picture_coding_type:2;
1429	unsigned int pad:21;
1430    } vld1;
1431
1432    struct {
1433	unsigned int index_0:4;
1434	unsigned int index_1:4;
1435	unsigned int index_2:4;
1436	unsigned int index_3:4;
1437	unsigned int index_4:4;
1438	unsigned int index_5:4;
1439	unsigned int index_6:4;
1440	unsigned int index_7:4;
1441    } desc_remap_table0;
1442
1443    struct {
1444	unsigned int index_8:4;
1445	unsigned int index_9:4;
1446	unsigned int index_10:4;
1447	unsigned int index_11:4;
1448	unsigned int index_12:4;
1449	unsigned int index_13:4;
1450	unsigned int index_14:4;
1451	unsigned int index_15:4;
1452    } desc_remap_table1;
1453};
1454
1455struct brw_interface_descriptor {
1456    struct {
1457	unsigned int grf_reg_blocks:4;
1458	unsigned int pad:2;
1459	unsigned int kernel_start_pointer:26;
1460    } desc0;
1461
1462    struct {
1463	unsigned int pad:7;
1464	unsigned int software_exception:1;
1465	unsigned int pad2:3;
1466	unsigned int maskstack_exception:1;
1467	unsigned int pad3:1;
1468	unsigned int illegal_opcode_exception:1;
1469	unsigned int pad4:2;
1470	unsigned int floating_point_mode:1;
1471	unsigned int thread_priority:1;
1472	unsigned int single_program_flow:1;
1473	unsigned int pad5:1;
1474	unsigned int const_urb_entry_read_offset:6;
1475	unsigned int const_urb_entry_read_len:6;
1476    } desc1;
1477
1478    struct {
1479	unsigned int pad:2;
1480	unsigned int sampler_count:3;
1481	unsigned int sampler_state_pointer:27;
1482    } desc2;
1483
1484    struct {
1485	unsigned int binding_table_entry_count:5;
1486	unsigned int binding_table_pointer:27;
1487    } desc3;
1488};
1489
1490#endif
1491