1/* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28#ifndef CH7017_REG_H 29#define CH7017_REG_H 30 31#define CH7017_TV_DISPLAY_MODE 0x00 32#define CH7017_FLICKER_FILTER 0x01 33#define CH7017_VIDEO_BANDWIDTH 0x02 34#define CH7017_TEXT_ENHANCEMENT 0x03 35#define CH7017_START_ACTIVE_VIDEO 0x04 36#define CH7017_HORIZONTAL_POSITION 0x05 37#define CH7017_VERTICAL_POSITION 0x06 38#define CH7017_BLACK_LEVEL 0x07 39#define CH7017_CONTRAST_ENHANCEMENT 0x08 40#define CH7017_TV_PLL 0x09 41#define CH7017_TV_PLL_M 0x0a 42#define CH7017_TV_PLL_N 0x0b 43#define CH7017_SUB_CARRIER_0 0x0c 44#define CH7017_CIV_CONTROL 0x10 45#define CH7017_CIV_0 0x11 46#define CH7017_CHROMA_BOOST 0x14 47#define CH7017_CLOCK_MODE 0x1c 48#define CH7017_INPUT_CLOCK 0x1d 49#define CH7017_GPIO_CONTROL 0x1e 50#define CH7017_INPUT_DATA_FORMAT 0x1f 51#define CH7017_CONNECTION_DETECT 0x20 52#define CH7017_DAC_CONTROL 0x21 53#define CH7017_BUFFERED_CLOCK_OUTPUT 0x22 54#define CH7017_DEFEAT_VSYNC 0x47 55#define CH7017_TEST_PATTERN 0x48 56 57#define CH7017_POWER_MANAGEMENT 0x49 58/** Enables the TV output path. */ 59#define CH7017_TV_EN (1 << 0) 60#define CH7017_DAC0_POWER_DOWN (1 << 1) 61#define CH7017_DAC1_POWER_DOWN (1 << 2) 62#define CH7017_DAC2_POWER_DOWN (1 << 3) 63#define CH7017_DAC3_POWER_DOWN (1 << 4) 64/** Powers down the TV out block, and DAC0-3 */ 65#define CH7017_TV_POWER_DOWN_EN (1 << 5) 66 67#define CH7017_VERSION_ID 0x4a 68 69#define CH7017_DEVICE_ID 0x4b 70#define CH7017_DEVICE_ID_VALUE 0x1b 71#define CH7018_DEVICE_ID_VALUE 0x1a 72#define CH7019_DEVICE_ID_VALUE 0x19 73 74#define CH7017_XCLK_D2_ADJUST 0x53 75#define CH7017_UP_SCALER_COEFF_0 0x55 76#define CH7017_UP_SCALER_COEFF_1 0x56 77#define CH7017_UP_SCALER_COEFF_2 0x57 78#define CH7017_UP_SCALER_COEFF_3 0x58 79#define CH7017_UP_SCALER_COEFF_4 0x59 80#define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a 81#define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b 82#define CH7017_GPIO_INVERT 0x5c 83#define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d 84#define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e 85 86#define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f 87/**< Low bits of horizontal active pixel input */ 88 89#define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60 90/** High bits of horizontal active pixel input */ 91#define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0) 92/** High bits of vertical active line output */ 93#define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3) 94 95#define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61 96/**< Low bits of vertical active line output */ 97 98#define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62 99/**< Low bits of horizontal active pixel output */ 100 101#define CH7017_LVDS_POWER_DOWN 0x63 102/** High bits of horizontal active pixel output */ 103#define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0) 104/** Enables the LVDS power down state transition */ 105#define CH7017_LVDS_POWER_DOWN_EN (1 << 6) 106/** Enables the LVDS upscaler */ 107#define CH7017_LVDS_UPSCALER_EN (1 << 7) 108#define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08 109 110#define CH7017_LVDS_ENCODING 0x64 111#define CH7017_LVDS_DITHER_2D (1 << 2) 112#define CH7017_LVDS_DITHER_DIS (1 << 3) 113#define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4) 114#define CH7017_LVDS_24_BIT (1 << 5) 115 116#define CH7017_LVDS_ENCODING_2 0x65 117 118#define CH7017_LVDS_PLL_CONTROL 0x66 119/** Enables the LVDS panel output path */ 120#define CH7017_LVDS_PANEN (1 << 0) 121/** Enables the LVDS panel backlight */ 122#define CH7017_LVDS_BKLEN (1 << 3) 123 124#define CH7017_POWER_SEQUENCING_T1 0x67 125#define CH7017_POWER_SEQUENCING_T2 0x68 126#define CH7017_POWER_SEQUENCING_T3 0x69 127#define CH7017_POWER_SEQUENCING_T4 0x6a 128#define CH7017_POWER_SEQUENCING_T5 0x6b 129#define CH7017_GPIO_DRIVER_TYPE 0x6c 130#define CH7017_GPIO_DATA 0x6d 131#define CH7017_GPIO_DIRECTION_CONTROL 0x6e 132 133#define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71 134# define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4 135# define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0 136# define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80 137 138#define CH7017_LVDS_PLL_VCO_CONTROL 0x72 139# define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80 140# define CH7017_LVDS_PLL_VCO_SHIFT 4 141# define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0 142 143#define CH7017_OUTPUTS_ENABLE 0x73 144# define CH7017_CHARGE_PUMP_LOW 0x0 145# define CH7017_CHARGE_PUMP_HIGH 0x3 146# define CH7017_LVDS_CHANNEL_A (1 << 3) 147# define CH7017_LVDS_CHANNEL_B (1 << 4) 148# define CH7017_TV_DAC_A (1 << 5) 149# define CH7017_TV_DAC_B (1 << 6) 150# define CH7017_DDC_SELECT_DC2 (1 << 7) 151 152#define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74 153#define CH7017_LVDS_PLL_EMI_REDUCTION 0x75 154#define CH7017_LVDS_POWER_DOWN_FLICKER 0x76 155 156#define CH7017_LVDS_CONTROL_2 0x78 157# define CH7017_LOOP_FILTER_SHIFT 5 158# define CH7017_PHASE_DETECTOR_SHIFT 0 159 160#define CH7017_BANG_LIMIT_CONTROL 0x7f 161 162#endif /* CH7017_REG_H */ 163