1/* 2 * Copyright � 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28#ifndef _I830_BIOS_H_ 29#define _I830_BIOS_H_ 30 31#include <stdint.h> 32#ifndef REG_DUMPER 33#include <xf86str.h> 34#endif 35 36struct vbt_header { 37 char signature[20]; /**< Always starts with 'VBT$' */ 38 uint16_t version; /**< decimal */ 39 uint16_t header_size; /**< in bytes */ 40 uint16_t vbt_size; /**< in bytes */ 41 uint8_t vbt_checksum; 42 uint8_t reserved0; 43 uint32_t bdb_offset; /**< from beginning of VBT */ 44 uint32_t aim_offset[4]; /**< from beginning of VBT */ 45} __attribute__((packed)); 46 47struct bdb_header { 48 char signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ 49 uint16_t version; /**< decimal */ 50 uint16_t header_size; /**< in bytes */ 51 uint16_t bdb_size; /**< in bytes */ 52} __attribute__((packed)); 53 54/* 55 * There are several types of BIOS data blocks (BDBs), each block has 56 * an ID and size in the first 3 bytes (ID in first, size in next 2). 57 * Known types are listed below. 58 */ 59#define BDB_GENERAL_FEATURES 1 60#define BDB_GENERAL_DEFINITIONS 2 61#define BDB_OLD_TOGGLE_LIST 3 62#define BDB_MODE_SUPPORT_LIST 4 63#define BDB_GENERIC_MODE_TABLE 5 64#define BDB_EXT_MMIO_REGS 6 65#define BDB_SWF_IO 7 66#define BDB_SWF_MMIO 8 67#define BDB_DOT_CLOCK_TABLE 9 68#define BDB_MODE_REMOVAL_TABLE 10 69#define BDB_CHILD_DEVICE_TABLE 11 70#define BDB_DRIVER_FEATURES 12 71#define BDB_DRIVER_PERSISTENCE 13 72#define BDB_EXT_TABLE_PTRS 14 73#define BDB_DOT_CLOCK_OVERRIDE 15 74#define BDB_DISPLAY_SELECT 16 75/* 17 rsvd */ 76#define BDB_DRIVER_ROTATION 18 77#define BDB_DISPLAY_REMOVE 19 78#define BDB_OEM_CUSTOM 20 79#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 80#define BDB_SDVO_LVDS_OPTIONS 22 81#define BDB_SDVO_PANEL_DTDS 23 82#define BDB_SDVO_LVDS_PNP_IDS 24 83#define BDB_SDVO_LVDS_POWER_SEQ 25 84#define BDB_TV_OPTIONS 26 85#define BDB_LVDS_OPTIONS 40 86#define BDB_LVDS_LFP_DATA_PTRS 41 87#define BDB_LVDS_LFP_DATA 42 88#define BDB_LVDS_BACKLIGHT 43 89#define BDB_LVDS_POWER 44 90#define BDB_SKIP 254 /* VBIOS private block, ignore */ 91 92struct bdb_general_features { 93 /* bits 1 */ 94 unsigned char panel_fitting:2; 95 unsigned char flexaim:1; 96 unsigned char msg_enable:1; 97 unsigned char clear_screen:3; 98 unsigned char color_flip:1; 99 100 /* bits 2 */ 101 unsigned char download_ext_vbt:1; 102 unsigned char enable_ssc:1; 103 unsigned char ssc_freq:1; 104 unsigned char enable_lfp_on_override:1; 105 unsigned char disable_ssc_ddt:1; 106 unsigned char rsvd8:3; /* finish byte */ 107 108 /* bits 3 */ 109 unsigned char disable_smooth_vision:1; 110 unsigned char single_dvi:1; 111 unsigned char rsvd9:6; /* finish byte */ 112 113 /* bits 4 */ 114 unsigned char legacy_monitor_detect; 115 116 /* bits 5 */ 117 unsigned char int_crt_support:1; 118 unsigned char int_tv_support:1; 119 unsigned char rsvd11:6; /* finish byte */ 120} __attribute__((packed)); 121 122#define GPIO_PIN_NONE 0x00 /* "N/A" */ 123#define GPIO_PIN_I2C 0x01 /* "I2C GPIO pins" */ 124#define GPIO_PIN_CRT_DDC 0x02 /* "Analog CRT DDC GPIO pins" */ 125/* 915+ */ 126#define GPIO_PIN_LVDS 0x03 /* "Integrated LVDS DDC GPIO pins" */ 127#define GPIO_PIN_SDVO_I2C 0x05 /* "sDVO I2C GPIO pins" */ 128#define GPIO_PIN_SDVO_DDC1 0x1D /* "SDVO DDC1 GPIO pins" */ 129#define GPIO_PIN_SDVO_DDC2 0x2D /* "SDVO DDC2 GPIO pins" */ 130/* pre-915 */ 131#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 132#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 133#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 134#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 135 136/* Pre 915 */ 137#define DEVICE_TYPE_NONE 0x00 138#define DEVICE_TYPE_CRT 0x01 139#define DEVICE_TYPE_TV 0x09 140#define DEVICE_TYPE_EFP 0x12 141#define DEVICE_TYPE_LFP 0x22 142/* On 915+ */ 143#define DEVICE_TYPE_CRT_DPMS 0x6001 144#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 145#define DEVICE_TYPE_TV_COMPOSITE 0x0209 146#define DEVICE_TYPE_TV_MACROVISION 0x0289 147#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 148#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 149#define DEVICE_TYPE_TV_SCART 0x0209 150#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 151#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 152#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 153#define DEVICE_TYPE_EFP_DVI_I 0x6053 154#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 155#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 156#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 157#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 158#define DEVICE_TYPE_LFP_PANELLINK 0x5012 159#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 160#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 161#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 162#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 163 164#define DEVICE_CFG_NONE 0x00 165#define DEVICE_CFG_12BIT_DVOB 0x01 166#define DEVICE_CFG_12BIT_DVOC 0x02 167#define DEVICE_CFG_24BIT_DVOBC 0x09 168#define DEVICE_CFG_24BIT_DVOCB 0x0a 169#define DEVICE_CFG_DUAL_DVOB 0x11 170#define DEVICE_CFG_DUAL_DVOC 0x12 171#define DEVICE_CFG_DUAL_DVOBC 0x13 172#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 173#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 174 175#define DEVICE_WIRE_NONE 0x00 176#define DEVICE_WIRE_DVOB 0x01 177#define DEVICE_WIRE_DVOC 0x02 178#define DEVICE_WIRE_DVOBC 0x03 179#define DEVICE_WIRE_DVOBB 0x05 180#define DEVICE_WIRE_DVOCC 0x06 181#define DEVICE_WIRE_DVOB_MASTER 0x0d 182#define DEVICE_WIRE_DVOC_MASTER 0x0e 183 184#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 185#define DEVICE_PORT_DVOB 0x01 186#define DEVICE_PORT_DVOC 0x02 187 188struct child_device_config { 189 uint16_t handle; 190 uint16_t device_type; /* See DEVICE_TYPE_* above */ 191 uint8_t device_id[10]; 192 uint16_t addin_offset; 193 uint8_t dvo_port; /* See DEVICE_PORT_* above */ 194 uint8_t i2c_pin; 195 uint8_t slave_addr; 196 uint8_t ddc_pin; 197 uint16_t edid_ptr; 198 uint8_t dvo_cfg; /* See DEVICE_CFG_* above */ 199 uint8_t dvo2_port; 200 uint8_t i2c2_pin; 201 uint8_t slave2_addr; 202 uint8_t ddc2_pin; 203 uint8_t capabilities; 204 uint8_t dvo_wiring; /* See DEVICE_WIRE_* above */ 205 uint8_t dvo2_wiring; 206 uint16_t extended_type; 207 uint8_t dvo_function; 208} __attribute__((packed)); 209 210struct bdb_general_definitions { 211 unsigned char crt_ddc_gmbus_pin; /* see GPIO_PIN_* above */ 212 213 /* DPMS bits */ 214 unsigned char dpms_acpi:1; 215 unsigned char skip_boot_crt_detect:1; 216 unsigned char dpms_aim:1; 217 unsigned char rsvd1:5; /* finish byte */ 218 219 /* boot device bits */ 220 unsigned char boot_display[2]; 221 unsigned char child_dev_size; 222 223 /* 224 * Device info: 225 * If TV is present, it'll be at devices[0] 226 * LVDS will be next, either devices[0] or [1], if present 227 * Max total will be 6, but could be as few as 4 if both 228 * TV and LVDS are missing, so be careful when interpreting 229 * [4] and [5]. 230 */ 231 struct child_device_config devices[0]; 232 /* may be another device block here on some platforms */ 233} __attribute__((packed)); 234 235#define DEVICE_CHILD_SIZE 7 236 237struct bdb_child_devices { 238 uint8_t child_structure_size; 239 struct child_device_config children[DEVICE_CHILD_SIZE]; 240} __attribute__((packed)); 241 242struct bdb_lvds_options { 243 uint8_t panel_type; 244 uint8_t rsvd1; 245 /* LVDS capabilities, stored in a dword */ 246 uint8_t pfit_mode:2; 247 uint8_t pfit_text_mode_enhanced:1; 248 uint8_t pfit_gfx_mode_enhanced:1; 249 uint8_t pfit_ratio_auto:1; 250 uint8_t pixel_dither:1; 251 uint8_t lvds_edid:1; 252 uint8_t rsvd2:1; 253 uint8_t rsvd4; 254} __attribute__((packed)); 255 256/* 915+ only */ 257struct bdb_tv_features { 258 /* need to verify bit ordering */ 259 uint16_t under_over_scan_via_yprpb:2; 260 uint16_t rsvd1:10; 261 uint16_t under_over_scan_via_dvi:2; 262 uint16_t add_overscan_mode:1; 263 uint16_t rsvd2:1; 264} __attribute__((packed)); 265 266struct lvds_fp_timing { 267 uint16_t x_res; 268 uint16_t y_res; 269 uint32_t lvds_reg; 270 uint32_t lvds_reg_val; 271 uint32_t pp_on_reg; 272 uint32_t pp_on_reg_val; 273 uint32_t pp_off_reg; 274 uint32_t pp_off_reg_val; 275 uint32_t pp_cycle_reg; 276 uint32_t pp_cycle_reg_val; 277 uint32_t pfit_reg; 278 uint32_t pfit_reg_val; 279 uint16_t terminator; 280} __attribute__((packed)); 281 282struct lvds_dvo_timing { 283 uint16_t dclk; /**< In 10khz */ 284 uint8_t hactive; 285 uint8_t hblank; 286 uint8_t high_h; /**< 7:4 = hactive 11:8, 3:0 = hblank 11:8 */ 287 uint8_t vactive; 288 uint8_t vblank; 289 uint8_t high_v; /**< 7:4 = vactive 11:8, 3:0 = vblank 11:8 */ 290 uint8_t hsync_off; 291 uint8_t hsync_pulse_width; 292 uint8_t vsync_off; 293 uint8_t high_hsync_off; /**< 7:6 = hsync off 9:8 */ 294 uint8_t h_image; 295 uint8_t v_image; 296 uint8_t max_hv; 297 uint8_t h_border; 298 uint8_t v_border; 299 uint8_t flags; 300} __attribute__((packed)); 301 302struct lvds_pnp_id { 303 uint16_t mfg_name; 304 uint16_t product_code; 305 uint32_t serial; 306 uint8_t mfg_week; 307 uint8_t mfg_year; 308} __attribute__((packed));; 309 310/* LFP pointer table contains entries to the struct below */ 311struct bdb_lvds_lfp_data_ptr { 312 uint16_t fp_timing_offset; /* offsets are from start of bdb */ 313 uint8_t fp_table_size; 314 uint16_t dvo_timing_offset; 315 uint8_t dvo_table_size; 316 uint16_t panel_pnp_id_offset; 317 uint8_t pnp_table_size; 318} __attribute__((packed)); 319 320struct bdb_lvds_lfp_data_ptrs { 321 uint8_t lvds_entries; 322 struct bdb_lvds_lfp_data_ptr ptr[16]; 323} __attribute__((packed)); 324 325struct bdb_lvds_lfp_data_entry { 326 struct lvds_fp_timing fp_timing; 327 struct lvds_dvo_timing dvo_timing; 328 struct lvds_pnp_id pnp_id; 329} __attribute__((packed)); 330 331struct bdb_lvds_lfp_data { 332 struct bdb_lvds_lfp_data_entry data[16]; 333} __attribute__((packed)); 334 335#define BACKLIGHT_TYPE_NONE 0 336#define BACKLIGHT_TYPE_I2C 1 337#define BACKLIGHT_TYPE_PWM 2 338 339#define BACKLIGHT_GMBUS_100KHZ 0 340#define BACKLIGHT_GMBUS_50KHZ 1 341#define BACKLIGHT_GMBUS_400KHZ 2 342#define BACKLIGHT_GMBUS_1MHZ 3 343 344struct backlight_info { 345 uint8_t inverter_type:2; /* see BACKLIGHT_TYPE_* above */ 346 uint8_t inverter_polarity:1; /* 1 means 0 is max, 255 is min */ 347 uint8_t gpio_pins:3; /* see GPIO_PIN_* above */ 348 uint8_t gmbus_speed:2; 349 uint16_t pwm_frequency; /* in Hz */ 350 uint8_t min_brightness; 351 /* Next two are only for 915+ systems */ 352 uint8_t i2c_addr; 353 uint8_t i2c_cmd; 354} __attribute((packed)); 355 356struct bdb_backlight_control { 357 uint8_t row_size; 358 struct backlight_info lfps[16]; 359} __attribute__((packed)); 360 361struct bdb_bia { 362 uint8_t bia_enable:1; 363 uint8_t bia_level:3; 364 uint8_t rsvd1:3; 365 uint8_t als_enable:1; 366 uint8_t als_response_data[20]; 367} __attribute((packed)); 368 369struct aimdb_header { 370 char signature[16]; 371 char oem_device[20]; 372 uint16_t aimdb_version; 373 uint16_t aimdb_header_size; 374 uint16_t aimdb_size; 375} __attribute__((packed)); 376 377struct aimdb_block { 378 uint8_t aimdb_id; 379 uint16_t aimdb_size; 380} __attribute__((packed)); 381 382struct vch_panel_data { 383 uint16_t fp_timing_offset; 384 uint8_t fp_timing_size; 385 uint16_t dvo_timing_offset; 386 uint8_t dvo_timing_size; 387 uint16_t text_fitting_offset; 388 uint8_t text_fitting_size; 389 uint16_t graphics_fitting_offset; 390 uint8_t graphics_fitting_size; 391} __attribute__((packed)); 392 393struct vch_bdb_22 { 394 struct aimdb_block aimdb_block; 395 struct vch_panel_data panels[16]; 396} __attribute__((packed)); 397 398#define BLC_INVERTER_TYPE_NONE 0 399#define BLC_INVERTER_TYPE_I2C 1 400#define BLC_INVERTER_TYPE_PWM 2 401 402#define BLC_GPIO_NONE 0 403#define BLC_GPIO_I2C 1 404#define BLC_GPIO_CRT_DDC 2 405#define BLC_GPIO_DVI_DDC 3 406#define BLC_GPIO_SDVO_I2C 5 407 408struct blc_struct { 409 uint8_t inverter_type:2; 410 uint8_t inverter_polarity:1; /* 1 means inverted (0 = max brightness) */ 411 uint8_t gpio_pins:3; 412 uint8_t gmbus_speed:2; 413 uint16_t pwm_freq; /* in Hz */ 414 uint8_t min_brightness; /* (0-255) */ 415 uint8_t i2c_slave_addr; 416 uint8_t i2c_cmd; 417} __attribute__((packed)); 418 419struct bdb_lvds_backlight { 420 uint8_t blcstruct_size; 421 struct blc_struct panels[16]; 422} __attribute__((packed)); 423 424struct bdb_lvds_power { 425 uint8_t dpst_enabled:1; 426 uint8_t pwr_prefs:3; 427 uint8_t rsvd1:3; 428 uint8_t als_enabled:1; 429 uint16_t als_backlight1; 430 uint16_t als_backlight2; 431 uint16_t als_backlight3; 432 uint16_t als_backlight4; 433 uint16_t als_backlight5; 434} __attribute__((packed)); 435 436#define BDB_DRIVER_NO_LVDS 0 437#define BDB_DRIVER_INT_LVDS 1 438#define BDB_DRIVER_SDVO_LVDS 2 439#define BDB_DRIVER_EDP 3 440 441struct bdb_driver_feature { 442 uint8_t boot_dev_algorithm:1; 443 uint8_t block_display_switch:1; 444 uint8_t allow_display_switch:1; 445 uint8_t hotplug_dvo:1; 446 uint8_t dual_view_zoom:1; 447 uint8_t int15h_hook:1; 448 uint8_t sprite_in_clone:1; 449 uint8_t primary_lfp_id:1; 450 451 uint16_t boot_mode_x; 452 uint16_t boot_mode_y; 453 uint8_t boot_mode_bpp; 454 uint8_t boot_mode_refresh; 455 456 uint16_t enable_lfp_primary:1; 457 uint16_t selective_mode_pruning:1; 458 uint16_t dual_frequency:1; 459 uint16_t render_clock_freq:1; /* 0: high freq; 1: low freq */ 460 uint16_t nt_clone_support:1; 461 uint16_t power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 462 uint16_t sprite_display_assign:1; /* 0: secondary; 1: primary */ 463 uint16_t cui_aspect_scaling:1; 464 uint16_t preserve_aspect_ratio:1; 465 uint16_t sdvo_device_power_down:1; 466 uint16_t crt_hotplug:1; 467 uint16_t lvds_config:2; 468 uint16_t reserved:3; 469 470 uint8_t static_display:1; 471 uint8_t reserved2:7; 472 uint16_t legacy_crt_max_x; 473 uint16_t legacy_crt_max_y; 474 uint8_t legacy_crt_max_refresh; 475} __attribute__((packed)); 476 477struct bdb_sdvo_lvds_options { 478 uint8_t panel_backlight; 479 uint8_t h40_set_panel_type; 480 uint8_t panel_type; 481 uint8_t ssc_clk_freq; 482 uint16_t als_low_trip; 483 uint16_t als_high_trip; 484 uint8_t sclalarcoeff_tab_row_num; 485 uint8_t sclalarcoeff_tab_row_size; 486 uint8_t coefficient[8]; 487 uint8_t panel_misc_bits_1; 488 uint8_t panel_misc_bits_2; 489 uint8_t panel_misc_bits_3; 490 uint8_t panel_misc_bits_4; 491} __attribute__((packed)); 492 493 494#ifndef REG_DUMPER 495int i830_bios_init(ScrnInfoPtr pScrn); 496#endif 497 498/* 499 * Driver<->VBIOS interaction occurs through scratch bits in 500 * GR18 & SWF*. 501 * 502 * The VBIOS/firmware will signal to the gfx driver through the ASLE interrupt 503 * (visible in the interupt regs at bit 0) when it wants something done. 504 * 505 * Pre-965: 506 * The gfx driver can make calls to the VBIOS/firmware through an SMI request, 507 * generated by writing to offset 0xe0 of the device's config space (see the 508 * publically available 915 PRM for details). 509 * 510 * 965 and above: 511 * IGD OpRegion requests to the VBIOS/firmware are made using SWSCI, which can 512 * be triggered by writing to offset 0xe4 (see the publically available 513 * 965 graphics PRM for details). 514 */ 515 516/* GR18 bits are set on display switch and hotkey events */ 517#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 518#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 519#define GR18_HK_NONE (0x0<<3) 520#define GR18_HK_LFP_STRETCH (0x1<<3) 521#define GR18_HK_TOGGLE_DISP (0x2<<3) 522#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 523#define GR18_HK_POPUP_DISABLED (0x6<<3) 524#define GR18_HK_POPUP_ENABLED (0x7<<3) 525#define GR18_HK_PFIT (0x8<<3) 526#define GR18_HK_APM_CHANGE (0xa<<3) 527#define GR18_HK_MULTIPLE (0xc<<3) 528#define GR18_USER_INT_EN (1<<2) 529#define GR18_A0000_FLUSH_EN (1<<1) 530#define GR18_SMM_EN (1<<0) 531 532/* Set by driver, cleared by VBIOS */ 533#define SWF00_YRES_SHIFT 16 534#define SWF00_XRES_SHIFT 0 535#define SWF00_RES_MASK 0xffff 536 537/* Set by VBIOS at boot time and driver at runtime */ 538#define SWF01_TV2_FORMAT_SHIFT 8 539#define SWF01_TV1_FORMAT_SHIFT 0 540#define SWF01_TV_FORMAT_MASK 0xffff 541 542#define SWF10_VBIOS_BLC_I2C_EN (1<<29) 543#define SWF10_GTT_OVERRIDE_EN (1<<28) 544#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 545#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 546#define SWF10_OLD_TOGGLE 0x0 547#define SWF10_TOGGLE_LIST_1 0x1 548#define SWF10_TOGGLE_LIST_2 0x2 549#define SWF10_TOGGLE_LIST_3 0x3 550#define SWF10_TOGGLE_LIST_4 0x4 551#define SWF10_PANNING_EN (1<<23) 552#define SWF10_DRIVER_LOADED (1<<22) 553#define SWF10_EXTENDED_DESKTOP (1<<21) 554#define SWF10_EXCLUSIVE_MODE (1<<20) 555#define SWF10_OVERLAY_EN (1<<19) 556#define SWF10_PLANEB_HOLDOFF (1<<18) 557#define SWF10_PLANEA_HOLDOFF (1<<17) 558#define SWF10_VGA_HOLDOFF (1<<16) 559#define SWF10_ACTIVE_DISP_MASK 0xffff 560#define SWF10_PIPEB_LFP2 (1<<15) 561#define SWF10_PIPEB_EFP2 (1<<14) 562#define SWF10_PIPEB_TV2 (1<<13) 563#define SWF10_PIPEB_CRT2 (1<<12) 564#define SWF10_PIPEB_LFP (1<<11) 565#define SWF10_PIPEB_EFP (1<<10) 566#define SWF10_PIPEB_TV (1<<9) 567#define SWF10_PIPEB_CRT (1<<8) 568#define SWF10_PIPEA_LFP2 (1<<7) 569#define SWF10_PIPEA_EFP2 (1<<6) 570#define SWF10_PIPEA_TV2 (1<<5) 571#define SWF10_PIPEA_CRT2 (1<<4) 572#define SWF10_PIPEA_LFP (1<<3) 573#define SWF10_PIPEA_EFP (1<<2) 574#define SWF10_PIPEA_TV (1<<1) 575#define SWF10_PIPEA_CRT (1<<0) 576 577#define SWF11_MEMORY_SIZE_SHIFT 16 578#define SWF11_SV_TEST_EN (1<<15) 579#define SWF11_IS_AGP (1<<14) 580#define SWF11_DISPLAY_HOLDOFF (1<<13) 581#define SWF11_DPMS_REDUCED (1<<12) 582#define SWF11_IS_VBE_MODE (1<<11) 583#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 584#define SWF11_DPMS_MASK 0x07 585#define SWF11_DPMS_OFF (1<<2) 586#define SWF11_DPMS_SUSPEND (1<<1) 587#define SWF11_DPMS_STANDBY (1<<0) 588#define SWF11_DPMS_ON 0 589 590#define SWF14_GFX_PFIT_EN (1<<31) 591#define SWF14_TEXT_PFIT_EN (1<<30) 592#define SWF14_LID_SWITCH_EN (1<<29) 593#define SWF14_POPUP_EN (1<<28) 594#define SWF14_DISPLAY_HOLDOFF (1<<27) 595#define SWF14_DISP_DETECT_EN (1<<26) 596#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 597#define SWF14_DRIVER_STATUS (1<<24) 598#define SWF14_OS_TYPE_WIN9X (1<<23) 599#define SWF14_OS_TYPE_WINNT (1<<22) 600/* 21:19 rsvd */ 601#define SWF14_PM_TYPE_MASK 0x00070000 602#define SWF14_PM_ACPI_VIDEO (0x4 << 16) 603#define SWF14_PM_ACPI (0x3 << 16) 604#define SWF14_PM_APM_12 (0x2 << 16) 605#define SWF14_PM_APM_11 (0x1 << 16) 606#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 607 /* if GR18 indicates a display switch */ 608#define SWF14_DS_PIPEB_LFP2_EN (1<<15) 609#define SWF14_DS_PIPEB_EFP2_EN (1<<14) 610#define SWF14_DS_PIPEB_TV2_EN (1<<13) 611#define SWF14_DS_PIPEB_CRT2_EN (1<<12) 612#define SWF14_DS_PIPEB_LFP_EN (1<<11) 613#define SWF14_DS_PIPEB_EFP_EN (1<<10) 614#define SWF14_DS_PIPEB_TV_EN (1<<9) 615#define SWF14_DS_PIPEB_CRT_EN (1<<8) 616#define SWF14_DS_PIPEA_LFP2_EN (1<<7) 617#define SWF14_DS_PIPEA_EFP2_EN (1<<6) 618#define SWF14_DS_PIPEA_TV2_EN (1<<5) 619#define SWF14_DS_PIPEA_CRT2_EN (1<<4) 620#define SWF14_DS_PIPEA_LFP_EN (1<<3) 621#define SWF14_DS_PIPEA_EFP_EN (1<<2) 622#define SWF14_DS_PIPEA_TV_EN (1<<1) 623#define SWF14_DS_PIPEA_CRT_EN (1<<0) 624 /* if GR18 indicates a panel fitting request */ 625#define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 626 /* if GR18 indicates an APM change request */ 627#define SWF14_APM_HIBERNATE 0x4 628#define SWF14_APM_SUSPEND 0x3 629#define SWF14_APM_STANDBY 0x1 630#define SWF14_APM_RESTORE 0x0 631 632#endif /* _I830_BIOS_H_ */ 633