1/**************************************************************************
2
3Copyright 2001 VA Linux Systems Inc., Fremont, California.
4Copyright 2002 Tungsten Graphics Inc., Cedar Park, Texas.
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining a
9copy of this software and associated documentation files (the "Software"),
10to deal in the Software without restriction, including without limitation
11on the rights to use, copy, modify, merge, publish, distribute, sub
12license, and/or sell copies of the Software, and to permit persons to whom
13the Software is furnished to do so, subject to the following conditions:
14
15The above copyright notice and this permission notice (including the next
16paragraph) shall be included in all copies or substantial portions of the
17Software.
18
19THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
22ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
23DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
24OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
25USE OR OTHER DEALINGS IN THE SOFTWARE.
26
27**************************************************************************/
28
29
30#ifndef _I830_COMMON_H_
31#define _I830_COMMON_H_
32
33#include <stdint.h>
34
35#define I830_NR_TEX_REGIONS 255	/* maximum due to use of chars for next/prev */
36#define I830_LOG_MIN_TEX_REGION_SIZE 14
37
38
39/* Driver specific DRM command indices
40 * NOTE: these are not OS specific, but they are driver specific
41 */
42#define DRM_I830_INIT                     0x00
43#define DRM_I830_FLUSH                    0x01
44#define DRM_I830_FLIP                     0x02
45#define DRM_I830_BATCHBUFFER              0x03
46#define DRM_I830_IRQ_EMIT                 0x04
47#define DRM_I830_IRQ_WAIT                 0x05
48#define DRM_I830_GETPARAM                 0x06
49#define DRM_I830_SETPARAM                 0x07
50#define DRM_I830_ALLOC                    0x08
51#define DRM_I830_FREE                     0x09
52#define DRM_I830_INIT_HEAP                0x0a
53#define DRM_I830_CMDBUFFER                0x0b
54#define DRM_I830_DESTROY_HEAP             0x0c
55#define DRM_I830_SET_VBLANK_PIPE	  0x0d
56#define DRM_I830_GET_VBLANK_PIPE	  0x0e
57#define DRM_I830_HWS_PAGE_ADDR		  0x11
58
59
60typedef struct {
61   enum {
62      I830_INIT_DMA = 0x01,
63      I830_CLEANUP_DMA = 0x02,
64      I830_RESUME_DMA = 0x03
65   } func;
66   unsigned int mmio_offset;
67   int sarea_priv_offset;
68   unsigned int ring_start;
69   unsigned int ring_end;
70   unsigned int ring_size;
71   unsigned int front_offset;
72   unsigned int back_offset;
73   unsigned int depth_offset;
74   unsigned int w;
75   unsigned int h;
76   unsigned int pitch; /* Pitch of front buffer in units of pixels */
77   unsigned int pitch_bits;
78   unsigned int back_pitch;
79   unsigned int depth_pitch;
80   unsigned int cpp;
81   unsigned int chipset;
82} drmI830Init;
83
84typedef struct {
85	drmTextureRegion texList[I830_NR_TEX_REGIONS+1];
86        int last_upload;	/* last time texture was uploaded */
87        int last_enqueue;	/* last time a buffer was enqueued */
88	volatile int last_dispatch;	/* age of the most recently dispatched buffer */
89	int ctxOwner;		/* last context to upload state */
90	int texAge;
91        int pf_enabled;		/* is pageflipping allowed? */
92        int pf_active;
93        int pf_current_page;	/* which buffer is being displayed? */
94        int perf_boxes;	        /* performance boxes to be displayed */
95	int width, height;      /* screen size in pixels */
96
97	drm_handle_t front_handle;
98	int front_offset;
99	int front_size;
100
101	drm_handle_t back_handle;
102	int back_offset;
103	int back_size;
104
105	drm_handle_t depth_handle;
106	int depth_offset;
107	int depth_size;
108
109	drm_handle_t tex_handle;
110	int tex_offset;
111	int tex_size;
112	int log_tex_granularity;
113	int pitch;
114	int rotation;           /* 0, 90, 180 or 270 */
115	int rotated_offset;
116	int rotated_size;
117	int rotated_pitch;
118	int virtualX, virtualY;
119
120        unsigned int front_tiled;
121        unsigned int back_tiled;
122        unsigned int depth_tiled;
123        unsigned int rotated_tiled;
124        unsigned int rotated2_tiled;
125
126	int pipeA_x;
127	int pipeA_y;
128	int pipeA_w;
129	int pipeA_h;
130	int pipeB_x;
131	int pipeB_y;
132	int pipeB_w;
133	int pipeB_h;
134
135	/* Triple buffering */
136	drm_handle_t third_handle;
137	int third_offset;
138	int third_size;
139	unsigned int third_tiled;
140
141	/* buffer object handles for the static buffers.  May change
142	 * over the lifetime of the client, though it doesn't in our current
143	 * implementation.
144	 */
145	unsigned int front_bo_handle;
146	unsigned int back_bo_handle;
147	unsigned int third_bo_handle;
148	unsigned int depth_bo_handle;
149} drmI830Sarea;
150
151/* Flags for perf_boxes
152 */
153#define I830_BOX_RING_EMPTY    0x1 /* populated by kernel */
154#define I830_BOX_FLIP          0x2 /* populated by kernel */
155#define I830_BOX_WAIT          0x4 /* populated by kernel & client */
156#define I830_BOX_TEXTURE_LOAD  0x8 /* populated by kernel */
157#define I830_BOX_LOST_CONTEXT  0x10 /* populated by client */
158
159
160typedef struct {
161   	int start;		/* agp offset */
162	int used;		/* nr bytes in use */
163	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
164        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
165	int num_cliprects;	/* mulitpass with multiple cliprects? */
166        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
167} drmI830BatchBuffer;
168
169typedef struct {
170   	char *buf;		/* agp offset */
171	int sz; 		/* nr bytes in use */
172	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
173        int DR4;		/* window origin for GFX_OP_DRAWRECT_INFO*/
174	int num_cliprects;	/* mulitpass with multiple cliprects? */
175        drm_clip_rect_t *cliprects; /* pointer to userspace cliprects */
176} drmI830CmdBuffer;
177
178typedef struct {
179	int *irq_seq;
180} drmI830IrqEmit;
181
182typedef struct {
183	int irq_seq;
184} drmI830IrqWait;
185
186typedef struct {
187	int param;
188	int *value;
189} drmI830GetParam;
190
191#define I830_PARAM_IRQ_ACTIVE     1
192#define I830_PARAM_ALLOW_BATCHBUFFER   2
193
194typedef struct {
195	int param;
196	int value;
197} drmI830SetParam;
198
199#define I830_SETPARAM_USE_MI_BATCHBUFFER_START  1
200#define I830_SETPARAM_TEX_LRU_LOG_GRANULARITY   2
201#define I830_SETPARAM_ALLOW_BATCHBUFFER         3
202
203
204/* A memory manager for regions of shared memory:
205 */
206#define I830_MEM_REGION_AGP 1
207
208typedef struct {
209	int region;
210	int alignment;
211	int size;
212	int *region_offset;	/* offset from start of fb or agp */
213} drmI830MemAlloc;
214
215typedef struct {
216	int region;
217	int region_offset;
218} drmI830MemFree;
219
220typedef struct {
221	int region;
222	int size;
223	int start;
224} drmI830MemInitHeap;
225
226typedef struct {
227	int region;
228} drmI830MemDestroyHeap;
229
230#define	DRM_I830_VBLANK_PIPE_A	1
231#define	DRM_I830_VBLANK_PIPE_B	2
232
233typedef struct {
234	int pipe;
235} drmI830VBlankPipe;
236
237typedef struct {
238	uint64_t addr;
239} drmI830HWS;
240
241#endif /* _I830_DRM_H_ */
242