1/* -*- c-basic-offset: 4 -*- */ 2/* 3 * Copyright © 2006 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * 27 */ 28 29/** @file 30 * This file contains the register definitions for the i82807aa. 31 * 32 * Documentation on this chipset can be found in datasheet #29069001 at 33 * intel.com. 34 */ 35#ifndef I82807AA_REG_H 36#define I82807AA_REG_H 37 38/** @defgroup VR00 VCH Revision & GMBus Base Addr 39 * @{ 40 */ 41#define VR00 0x00 42# define VR00_BASE_ADDRESS_MASK 0x007f 43/** @} */ 44 45/** @defgroup VR01 VCH Functionality Enable 46 * @{ 47 */ 48#define VR01 0x01 49/** 50 * Enable the panel fitter 51 */ 52# define VR01_PANEL_FIT_ENABLE (1 << 3) 53/** 54 * Enables the LCD display. 55 * 56 * This must not be set while VR01_DVO_BYPASS_ENABLE is set. 57 */ 58# define VR01_LCD_ENABLE (1 << 2) 59/** Enables the DVO repeater. */ 60# define VR01_DVO_BYPASS_ENABLE (1 << 1) 61/** Enables the DVO clock */ 62# define VR01_DVO_ENABLE (1 << 0) 63/** @} */ 64 65/** @defgroup VR10 LCD Interface Format 66 * @{ 67 */ 68#define VR10 0x10 69/** Enables LVDS output instead of CMOS */ 70# define VR10_LVDS_ENABLE (1 << 4) 71/** Enables 18-bit LVDS output. */ 72# define VR10_INTERFACE_1X18 (0 << 2) 73/** Enables 24-bit LVDS or CMOS output */ 74# define VR10_INTERFACE_1X24 (1 << 2) 75/** Enables 2x18-bit LVDS or CMOS output. */ 76# define VR10_INTERFACE_2X18 (2 << 2) 77/** Enables 2x24-bit LVDS output */ 78# define VR10_INTERFACE_2X24 (3 << 2) 79/** @} */ 80 81/** @defgroup VR11 CMOS Output Control 82 * @{ 83 */ 84/** @} */ 85 86/** @defgroup VR12 LVDS Output Control 87 * @{ 88 */ 89/** @} */ 90 91/** @defgroup VR18 PLL clock select 92 * @{ 93 */ 94/** @} */ 95 96/** @defgroup VR19 PLL clock divisor M 97 * @{ 98 */ 99/** @} */ 100 101/** @defgroup VR1A PLL clock divisor N 102 * @{ 103 */ 104/** @} */ 105 106/** @defgroup VR1F FIFO Pre-load 107 * @{ 108 */ 109/** @} */ 110 111/** @defgroup VR20 LCD Horizontal Display Size 112 * @{ 113 */ 114#define VR20 0x20 115/** @} */ 116 117/** @defgroup VR21 LCD Vertical Display Size 118 * @{ 119 */ 120#define VR21 0x20 121/** @} */ 122 123/** @defgroup VR22 Horizontal TRP to DE Start Delay 124 * @{ 125 */ 126/** @} */ 127 128/** @defgroup VR23 Horizontal TRP to DE End Delay 129 * @{ 130 */ 131/** @} */ 132 133/** @defgroup VR24 Horizontal TRP To LP Start Delay 134 * @{ 135 */ 136/** @} */ 137 138/** @defgroup VR25 Horizontal TRP To LP End Delay 139 * @{ 140 */ 141/** @} */ 142 143/** @defgroup VR26 Vertical TRP To FLM Start Delay 144 * @{ 145 */ 146/** @} */ 147 148/** @defgroup VR27 Vertical TRP To FLM End Delay 149 * @{ 150 */ 151/** @} */ 152 153/** @defgroup VR30 Panel power down status 154 * @{ 155 */ 156#define VR30 0x30 157/** Read only bit indicating that the panel is not in a safe poweroff state. */ 158# define VR30_PANEL_ON (1 << 15) 159/** @} */ 160 161/** @defgroup VR31 Tpon Panel power on sequencing delay 162 * @{ 163 */ 164/** @} */ 165 166/** @defgroup VR32 Tpon Panel power off sequencing delay 167 * @{ 168 */ 169/** @} */ 170 171/** @defgroup VR33 Tstay Panel power off stay down delay 172 * @{ 173 */ 174/** @} */ 175 176/** @defgroup VR34 Maximal FLM Pulse Interval 177 * @{ 178 */ 179/** @} */ 180 181/** @defgroup VR35 Maximal LP Pulse Interval 182 * @{ 183 */ 184/** @} */ 185 186/** @defgroup VR40 187 * @{ 188 */ 189#define VR40 0x40 190# define VR40_STALL_ENABLE (1 << 13) 191# define VR40_VERTICAL_INTERP_ENABLE (1 << 12) 192# define VR40_ENHANCED_PANEL_FITTING (1 << 11) 193# define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) 194# define VR40_AUTO_RATIO_ENABLE (1 << 9) 195# define VR40_CLOCK_GATING_ENABLE (1 << 8) 196/** @} */ 197 198/** @defgroup VR41 Panel Fitting Vertical Ratio 199 * @{ 200 * 201 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 202 */ 203/** @} */ 204#define VR41 0x41 205 206/** @defgroup VR42 Panel Fitting Horizontal Ratio 207 * @{ 208 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 209 */ 210/** @} */ 211#define VR42 0x42 212 213/** @defgroup VR43 Horizontal Image Size 214 * @{ 215 */ 216/** @} */ 217#define VR43 0x43 218 219/** @defgroup VR44 Panel Fitting Coefficient 0 220 * @{ 221 */ 222/** @} */ 223 224/** @defgroup VR45 Panel Fitting Coefficient 1 225 * @{ 226 */ 227/** @} */ 228 229/** @defgroup VR46 Panel Fitting Coefficient 2 230 * @{ 231 */ 232/** @} */ 233 234/** @defgroup VR47 Panel Fitting Coefficient 3 235 * @{ 236 */ 237/** @} */ 238 239/** @defgroup VR48 Panel Fitting Coefficient 4 240 * @{ 241 */ 242/** @} */ 243 244/** @defgroup VR49 Panel Fitting Coefficient 5 245 * @{ 246 */ 247/** @} */ 248 249/** @defgroup VR80 GPIO 0 250 * @{ 251 */ 252/** @} */ 253 254#define VR80 0x80 255#define VR81 0x81 256#define VR82 0x82 257#define VR83 0x83 258#define VR84 0x84 259#define VR85 0x85 260#define VR86 0x86 261#define VR87 0x87 262 263/** @defgroup VR88 GPIO 8 264 * @{ 265 */ 266/** @} */ 267 268#define VR88 0x88 269 270/** @defgroup VR8E Graphics BIOS scratch 0 271 * @{ 272 */ 273#define VR8E 0x8E 274# define VR8E_PANEL_TYPE_MASK (0xf << 0) 275# define VR8E_PANEL_INTERFACE_CMOS (0 << 4) 276# define VR8E_PANEL_INTERFACE_LVDS (1 << 4) 277# define VR8E_FORCE_DEFAULT_PANEL (1 << 5) 278/** @} */ 279 280/** @defgroup VR8F Graphics BIOS scratch 1 281 * @{ 282 */ 283#define VR8F 0x8F 284# define VR8F_VCH_PRESENT (1 << 0) 285# define VR8F_DISPLAY_CONN (1 << 1) 286# define VR8F_POWER_MASK (0x3c) 287# define VR8F_POWER_POS (2) 288/** @} */ 289 290 291#endif /* I82807AA_REG_H */ 292