1fa225cbcSrjs/*
2fa225cbcSrjs * Copyright © 2006 Intel Corporation
3fa225cbcSrjs *
4fa225cbcSrjs * Permission is hereby granted, free of charge, to any person obtaining a
5fa225cbcSrjs * copy of this software and associated documentation files (the "Software"),
6fa225cbcSrjs * to deal in the Software without restriction, including without limitation
7fa225cbcSrjs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fa225cbcSrjs * and/or sell copies of the Software, and to permit persons to whom the
9fa225cbcSrjs * Software is furnished to do so, subject to the following conditions:
10fa225cbcSrjs *
11fa225cbcSrjs * The above copyright notice and this permission notice (including the next
12fa225cbcSrjs * paragraph) shall be included in all copies or substantial portions of the
13fa225cbcSrjs * Software.
14fa225cbcSrjs *
15fa225cbcSrjs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16fa225cbcSrjs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17fa225cbcSrjs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18fa225cbcSrjs * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19fa225cbcSrjs * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20fa225cbcSrjs * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21fa225cbcSrjs * SOFTWARE.
22fa225cbcSrjs *
23fa225cbcSrjs * Authors:
24fa225cbcSrjs *    Xiang Haihao <haihao.xiang@intel.com>
25fa225cbcSrjs *
26fa225cbcSrjs */
27fa225cbcSrjs
28fa225cbcSrjs#ifndef _I915XVMC_H
29fa225cbcSrjs#define _I915XVMC_H
30fa225cbcSrjs
31fa225cbcSrjs#include "intel_xvmc.h"
32fa225cbcSrjs#include "i915_hwmc.h"
33fa225cbcSrjs
34fa225cbcSrjs#define I915_SUBPIC_PALETTE_SIZE        16
35fa225cbcSrjs#define MAX_SUBCONTEXT_LEN              1024
36fa225cbcSrjs
37fa225cbcSrjs#define PCI_CHIP_I915_G                 0x2582
38fa225cbcSrjs#define PCI_CHIP_I915_GM                0x2592
39fa225cbcSrjs#define PCI_CHIP_I945_G                 0x2772
40fa225cbcSrjs#define PCI_CHIP_I945_GM                0x27A2
41fa225cbcSrjs#define PCI_CHIP_I945_GME               0x27AE
42fa225cbcSrjs#define PCI_CHIP_G33_G                  0x29C2
43fa225cbcSrjs#define PCI_CHIP_Q35_G                  0x29B2
44fa225cbcSrjs#define PCI_CHIP_Q33_G                  0x29D2
45fa225cbcSrjs
46fa225cbcSrjs/*
47fa225cbcSrjs * i915XvMCContext:
48fa225cbcSrjs *	Private Context data referenced via the privData
49fa225cbcSrjs *      pointer in the XvMCContext structure.
50fa225cbcSrjs */
51fa225cbcSrjstypedef struct _i915XvMCContext {
52fa225cbcSrjs    unsigned int ctxno;
53fa225cbcSrjs    unsigned int last_flip;
54fa225cbcSrjs    unsigned int dual_prime; /* Flag to identify when dual prime is in use. */
55fa225cbcSrjs    unsigned int yStride;
56fa225cbcSrjs    unsigned int uvStride;
57fa225cbcSrjs    unsigned short ref;
58fa225cbcSrjs    unsigned int depth;
59fa225cbcSrjs    XvPortID port;		       /* Xv Port ID when displaying */
60fa225cbcSrjs    int haveXv;                        /* Have I initialized the Xv
61fa225cbcSrjs                                        * connection for this surface? */
62fa225cbcSrjs    XvImage *xvImage;                  /* Fake Xv Image used for command
63fa225cbcSrjs                                        * buffer transport to the X server */
64fa225cbcSrjs    GC  gc;                            /* X GC needed for displaying */
65fa225cbcSrjs    Drawable draw;                     /* Drawable to undisplay from */
66fa225cbcSrjs    void *drawHash;
67fa225cbcSrjs    int deviceID;
68fa225cbcSrjs
69fa225cbcSrjs    intel_xvmc_drm_map_t sis;
70fa225cbcSrjs    intel_xvmc_drm_map_t msb;
71fa225cbcSrjs    intel_xvmc_drm_map_t ssb;
72fa225cbcSrjs    intel_xvmc_drm_map_t psp;
73fa225cbcSrjs    intel_xvmc_drm_map_t psc;
74fa225cbcSrjs    intel_xvmc_drm_map_t corrdata;
75fa225cbcSrjs} i915XvMCContext;
76fa225cbcSrjs
77fa225cbcSrjs/*
78fa225cbcSrjs * i915XvMCSubpicture:
79fa225cbcSrjs *  Private data structure for each XvMCSubpicture. This
80fa225cbcSrjs *  structure is referenced by the privData pointer in the XvMCSubpicture
81fa225cbcSrjs *  structure.
82fa225cbcSrjs */
83fa225cbcSrjstypedef struct _i915XvMCSubpicture {
84fa225cbcSrjs    unsigned int srfNo;
85fa225cbcSrjs    unsigned int last_render;
86fa225cbcSrjs    unsigned int last_flip;
87fa225cbcSrjs    unsigned int pitch;
88fa225cbcSrjs    unsigned char palette[3][16];
89fa225cbcSrjs    intel_xvmc_drm_map_t srf;
90fa225cbcSrjs    i915XvMCContext *privContext;
91fa225cbcSrjs} i915XvMCSubpicture;
92fa225cbcSrjs
93fa225cbcSrjs/* Number of YUV buffers per surface */
94fa225cbcSrjs#define I830_MAX_BUFS 2
95fa225cbcSrjs
96fa225cbcSrjs/*
97fa225cbcSrjs * i915XvMCSurface: Private data structure for each XvMCSurface. This
98fa225cbcSrjs *  structure is referenced by the privData pointer in the XvMCSurface
99fa225cbcSrjs *  structure.
100fa225cbcSrjs */
101fa225cbcSrjstypedef struct _i915XvMCSurface {
102fa225cbcSrjs    unsigned int srfNo;                    /* XvMC private surface numbers */
103fa225cbcSrjs    unsigned int last_render;
104fa225cbcSrjs    unsigned int last_flip;
105fa225cbcSrjs    unsigned int yStride;                  /* Stride of YUV420 Y component. */
106fa225cbcSrjs    unsigned int uvStride;
107fa225cbcSrjs    unsigned int width;                    /* Dimensions */
108fa225cbcSrjs    unsigned int height;
109fa225cbcSrjs    intel_xvmc_drm_map_t srf;
110fa225cbcSrjs    i915XvMCContext *privContext;
111fa225cbcSrjs    i915XvMCSubpicture *privSubPic;     /* Subpicture to be blended when
112fa225cbcSrjs                                         * displaying. NULL if none. */
113fa225cbcSrjs} i915XvMCSurface;
114fa225cbcSrjs
115fa225cbcSrjs#endif /* _I915XVMC_H */
116