1/*
2 * Copyright © 2006 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 *    Wang Zhenyu <zhenyu.z.wang@intel.com>
25 *    Keith Packard <keithp@keithp.com>
26 */
27
28include(`exa_wm.g4i')
29
30/*
31 * Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2),
32 *
33 * Note that the SIMD16 write message takes data for the first
34 * two sub-spans followed by the data for the second two sub-spans
35 * instead of having the two sub-spans interleaved by channel. Weird.
36 */
37
38mov (8) data_port_r_01<1>F	src_sample_r_01<8,8,1>F { align1 };
39mov (8) data_port_g_01<1>F	src_sample_g_01<8,8,1>F { align1 };
40mov (8) data_port_b_01<1>F	src_sample_b_01<8,8,1>F { align1 };
41mov (8) data_port_a_01<1>F	src_sample_a_01<8,8,1>F { align1 };
42
43mov (8) data_port_r_23<1>F	src_sample_r_23<8,8,1>F { sechalf align1 };
44mov (8) data_port_g_23<1>F	src_sample_g_23<8,8,1>F { sechalf align1 };
45mov (8) data_port_b_23<1>F	src_sample_b_23<8,8,1>F { sechalf align1 };
46mov (8) data_port_a_23<1>F 	src_sample_a_23<8,8,1>F { sechalf align1 };
47
48/* m0, m1 are all direct passed by PS thread payload */
49mov (8) data_port_msg_1<1>UD	g1<8,8,1>UD		{ mask_disable align1 };
50
51/* write */
52send (16) 
53	data_port_msg_0_ind 
54	acc0<1>UW 
55	g0<8,8,1>UW 
56	write (
57	       0,  /* binding_table */
58	       8,  /* pixel scordboard clear, msg type simd16 single source */
59	       4,  /* render target write */
60	       0   /* no write commit message */
61	) 
62	mlen 10
63	rlen 0
64	{ align1 EOT };
65
66nop;
67nop;
68nop;
69nop;
70nop;
71nop;
72nop;
73nop;
74
75