intel.h revision 42542f5f
1/************************************************************************** 2 3Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 4Copyright © 2002 David Dawes 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining a 9copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sub license, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial portions 18of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 24ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 * David Dawes <dawes@xfree86.org> 34 * 35 */ 36 37#ifdef HAVE_CONFIG_H 38#include "config.h" 39#endif 40 41#if 0 42#define I830DEBUG 43#endif 44 45#include <stdint.h> 46 47#ifndef REMAP_RESERVED 48#define REMAP_RESERVED 0 49#endif 50 51#ifndef _I830_H_ 52#define _I830_H_ 53 54#include "xorg-server.h" 55#include "xf86_OSproc.h" 56#include "compiler.h" 57#include "xf86Pci.h" 58#include "xf86Cursor.h" 59#include "xf86xv.h" 60#include "xf86Crtc.h" 61#include "xf86RandR12.h" 62 63#include "xorg-server.h" 64#include <pciaccess.h> 65 66#define _XF86DRI_SERVER_ 67#include "drm.h" 68#include "dri2.h" 69#include "intel_bufmgr.h" 70#include "i915_drm.h" 71 72#include "intel_driver.h" 73#include "intel_options.h" 74#include "intel_list.h" 75#include "compat-api.h" 76 77#if HAVE_UDEV 78#include <libudev.h> 79#endif 80 81#if HAVE_DRI3 82#include "misync.h" 83#endif 84 85/* remain compatible to xorg-server 1.6 */ 86#ifndef MONITOR_EDID_COMPLETE_RAWDATA 87#define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA 88#endif 89 90#if XF86_CRTC_VERSION >= 5 91#define INTEL_PIXMAP_SHARING 1 92#endif 93 94#define MAX_PIPES 4 /* consider making all users dynamic */ 95 96struct intel_pixmap { 97 dri_bo *bo; 98 99 struct list batch; 100 101 uint16_t stride; 102 uint8_t tiling; 103 int8_t busy :2; 104 uint8_t dirty :1; 105 uint8_t offscreen :1; 106 uint8_t pinned :5; 107#define PIN_SCANOUT 0x1 108#define PIN_DRI2 0x2 109#define PIN_DRI3 0x4 110#define PIN_PRIME 0x8 111#define PIN_GLAMOR 0x10 112}; 113 114#if HAS_DEVPRIVATEKEYREC 115extern DevPrivateKeyRec uxa_pixmap_index; 116#else 117extern int uxa_pixmap_index; 118#endif 119 120static inline struct intel_pixmap *intel_get_pixmap_private(PixmapPtr pixmap) 121{ 122#if HAS_DEVPRIVATEKEYREC 123 return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index); 124#else 125 return dixLookupPrivate(&pixmap->devPrivates, &uxa_pixmap_index); 126#endif 127} 128 129static inline Bool intel_pixmap_is_busy(struct intel_pixmap *priv) 130{ 131 if (priv->busy == -1) 132 priv->busy = drm_intel_bo_busy(priv->bo); 133 return priv->busy; 134} 135 136static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixmap *intel) 137{ 138 dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel); 139} 140 141static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap) 142{ 143 return pixmap && intel_get_pixmap_private(pixmap)->dirty; 144} 145 146static inline Bool intel_pixmap_tiled(PixmapPtr pixmap) 147{ 148 return intel_get_pixmap_private(pixmap)->tiling != I915_TILING_NONE; 149} 150 151dri_bo *intel_get_pixmap_bo(PixmapPtr pixmap); 152void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo); 153 154#include "common.h" 155 156#define PITCH_NONE 0 157 158/** enumeration of 3d consumers so some can maintain invariant state. */ 159enum last_3d { 160 LAST_3D_OTHER, 161 LAST_3D_VIDEO, 162 LAST_3D_RENDER, 163 LAST_3D_ROTATION 164}; 165 166enum dri_type { 167 DRI_DISABLED, 168 DRI_NONE, 169 DRI_ACTIVE 170}; 171 172typedef struct intel_screen_private { 173 ScrnInfoPtr scrn; 174 int cpp; 175 176#define RENDER_BATCH I915_EXEC_RENDER 177#define BLT_BATCH I915_EXEC_BLT 178 unsigned int current_batch; 179 180 void *modes; 181 drm_intel_bo *front_buffer, *back_buffer; 182 PixmapPtr back_pixmap; 183 unsigned int back_name; 184 long front_pitch, front_tiling; 185 186 dri_bufmgr *bufmgr; 187 188 uint32_t batch_ptr[4096]; 189 /** Byte offset in batch_ptr for the next dword to be emitted. */ 190 unsigned int batch_used; 191 /** Position in batch_ptr at the start of the current BEGIN_BATCH */ 192 unsigned int batch_emit_start; 193 /** Number of bytes to be emitted in the current BEGIN_BATCH. */ 194 uint32_t batch_emitting; 195 dri_bo *batch_bo, *last_batch_bo[2]; 196 /** Whether we're in a section of code that can't tolerate flushing */ 197 Bool in_batch_atomic; 198 /** Ending batch_used that was verified by intel_start_batch_atomic() */ 199 int batch_atomic_limit; 200 struct list batch_pixmaps; 201 drm_intel_bo *wa_scratch_bo; 202 OsTimerPtr cache_expire; 203 204 /* For Xvideo */ 205 Bool use_overlay; 206#ifdef INTEL_XVMC 207 /* For XvMC */ 208 Bool XvMCEnabled; 209#endif 210 211 CreateScreenResourcesProcPtr CreateScreenResources; 212 213 Bool shadow_present; 214 215 unsigned int tiling; 216#define INTEL_TILING_FB 0x1 217#define INTEL_TILING_2D 0x2 218#define INTEL_TILING_3D 0x4 219#define INTEL_TILING_ALL (~0) 220 221 Bool swapbuffers_wait; 222 Bool has_relaxed_fencing; 223 224 int Chipset; 225 EntityInfoPtr pEnt; 226 struct pci_device *PciInfo; 227 const struct intel_device_info *info; 228 229 unsigned int BR[20]; 230 231 CloseScreenProcPtr CloseScreen; 232 233 void (*context_switch) (struct intel_screen_private *intel, 234 int new_mode); 235 void (*vertex_flush) (struct intel_screen_private *intel); 236 void (*batch_flush) (struct intel_screen_private *intel); 237 void (*batch_commit_notify) (struct intel_screen_private *intel); 238 239 struct _UxaDriver *uxa_driver; 240 int uxa_flags; 241 Bool need_sync; 242 int accel_pixmap_offset_alignment; 243 int accel_max_x; 244 int accel_max_y; 245 int max_bo_size; 246 int max_gtt_map_size; 247 int max_tiling_size; 248 249 Bool XvDisabled; /* Xv disabled in PreInit. */ 250 Bool XvEnabled; /* Xv enabled for this generation. */ 251 Bool XvPreferOverlay; 252 253 int colorKey; 254 XF86VideoAdaptorPtr adaptor; 255 ScreenBlockHandlerProcPtr BlockHandler; 256 Bool overlayOn; 257 258 struct { 259 drm_intel_bo *gen4_vs_bo; 260 drm_intel_bo *gen4_sf_bo; 261 drm_intel_bo *gen4_wm_packed_bo; 262 drm_intel_bo *gen4_wm_planar_bo; 263 drm_intel_bo *gen4_cc_bo; 264 drm_intel_bo *gen4_cc_vp_bo; 265 drm_intel_bo *gen4_sampler_bo; 266 drm_intel_bo *gen4_sip_kernel_bo; 267 drm_intel_bo *wm_prog_packed_bo; 268 drm_intel_bo *wm_prog_planar_bo; 269 drm_intel_bo *gen6_blend_bo; 270 drm_intel_bo *gen6_depth_stencil_bo; 271 } video; 272 273 /* Render accel state */ 274 float scale_units[2][2]; 275 /** Transform pointers for src/mask, or NULL if identity */ 276 PictTransform *transform[2]; 277 278 PixmapPtr render_source, render_mask, render_dest; 279 PicturePtr render_source_picture, render_mask_picture, render_dest_picture; 280 Bool needs_3d_invariant; 281 Bool needs_render_state_emit; 282 Bool needs_render_vertex_emit; 283 284 /* i830 render accel state */ 285 uint32_t render_dest_format; 286 uint32_t cblend, ablend, s8_blendctl; 287 288 /* i915 render accel state */ 289 PixmapPtr texture[2]; 290 uint32_t mapstate[6]; 291 uint32_t samplerstate[6]; 292 293 struct { 294 int op; 295 uint32_t dst_format; 296 } i915_render_state; 297 298 struct { 299 int num_sf_outputs; 300 int drawrect; 301 uint32_t blend; 302 dri_bo *samplers; 303 dri_bo *kernel; 304 } gen6_render_state; 305 306 uint32_t prim_offset; 307 void (*prim_emit)(struct intel_screen_private *intel, 308 int srcX, int srcY, 309 int maskX, int maskY, 310 int dstX, int dstY, 311 int w, int h); 312 int floats_per_vertex; 313 int last_floats_per_vertex; 314 uint16_t vertex_offset; 315 uint16_t vertex_count; 316 uint16_t vertex_index; 317 uint16_t vertex_used; 318 uint32_t vertex_id; 319 float vertex_ptr[4*1024]; 320 dri_bo *vertex_bo; 321 322 uint8_t surface_data[16*1024]; 323 uint16_t surface_used; 324 uint16_t surface_table; 325 uint32_t surface_reloc; 326 dri_bo *surface_bo; 327 328 /* 965 render acceleration state */ 329 struct gen4_render_state *gen4_render_state; 330 331 /* DRI enabled this generation. */ 332 enum dri_type dri2, dri3; 333 int drmSubFD; 334 char *deviceName; 335 336 Bool use_pageflipping; 337 Bool use_triple_buffer; 338 Bool force_fallback; 339 Bool has_kernel_flush; 340 Bool needs_flush; 341 342 struct _DRI2FrameEvent *pending_flip[MAX_PIPES]; 343 344 /* Broken-out options. */ 345 OptionInfoPtr Options; 346 347 /* Driver phase/state information */ 348 Bool suspended; 349 350 enum last_3d last_3d; 351 352 /** 353 * User option to print acceleration fallback info to the server log. 354 */ 355 Bool fallback_debug; 356 unsigned debug_flush; 357#if HAVE_UDEV 358 struct udev_monitor *uevent_monitor; 359 pointer uevent_handler; 360#endif 361 Bool has_prime_vmap_flush; 362 363#if HAVE_DRI3 364 SyncScreenFuncsRec save_sync_screen_funcs; 365#endif 366 void (*flush_rendering)(struct intel_screen_private *intel); 367} intel_screen_private; 368 369#define INTEL_INFO(intel) ((intel)->info) 370#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1)) 371#define IS_GEN1(intel) IS_GENx(intel, 1) 372#define IS_GEN2(intel) IS_GENx(intel, 2) 373#define IS_GEN3(intel) IS_GENx(intel, 3) 374#define IS_GEN4(intel) IS_GENx(intel, 4) 375#define IS_GEN5(intel) IS_GENx(intel, 5) 376#define IS_GEN6(intel) IS_GENx(intel, 6) 377#define IS_GEN7(intel) IS_GENx(intel, 7) 378#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075) 379 380/* Some chips have specific errata (or limits) that we need to workaround. */ 381#define IS_I830(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I830_M) 382#define IS_845G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_845_G) 383#define IS_I865G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I865_G) 384 385#define IS_I915G(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_G || (intel)->PciInfo->device_id == PCI_CHIP_E7221_G) 386#define IS_I915GM(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_GM) 387 388#define IS_965_Q(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I965_Q) 389 390/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ 391#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040) 392#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060) 393 394#ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH 395#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 396#endif 397 398enum { 399 DEBUG_FLUSH_BATCHES = 0x1, 400 DEBUG_FLUSH_CACHES = 0x2, 401 DEBUG_FLUSH_WAIT = 0x4, 402}; 403 404extern Bool intel_mode_pre_init(ScrnInfoPtr pScrn, int fd, int cpp); 405extern void intel_mode_init(struct intel_screen_private *intel); 406extern void intel_mode_disable_unused_functions(ScrnInfoPtr scrn); 407extern void intel_mode_remove_fb(intel_screen_private *intel); 408extern void intel_mode_close(intel_screen_private *intel); 409extern void intel_mode_fini(intel_screen_private *intel); 410extern int intel_mode_read_drm_events(intel_screen_private *intel); 411extern void intel_mode_hotplug(intel_screen_private *intel); 412 413typedef void (*intel_drm_handler_proc)(ScrnInfoPtr scrn, 414 xf86CrtcPtr crtc, 415 uint64_t seq, 416 uint64_t usec, 417 void *data); 418 419typedef void (*intel_drm_abort_proc)(ScrnInfoPtr scrn, 420 xf86CrtcPtr crtc, 421 void *data); 422 423extern uint32_t intel_drm_queue_alloc(ScrnInfoPtr scrn, xf86CrtcPtr crtc, void *data, intel_drm_handler_proc handler, intel_drm_abort_proc abort); 424extern void intel_drm_abort(ScrnInfoPtr scrn, Bool (*match)(void *data, void *match_data), void *match_data); 425 426extern int intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, xf86CrtcPtr crtc); 427extern int intel_crtc_id(xf86CrtcPtr crtc); 428extern int intel_output_dpms_status(xf86OutputPtr output); 429extern void intel_copy_fb(ScrnInfoPtr scrn); 430 431int 432intel_get_crtc_msc_ust(ScrnInfoPtr scrn, xf86CrtcPtr crtc, uint64_t *msc, uint64_t *ust); 433 434uint32_t 435intel_crtc_msc_to_sequence(ScrnInfoPtr scrn, xf86CrtcPtr crtc, uint64_t expect); 436 437uint64_t 438intel_sequence_to_crtc_msc(xf86CrtcPtr crtc, uint32_t sequence); 439 440enum DRI2FrameEventType { 441 DRI2_SWAP, 442 DRI2_SWAP_CHAIN, 443 DRI2_FLIP, 444 DRI2_WAITMSC, 445}; 446 447#if XORG_VERSION_CURRENT <= XORG_VERSION_NUMERIC(1,7,99,3,0) 448typedef void (*DRI2SwapEventPtr)(ClientPtr client, void *data, int type, 449 CARD64 ust, CARD64 msc, CARD64 sbc); 450#endif 451 452typedef void (*intel_pageflip_handler_proc) (uint64_t frame, 453 uint64_t usec, 454 void *data); 455 456typedef void (*intel_pageflip_abort_proc) (void *data); 457 458typedef struct _DRI2FrameEvent { 459 struct intel_screen_private *intel; 460 461 XID drawable_id; 462 ClientPtr client; 463 enum DRI2FrameEventType type; 464 int frame; 465 int pipe; 466 467 struct list drawable_resource, client_resource; 468 469 /* for swaps & flips only */ 470 DRI2SwapEventPtr event_complete; 471 void *event_data; 472 DRI2BufferPtr front; 473 DRI2BufferPtr back; 474 475 struct _DRI2FrameEvent *chain; 476} DRI2FrameEventRec, *DRI2FrameEventPtr; 477 478extern Bool intel_do_pageflip(intel_screen_private *intel, 479 dri_bo *new_front, 480 int ref_crtc_hw_id, 481 Bool async, 482 void *pageflip_data, 483 intel_pageflip_handler_proc pageflip_handler, 484 intel_pageflip_abort_proc pageflip_abort); 485 486static inline intel_screen_private * 487intel_get_screen_private(ScrnInfoPtr scrn) 488{ 489 return (intel_screen_private *)(scrn->driverPrivate); 490} 491 492#ifndef ARRAY_SIZE 493#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) 494#endif 495 496#ifndef ALIGN 497#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) 498#endif 499 500#ifndef MIN 501#define MIN(a,b) ((a) < (b) ? (a) : (b)) 502#endif 503 504static inline unsigned long intel_pixmap_pitch(PixmapPtr pixmap) 505{ 506 return (unsigned long)pixmap->devKind; 507} 508 509/* Batchbuffer support macros and functions */ 510#include "intel_batchbuffer.h" 511 512/* I830 specific functions */ 513extern void IntelEmitInvarientState(ScrnInfoPtr scrn); 514extern void I830EmitInvarientState(ScrnInfoPtr scrn); 515extern void I915EmitInvarientState(ScrnInfoPtr scrn); 516 517extern void I830EmitFlush(ScrnInfoPtr scrn); 518 519extern void I830InitVideo(ScreenPtr pScreen); 520extern xf86CrtcPtr intel_covering_crtc(ScrnInfoPtr scrn, BoxPtr box, 521 xf86CrtcPtr desired, BoxPtr crtc_box_ret); 522 523Bool I830DRI2ScreenInit(ScreenPtr pScreen); 524void I830DRI2CloseScreen(ScreenPtr pScreen); 525void I830DRI2FrameEventHandler(unsigned int frame, unsigned int tv_sec, 526 unsigned int tv_usec, DRI2FrameEventPtr flip_info); 527void I830DRI2FlipEventHandler(unsigned int frame, unsigned int tv_sec, 528 unsigned int tv_usec, DRI2FrameEventPtr flip_info); 529 530/* intel_dri3.c */ 531Bool intel_dri3_screen_init(ScreenPtr screen); 532 533extern Bool intel_crtc_on(xf86CrtcPtr crtc); 534int intel_crtc_to_pipe(xf86CrtcPtr crtc); 535 536/* intel_memory.c */ 537unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long size); 538unsigned long intel_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, 539 uint32_t tiling_mode); 540Bool intel_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling); 541void intel_set_gem_max_sizes(ScrnInfoPtr scrn); 542 543drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn, 544 int width, int height, int cpp, 545 int *out_stride, 546 uint32_t *out_tiling); 547 548/* i830_render.c */ 549Bool i830_check_composite(int op, 550 PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 551 int width, int height); 552Bool i830_check_composite_target(PixmapPtr pixmap); 553Bool i830_check_composite_texture(ScreenPtr screen, PicturePtr picture); 554Bool i830_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 555 PicturePtr dest, PixmapPtr sourcecPixmap, 556 PixmapPtr maskPixmap, PixmapPtr destPixmap); 557void i830_composite(PixmapPtr dest, int srcX, int srcY, 558 int maskX, int maskY, int dstX, int dstY, int w, int h); 559void i830_vertex_flush(intel_screen_private *intel); 560 561/* i915_render.c */ 562Bool i915_check_composite(int op, 563 PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 564 int width, int height); 565Bool i915_check_composite_target(PixmapPtr pixmap); 566Bool i915_check_composite_texture(ScreenPtr screen, PicturePtr picture); 567Bool i915_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 568 PicturePtr dest, PixmapPtr sourcecPixmap, 569 PixmapPtr maskPixmap, PixmapPtr destPixmap); 570void i915_composite(PixmapPtr dest, int srcX, int srcY, 571 int maskX, int maskY, int dstX, int dstY, int w, int h); 572void i915_vertex_flush(intel_screen_private *intel); 573void i915_batch_commit_notify(intel_screen_private *intel); 574void i830_batch_commit_notify(intel_screen_private *intel); 575/* i965_render.c */ 576unsigned int gen4_render_state_size(ScrnInfoPtr scrn); 577void gen4_render_state_init(ScrnInfoPtr scrn); 578void gen4_render_state_cleanup(ScrnInfoPtr scrn); 579Bool i965_check_composite(int op, 580 PicturePtr sourcec, PicturePtr mask, PicturePtr dest, 581 int width, int height); 582Bool i965_check_composite_texture(ScreenPtr screen, PicturePtr picture); 583Bool i965_prepare_composite(int op, PicturePtr sourcec, PicturePtr mask, 584 PicturePtr dest, PixmapPtr sourcecPixmap, 585 PixmapPtr maskPixmap, PixmapPtr destPixmap); 586void i965_composite(PixmapPtr dest, int srcX, int srcY, 587 int maskX, int maskY, int dstX, int dstY, int w, int h); 588 589void i965_vertex_flush(intel_screen_private *intel); 590void i965_batch_flush(intel_screen_private *intel); 591void i965_batch_commit_notify(intel_screen_private *intel); 592 593/* i965_3d.c */ 594void gen6_upload_invariant_states(intel_screen_private *intel); 595void gen6_upload_viewport_state_pointers(intel_screen_private *intel, 596 drm_intel_bo *cc_vp_bo); 597void gen7_upload_viewport_state_pointers(intel_screen_private *intel, 598 drm_intel_bo *cc_vp_bo); 599void gen6_upload_urb(intel_screen_private *intel); 600void gen7_upload_urb(intel_screen_private *intel); 601void gen6_upload_cc_state_pointers(intel_screen_private *intel, 602 drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, 603 drm_intel_bo *depth_stencil_bo, 604 uint32_t blend_offset); 605void gen7_upload_cc_state_pointers(intel_screen_private *intel, 606 drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, 607 drm_intel_bo *depth_stencil_bo, 608 uint32_t blend_offset); 609void gen6_upload_sampler_state_pointers(intel_screen_private *intel, 610 drm_intel_bo *sampler_bo); 611void gen7_upload_sampler_state_pointers(intel_screen_private *intel, 612 drm_intel_bo *sampler_bo); 613void gen7_upload_bypass_states(intel_screen_private *intel); 614void gen6_upload_gs_state(intel_screen_private *intel); 615void gen6_upload_vs_state(intel_screen_private *intel); 616void gen6_upload_clip_state(intel_screen_private *intel); 617void gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); 618void gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); 619void gen6_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); 620void gen7_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); 621void gen6_upload_depth_buffer_state(intel_screen_private *intel); 622void gen7_upload_depth_buffer_state(intel_screen_private *intel); 623 624Bool intel_transform_is_affine(PictTransformPtr t); 625Bool 626intel_get_transformed_coordinates(int x, int y, PictTransformPtr transform, 627 float *x_out, float *y_out); 628 629Bool 630intel_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, 631 float *x_out, float *y_out, float *z_out); 632 633static inline void 634intel_debug_fallback(ScrnInfoPtr scrn, const char *format, ...) _X_ATTRIBUTE_PRINTF(2, 3); 635 636static inline void 637intel_debug_fallback(ScrnInfoPtr scrn, const char *format, ...) 638{ 639 intel_screen_private *intel = intel_get_screen_private(scrn); 640 va_list ap; 641 642 va_start(ap, format); 643 if (intel->fallback_debug) { 644 xf86DrvMsg(scrn->scrnIndex, X_INFO, "fallback: "); 645 LogVMessageVerb(X_INFO, 1, format, ap); 646 } 647 va_end(ap); 648} 649 650static inline Bool 651intel_check_pitch_2d(PixmapPtr pixmap) 652{ 653 uint32_t pitch = intel_pixmap_pitch(pixmap); 654 if (pitch > KB(32)) { 655 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 656 intel_debug_fallback(scrn, "pitch exceeds 2d limit 32K\n"); 657 return FALSE; 658 } 659 return TRUE; 660} 661 662/* For pre-965 chip only, as they have 8KB limit for 3D */ 663static inline Bool 664intel_check_pitch_3d(PixmapPtr pixmap) 665{ 666 uint32_t pitch = intel_pixmap_pitch(pixmap); 667 if (pitch > KB(8)) { 668 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 669 intel_debug_fallback(scrn, "pitch exceeds 3d limit 8K\n"); 670 return FALSE; 671 } 672 return TRUE; 673} 674 675/** 676 * Little wrapper around drm_intel_bo_reloc to return the initial value you 677 * should stuff into the relocation entry. 678 * 679 * If only we'd done this before settling on the library API. 680 */ 681static inline uint32_t 682intel_emit_reloc(drm_intel_bo * bo, uint32_t offset, 683 drm_intel_bo * target_bo, uint32_t target_offset, 684 uint32_t read_domains, uint32_t write_domain) 685{ 686 drm_intel_bo_emit_reloc(bo, offset, target_bo, target_offset, 687 read_domains, write_domain); 688 689 return target_bo->offset + target_offset; 690} 691 692static inline drm_intel_bo *intel_bo_alloc_for_data(intel_screen_private *intel, 693 const void *data, 694 unsigned int size, 695 const char *name) 696{ 697 drm_intel_bo *bo; 698 int ret; 699 700 bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096); 701 assert(bo); 702 703 ret = drm_intel_bo_subdata(bo, 0, size, data); 704 assert(ret == 0); 705 706 return bo; 707 (void)ret; 708} 709 710void intel_debug_flush(ScrnInfoPtr scrn); 711 712static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable) 713{ 714 ScreenPtr screen = drawable->pScreen; 715 716 if (drawable->type == DRAWABLE_PIXMAP) 717 return (PixmapPtr) drawable; 718 else 719 return screen->GetWindowPixmap((WindowPtr) drawable); 720} 721 722static inline Bool pixmap_is_scanout(PixmapPtr pixmap) 723{ 724 ScreenPtr screen = pixmap->drawable.pScreen; 725 726 return pixmap == screen->GetScreenPixmap(screen); 727} 728 729Bool intel_uxa_init(ScreenPtr pScreen); 730Bool intel_uxa_create_screen_resources(ScreenPtr pScreen); 731void intel_uxa_block_handler(intel_screen_private *intel); 732Bool intel_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table, 733 int num_bos); 734 735static inline Bool intel_pixmap_is_offscreen(PixmapPtr pixmap) 736{ 737 struct intel_pixmap *priv = intel_get_pixmap_private(pixmap); 738 return priv && priv->offscreen; 739} 740 741#if HAVE_DRI3 742Bool intel_sync_init(ScreenPtr screen); 743void intel_sync_close(ScreenPtr screen); 744#else 745static inline Bool intel_sync_init(ScreenPtr screen) { return 0; } 746void intel_sync_close(ScreenPtr screen); 747#endif 748 749/* 750 * intel_present.c 751 */ 752 753#if 0 754#define DebugPresent(x) ErrorF x 755#else 756#define DebugPresent(x) 757#endif 758 759#if HAVE_PRESENT 760Bool intel_present_screen_init(ScreenPtr screen); 761#else 762static inline Bool intel_present_screen_init(ScreenPtr screen) { return 0; } 763#endif 764 765#endif /* _I830_H_ */ 766