mga_macros.h revision fe5e51b7
1fe5e51b7Smrg/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/mga/mga_macros.h,v 1.21 2001/09/26 12:59:17 alanh Exp $ */
2fe5e51b7Smrg
3fe5e51b7Smrg#ifndef _MGA_MACROS_H_
4fe5e51b7Smrg#define _MGA_MACROS_H_
5fe5e51b7Smrg
6fe5e51b7Smrg#ifdef XSERVER_LIBPCIACCESS
7fe5e51b7Smrg#define MGA_IO_ADDRESS(p) (p)->PciInfo->regions[(p)->io_bar].base_addr
8fe5e51b7Smrg#define VENDOR_ID(p)      (p)->vendor_id
9fe5e51b7Smrg#define DEVICE_ID(p)      (p)->device_id
10fe5e51b7Smrg#define SUBSYS_ID(p)      (p)->subdevice_id
11fe5e51b7Smrg#define CHIP_REVISION(p)  (p)->revision
12fe5e51b7Smrg#else
13fe5e51b7Smrg#define MGA_IO_ADDRESS(p) (p)->IOAddress
14fe5e51b7Smrg#define VENDOR_ID(p)      (p)->vendor
15fe5e51b7Smrg#define DEVICE_ID(p)      (p)->chipType
16fe5e51b7Smrg#define SUBSYS_ID(p)      (p)->subsysCard
17fe5e51b7Smrg#define CHIP_REVISION(p)  (p)->chipRev
18fe5e51b7Smrg#endif
19fe5e51b7Smrg
20fe5e51b7Smrg#define RGBEQUAL(c) (!((((c) >> 8) ^ (c)) & 0xffff))
21fe5e51b7Smrg
22fe5e51b7Smrg#ifdef XF86DRI
23fe5e51b7Smrg#define MGA_SYNC_XTAG                 0x275f4200
24fe5e51b7Smrg
25fe5e51b7Smrg#define MGABUSYWAIT() do { \
26fe5e51b7SmrgOUTREG(MGAREG_DWGSYNC, MGA_SYNC_XTAG); \
27fe5e51b7Smrgwhile(INREG(MGAREG_DWGSYNC) != MGA_SYNC_XTAG) ; \
28fe5e51b7Smrg}while(0);
29fe5e51b7Smrg
30fe5e51b7Smrg#endif
31fe5e51b7Smrg
32fe5e51b7Smrg#define MGAISBUSY() (INREG8(MGAREG_Status + 2) & 0x01)
33fe5e51b7Smrg
34fe5e51b7Smrg#define WAITFIFO(cnt) \
35fe5e51b7Smrg   if(!pMga->UsePCIRetry) {\
36fe5e51b7Smrg	register int n = cnt; \
37fe5e51b7Smrg	if(n > pMga->FifoSize) n = pMga->FifoSize; \
38fe5e51b7Smrg	while(pMga->fifoCount < (n))\
39fe5e51b7Smrg	    pMga->fifoCount = INREG8(MGAREG_FIFOSTATUS);\
40fe5e51b7Smrg	pMga->fifoCount -= n;\
41fe5e51b7Smrg   }
42fe5e51b7Smrg
43fe5e51b7Smrg#define XYADDRESS(x,y) \
44fe5e51b7Smrg    ((y) * pMga->CurrentLayout.displayWidth + (x) + pMga->YDstOrg)
45fe5e51b7Smrg
46fe5e51b7Smrg#define MAKEDMAINDEX(index)  ((((index) >> 2) & 0x7f) | (((index) >> 6) & 0x80))
47fe5e51b7Smrg
48fe5e51b7Smrg#define DMAINDICES(one,two,three,four)	\
49fe5e51b7Smrg	( MAKEDMAINDEX(one) | \
50fe5e51b7Smrg	 (MAKEDMAINDEX(two) << 8) | \
51fe5e51b7Smrg	 (MAKEDMAINDEX(three) << 16) | \
52fe5e51b7Smrg 	 (MAKEDMAINDEX(four) << 24) )
53fe5e51b7Smrg
54fe5e51b7Smrg#define SET_PLANEMASK_REPLICATED(mask, rep_mask, bpp) \
55fe5e51b7Smrg    do { \
56fe5e51b7Smrg	if( (bpp != 24) \
57fe5e51b7Smrg	    && !(pMga->AccelFlags & MGA_NO_PLANEMASK) \
58fe5e51b7Smrg	    && ((mask) != pMga->PlaneMask)) { \
59fe5e51b7Smrg	   pMga->PlaneMask = (mask); \
60fe5e51b7Smrg	   OUTREG(MGAREG_PLNWT,(rep_mask)); \
61fe5e51b7Smrg	} \
62fe5e51b7Smrg    } while( 0 )
63fe5e51b7Smrg
64fe5e51b7Smrg#define DISABLE_CLIP() { \
65fe5e51b7Smrg	pMga->AccelFlags &= ~CLIPPER_ON; \
66fe5e51b7Smrg	WAITFIFO(1); \
67fe5e51b7Smrg	OUTREG(MGAREG_CXBNDRY, 0xFFFF0000); }
68fe5e51b7Smrg
69fe5e51b7Smrg#ifdef XF86DRI
70fe5e51b7Smrg#define CHECK_DMA_QUIESCENT(pMGA, pScrn) {	\
71fe5e51b7Smrg   if (!pMGA->haveQuiescense) {			\
72fe5e51b7Smrg      pMGA->GetQuiescence( pScrn );		\
73fe5e51b7Smrg   }						\
74fe5e51b7Smrg}
75fe5e51b7Smrg#else
76fe5e51b7Smrg#define CHECK_DMA_QUIESCENT(pMGA, pScrn)
77fe5e51b7Smrg#endif
78fe5e51b7Smrg
79fe5e51b7Smrg#ifdef USEMGAHAL
80fe5e51b7Smrg#define MGA_HAL(x) { \
81fe5e51b7Smrg	MGAPtr pMga = MGAPTR(pScrn); \
82fe5e51b7Smrg	if (pMga->HALLoaded && pMga->chip_attribs->HAL_chipset) { x; } \
83fe5e51b7Smrg}
84fe5e51b7Smrg#define MGA_NOT_HAL(x) { \
85fe5e51b7Smrg	MGAPtr pMga = MGAPTR(pScrn); \
86fe5e51b7Smrg	if (!pMga->HALLoaded || !pMga->chip_attribs->HAL_chipset) { x; } \
87fe5e51b7Smrg}
88fe5e51b7Smrg#else
89fe5e51b7Smrg#define MGA_NOT_HAL(x) { x; }
90fe5e51b7Smrg#endif
91fe5e51b7Smrg
92fe5e51b7Smrg#define MGAISGx50(x) ((x)->is_Gx50)
93fe5e51b7Smrg
94fe5e51b7Smrg#define MGA_DH_NEEDS_HAL(x) (((x)->Chipset == PCI_CHIP_MGAG400) && \
95fe5e51b7Smrg			     ((x)->ChipRev < 0x80))
96fe5e51b7Smrg
97fe5e51b7Smrg#endif /* _MGA_MACROS_H_ */
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