1/* author: stephen crowley, crow@debian.org */ 2 3/* 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * STEPHEN CROWLEY, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 20 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef _MGAREGS_H_ 24#define _MGAREGS_H_ 25 26/*************** (START) AUTOMATICALLY GENERATED REGISTER FILE ***************/ 27/* 28 * Generated on Sat Nov 20 21:25:36 CST 1999 29 */ 30 31 32 33/* 34 * Power Graphic Mode Memory Space Registers 35 */ 36 37# define AGP_PLL_agp2xpllen_MASK 0xfffffffe /* bit 0 */ 38# define AGP_PLL_agp2xpllen_disable 0x0 39# define AGP_PLL_agp2xpllen_enable 0x1 40 41# define AC_src_MASK 0xfffffff0 /* bits 0-3 */ 42# define AC_src_zero 0x0 /* val 0, shift 0 */ 43# define AC_src_one 0x1 /* val 1, shift 0 */ 44# define AC_src_dst_color 0x2 /* val 2, shift 0 */ 45# define AC_src_om_dst_color 0x3 /* val 3, shift 0 */ 46# define AC_src_src_alpha 0x4 /* val 4, shift 0 */ 47# define AC_src_om_src_alpha 0x5 /* val 5, shift 0 */ 48# define AC_src_dst_alpha 0x6 /* val 6, shift 0 */ 49# define AC_src_om_dst_alpha 0x7 /* val 7, shift 0 */ 50# define AC_src_src_alpha_sat 0x8 /* val 8, shift 0 */ 51# define AC_dst_MASK 0xffffff0f /* bits 4-7 */ 52# define AC_dst_zero 0x0 /* val 0, shift 4 */ 53# define AC_dst_one 0x10 /* val 1, shift 4 */ 54# define AC_dst_src_color 0x20 /* val 2, shift 4 */ 55# define AC_dst_om_src_color 0x30 /* val 3, shift 4 */ 56# define AC_dst_src_alpha 0x40 /* val 4, shift 4 */ 57# define AC_dst_om_src_alpha 0x50 /* val 5, shift 4 */ 58# define AC_dst_dst_alpha 0x60 /* val 6, shift 4 */ 59# define AC_dst_om_dst_alpha 0x70 /* val 7, shift 4 */ 60# define AC_amode_MASK 0xfffffcff /* bits 8-9 */ 61# define AC_amode_FCOL 0x0 /* val 0, shift 8 */ 62# define AC_amode_alpha_channel 0x100 /* val 1, shift 8 */ 63# define AC_amode_video_alpha 0x200 /* val 2, shift 8 */ 64# define AC_amode_RSVD 0x300 /* val 3, shift 8 */ 65# define AC_astipple_MASK 0xfffff7ff /* bit 11 */ 66# define AC_astipple_disable 0x0 67# define AC_astipple_enable 0x800 68# define AC_aten_MASK 0xffffefff /* bit 12 */ 69# define AC_aten_disable 0x0 70# define AC_aten_enable 0x1000 71# define AC_atmode_MASK 0xffff1fff /* bits 13-15 */ 72# define AC_atmode_noacmp 0x0 /* val 0, shift 13 */ 73# define AC_atmode_ae 0x4000 /* val 2, shift 13 */ 74# define AC_atmode_ane 0x6000 /* val 3, shift 13 */ 75# define AC_atmode_alt 0x8000 /* val 4, shift 13 */ 76# define AC_atmode_alte 0xa000 /* val 5, shift 13 */ 77# define AC_atmode_agt 0xc000 /* val 6, shift 13 */ 78# define AC_atmode_agte 0xe000 /* val 7, shift 13 */ 79# define AC_atref_MASK 0xff00ffff /* bits 16-23 */ 80# define AC_atref_SHIFT 16 81# define AC_alphasel_MASK 0xfcffffff /* bits 24-25 */ 82# define AC_alphasel_fromtex 0x0 /* val 0, shift 24 */ 83# define AC_alphasel_diffused 0x1000000 /* val 1, shift 24 */ 84# define AC_alphasel_modulated 0x2000000 /* val 2, shift 24 */ 85# define AC_alphasel_trans 0x3000000 /* val 3, shift 24 */ 86 87# define AR0_ar0_MASK 0xfffc0000 /* bits 0-17 */ 88# define AR0_ar0_SHIFT 0 89 90# define AR1_ar1_MASK 0xff000000 /* bits 0-23 */ 91# define AR1_ar1_SHIFT 0 92 93# define AR2_ar2_MASK 0xfffc0000 /* bits 0-17 */ 94# define AR2_ar2_SHIFT 0 95 96# define AR3_ar3_MASK 0xff000000 /* bits 0-23 */ 97# define AR3_ar3_SHIFT 0 98# define AR3_spage_MASK 0xf8ffffff /* bits 24-26 */ 99# define AR3_spage_SHIFT 24 100 101# define AR4_ar4_MASK 0xfffc0000 /* bits 0-17 */ 102# define AR4_ar4_SHIFT 0 103 104# define AR5_ar5_MASK 0xfffc0000 /* bits 0-17 */ 105# define AR5_ar5_SHIFT 0 106 107# define AR6_ar6_MASK 0xfffc0000 /* bits 0-17 */ 108# define AR6_ar6_SHIFT 0 109 110# define BC_besen_MASK 0xfffffffe /* bit 0 */ 111# define BC_besen_disable 0x0 112# define BC_besen_enable 0x1 113# define BC_besv1srcstp_MASK 0xffffffbf /* bit 6 */ 114# define BC_besv1srcstp_even 0x0 115# define BC_besv1srcstp_odd 0x40 116# define BC_besv2srcstp_MASK 0xfffffeff /* bit 8 */ 117# define BC_besv2srcstp_disable 0x0 118# define BC_besv2srcstp_enable 0x100 119# define BC_beshfen_MASK 0xfffffbff /* bit 10 */ 120# define BC_beshfen_disable 0x0 121# define BC_beshfen_enable 0x400 122# define BC_besvfen_MASK 0xfffff7ff /* bit 11 */ 123# define BC_besvfen_disable 0x0 124# define BC_besvfen_enable 0x800 125# define BC_beshfixc_MASK 0xffffefff /* bit 12 */ 126# define BC_beshfixc_weight 0x0 127# define BC_beshfixc_coeff 0x1000 128# define BC_bescups_MASK 0xfffeffff /* bit 16 */ 129# define BC_bescups_disable 0x0 130# define BC_bescups_enable 0x10000 131# define BC_bes420pl_MASK 0xfffdffff /* bit 17 */ 132# define BC_bes420pl_422 0x0 133# define BC_bes420pl_420 0x20000 134# define BC_besdith_MASK 0xfffbffff /* bit 18 */ 135# define BC_besdith_disable 0x0 136# define BC_besdith_enable 0x40000 137# define BC_beshmir_MASK 0xfff7ffff /* bit 19 */ 138# define BC_beshmir_disable 0x0 139# define BC_beshmir_enable 0x80000 140# define BC_besbwen_MASK 0xffefffff /* bit 20 */ 141# define BC_besbwen_color 0x0 142# define BC_besbwen_bw 0x100000 143# define BC_besblank_MASK 0xffdfffff /* bit 21 */ 144# define BC_besblank_disable 0x0 145# define BC_besblank_enable 0x200000 146# define BC_besfselm_MASK 0xfeffffff /* bit 24 */ 147# define BC_besfselm_soft 0x0 148# define BC_besfselm_hard 0x1000000 149# define BC_besfsel_MASK 0xf9ffffff /* bits 25-26 */ 150# define BC_besfsel_a1 0x0 /* val 0, shift 25 */ 151# define BC_besfsel_a2 0x2000000 /* val 1, shift 25 */ 152# define BC_besfsel_b1 0x4000000 /* val 2, shift 25 */ 153# define BC_besfsel_b2 0x6000000 /* val 3, shift 25 */ 154 155# define BGC_beshzoom_MASK 0xfffffffe /* bit 0 */ 156# define BGC_beshzoom_disable 0x0 157# define BGC_beshzoom_enable 0x1 158# define BGC_beshzoomf_MASK 0xfffffffd /* bit 1 */ 159# define BGC_beshzoomf_disable 0x0 160# define BGC_beshzoomf_enable 0x2 161# define BGC_bescorder_MASK 0xfffffff7 /* bit 3 */ 162# define BGC_bescorder_even 0x0 163# define BGC_bescorder_odd 0x8 164# define BGC_besreghup_MASK 0xffffffef /* bit 4 */ 165# define BGC_besreghup_disable 0x0 166# define BGC_besreghup_enable 0x10 167# define BGC_besvcnt_MASK 0xf000ffff /* bits 16-27 */ 168# define BGC_besvcnt_SHIFT 16 169 170# define BHC_besright_MASK 0xfffff800 /* bits 0-10 */ 171# define BHC_besright_SHIFT 0 172# define BHC_besleft_MASK 0xf800ffff /* bits 16-26 */ 173# define BHC_besleft_SHIFT 16 174 175# define BHISF_beshiscal_MASK 0xffe00003 /* bits 2-20 */ 176# define BHISF_beshiscal_SHIFT 2 177 178# define BHSE_beshsrcend_MASK 0xfc000003 /* bits 2-25 */ 179# define BHSE_beshsrcend_SHIFT 2 180 181# define BHSL_beshsrclst_MASK 0xfc00ffff /* bits 16-25 */ 182# define BHSL_beshsrclst_SHIFT 16 183 184# define BHSS_beshsrcst_MASK 0xfc000003 /* bits 2-25 */ 185# define BHSS_beshsrcst_SHIFT 2 186 187# define BP_bespitch_MASK 0xfffff000 /* bits 0-11 */ 188# define BP_bespitch_SHIFT 0 189 190# define BS_besstat_MASK 0xfffffffc /* bits 0-1 */ 191# define BS_besstat_a1 0x0 /* val 0, shift 0 */ 192# define BS_besstat_a2 0x1 /* val 1, shift 0 */ 193# define BS_besstat_b1 0x2 /* val 2, shift 0 */ 194# define BS_besstat_b2 0x3 /* val 3, shift 0 */ 195 196# define BSF_besv1srclast_MASK 0xfffffc00 /* bits 0-9 */ 197# define BSF_besv1srclast_SHIFT 0 198 199# define BSF_besv2srclst_MASK 0xfffffc00 /* bits 0-9 */ 200# define BSF_besv2srclst_SHIFT 0 201 202# define BSF_besv1wght_MASK 0xffff0003 /* bits 2-15 */ 203# define BSF_besv1wght_SHIFT 2 204# define BSF_besv1wghts_MASK 0xfffeffff /* bit 16 */ 205# define BSF_besv1wghts_disable 0x0 206# define BSF_besv1wghts_enable 0x10000 207 208# define BSF_besv2wght_MASK 0xffff0003 /* bits 2-15 */ 209# define BSF_besv2wght_SHIFT 2 210# define BSF_besv2wghts_MASK 0xfffeffff /* bit 16 */ 211# define BSF_besv2wghts_disable 0x0 212# define BSF_besv2wghts_enable 0x10000 213 214# define BVC_besbot_MASK 0xfffff800 /* bits 0-10 */ 215# define BVC_besbot_SHIFT 0 216# define BVC_bestop_MASK 0xf800ffff /* bits 16-26 */ 217# define BVC_bestop_SHIFT 16 218 219# define BVISF_besviscal_MASK 0xffe00003 /* bits 2-20 */ 220# define BVISF_besviscal_SHIFT 2 221 222# define CXB_cxleft_MASK 0xfffff000 /* bits 0-11 */ 223# define CXB_cxleft_SHIFT 0 224# define CXB_cxright_MASK 0xf000ffff /* bits 16-27 */ 225# define CXB_cxright_SHIFT 16 226 227# define DO_dstmap_MASK 0xfffffffe /* bit 0 */ 228# define DO_dstmap_fb 0x0 229# define DO_dstmap_sys 0x1 230# define DO_dstacc_MASK 0xfffffffd /* bit 1 */ 231# define DO_dstacc_pci 0x0 232# define DO_dstacc_agp 0x2 233# define DO_dstorg_MASK 0x7 /* bits 3-31 */ 234# define DO_dstorg_SHIFT 3 235 236# define DC_opcod_MASK 0xfffffff0 /* bits 0-3 */ 237# define DC_opcod_line_open 0x0 /* val 0, shift 0 */ 238# define DC_opcod_autoline_open 0x1 /* val 1, shift 0 */ 239# define DC_opcod_line_close 0x2 /* val 2, shift 0 */ 240# define DC_opcod_autoline_close 0x3 /* val 3, shift 0 */ 241# define DC_opcod_trap 0x4 /* val 4, shift 0 */ 242# define DC_opcod_texture_trap 0x6 /* val 6, shift 0 */ 243# define DC_opcod_bitblt 0x8 /* val 8, shift 0 */ 244# define DC_opcod_iload 0x9 /* val 9, shift 0 */ 245# define DC_atype_MASK 0xffffff8f /* bits 4-6 */ 246# define DC_atype_rpl 0x0 /* val 0, shift 4 */ 247# define DC_atype_rstr 0x10 /* val 1, shift 4 */ 248# define DC_atype_zi 0x30 /* val 3, shift 4 */ 249# define DC_atype_blk 0x40 /* val 4, shift 4 */ 250# define DC_atype_i 0x70 /* val 7, shift 4 */ 251# define DC_linear_MASK 0xffffff7f /* bit 7 */ 252# define DC_linear_xy 0x0 253# define DC_linear_linear 0x80 254# define DC_zmode_MASK 0xfffff8ff /* bits 8-10 */ 255# define DC_zmode_nozcmp 0x0 /* val 0, shift 8 */ 256# define DC_zmode_ze 0x200 /* val 2, shift 8 */ 257# define DC_zmode_zne 0x300 /* val 3, shift 8 */ 258# define DC_zmode_zlt 0x400 /* val 4, shift 8 */ 259# define DC_zmode_zlte 0x500 /* val 5, shift 8 */ 260# define DC_zmode_zgt 0x600 /* val 6, shift 8 */ 261# define DC_zmode_zgte 0x700 /* val 7, shift 8 */ 262# define DC_solid_MASK 0xfffff7ff /* bit 11 */ 263# define DC_solid_disable 0x0 264# define DC_solid_enable 0x800 265# define DC_arzero_MASK 0xffffefff /* bit 12 */ 266# define DC_arzero_disable 0x0 267# define DC_arzero_enable 0x1000 268# define DC_sgnzero_MASK 0xffffdfff /* bit 13 */ 269# define DC_sgnzero_disable 0x0 270# define DC_sgnzero_enable 0x2000 271# define DC_shftzero_MASK 0xffffbfff /* bit 14 */ 272# define DC_shftzero_disable 0x0 273# define DC_shftzero_enable 0x4000 274# define DC_bop_MASK 0xfff0ffff /* bits 16-19 */ 275# define DC_bop_SHIFT 16 276# define DC_trans_MASK 0xff0fffff /* bits 20-23 */ 277# define DC_trans_SHIFT 20 278# define DC_bltmod_MASK 0xe1ffffff /* bits 25-28 */ 279# define DC_bltmod_bmonolef 0x0 /* val 0, shift 25 */ 280# define DC_bltmod_bmonowf 0x8000000 /* val 4, shift 25 */ 281# define DC_bltmod_bplan 0x2000000 /* val 1, shift 25 */ 282# define DC_bltmod_bfcol 0x4000000 /* val 2, shift 25 */ 283# define DC_bltmod_bu32bgr 0x6000000 /* val 3, shift 25 */ 284# define DC_bltmod_bu32rgb 0xe000000 /* val 7, shift 25 */ 285# define DC_bltmod_bu24bgr 0x16000000 /* val 11, shift 25 */ 286# define DC_bltmod_bu24rgb 0x1e000000 /* val 15, shift 25 */ 287# define DC_pattern_MASK 0xdfffffff /* bit 29 */ 288# define DC_pattern_disable 0x0 289# define DC_pattern_enable 0x20000000 290# define DC_transc_MASK 0xbfffffff /* bit 30 */ 291# define DC_transc_disable 0x0 292# define DC_transc_enable 0x40000000 293# define DC_clipdis_MASK 0x7fffffff /* bit 31 */ 294# define DC_clipdis_disable 0x0 295# define DC_clipdis_enable 0x80000000 296 297# define DS_dwgsyncaddr_MASK 0x3 /* bits 2-31 */ 298# define DS_dwgsyncaddr_SHIFT 2 299 300# define FS_fifocount_MASK 0xffffff80 /* bits 0-6 */ 301# define FS_fifocount_SHIFT 0 302# define FS_bfull_MASK 0xfffffeff /* bit 8 */ 303# define FS_bfull_disable 0x0 304# define FS_bfull_enable 0x100 305# define FS_bempty_MASK 0xfffffdff /* bit 9 */ 306# define FS_bempty_disable 0x0 307# define FS_bempty_enable 0x200 308 309# define XA_fxleft_MASK 0xffff0000 /* bits 0-15 */ 310# define XA_fxleft_SHIFT 0 311# define XA_fxright_MASK 0xffff /* bits 16-31 */ 312# define XA_fxright_SHIFT 16 313 314# define IC_softrapiclr_MASK 0xfffffffe /* bit 0 */ 315# define IC_softrapiclr_disable 0x0 316# define IC_softrapiclr_enable 0x1 317# define IC_pickiclr_MASK 0xfffffffb /* bit 2 */ 318# define IC_pickiclr_disable 0x0 319# define IC_pickiclr_enable 0x4 320# define IC_vlineiclr_MASK 0xffffffdf /* bit 5 */ 321# define IC_vlineiclr_disable 0x0 322# define IC_vlineiclr_enable 0x20 323# define IC_wiclr_MASK 0xffffff7f /* bit 7 */ 324# define IC_wiclr_disable 0x0 325# define IC_wiclr_enable 0x80 326# define IC_wciclr_MASK 0xfffffeff /* bit 8 */ 327# define IC_wciclr_disable 0x0 328# define IC_wciclr_enable 0x100 329 330# define IE_softrapien_MASK 0xfffffffe /* bit 0 */ 331# define IE_softrapien_disable 0x0 332# define IE_softrapien_enable 0x1 333# define IE_pickien_MASK 0xfffffffb /* bit 2 */ 334# define IE_pickien_disable 0x0 335# define IE_pickien_enable 0x4 336# define IE_vlineien_MASK 0xffffffdf /* bit 5 */ 337# define IE_vlineien_disable 0x0 338# define IE_vlineien_enable 0x20 339# define IE_extien_MASK 0xffffffbf /* bit 6 */ 340# define IE_extien_disable 0x0 341# define IE_extien_enable 0x40 342# define IE_wien_MASK 0xffffff7f /* bit 7 */ 343# define IE_wien_disable 0x0 344# define IE_wien_enable 0x80 345# define IE_wcien_MASK 0xfffffeff /* bit 8 */ 346# define IE_wcien_disable 0x0 347# define IE_wcien_enable 0x100 348 349# define MA_pwidth_MASK 0xfffffffc /* bits 0-1 */ 350# define MA_pwidth_8 0x0 /* val 0, shift 0 */ 351# define MA_pwidth_16 0x1 /* val 1, shift 0 */ 352# define MA_pwidth_32 0x2 /* val 2, shift 0 */ 353# define MA_pwidth_24 0x3 /* val 3, shift 0 */ 354# define MA_zwidth_MASK 0xffffffe7 /* bits 3-4 */ 355# define MA_zwidth_16 0x0 /* val 0, shift 3 */ 356# define MA_zwidth_32 0x8 /* val 1, shift 3 */ 357# define MA_zwidth_15 0x10 /* val 2, shift 3 */ 358# define MA_zwidth_24 0x18 /* val 3, shift 3 */ 359# define MA_memreset_MASK 0xffff7fff /* bit 15 */ 360# define MA_memreset_disable 0x0 361# define MA_memreset_enable 0x8000 362# define MA_fogen_MASK 0xfbffffff /* bit 26 */ 363# define MA_fogen_disable 0x0 364# define MA_fogen_enable 0x4000000 365# define MA_tlutload_MASK 0xdfffffff /* bit 29 */ 366# define MA_tlutload_disable 0x0 367# define MA_tlutload_enable 0x20000000 368# define MA_nodither_MASK 0xbfffffff /* bit 30 */ 369# define MA_nodither_disable 0x0 370# define MA_nodither_enable 0x40000000 371# define MA_dit555_MASK 0x7fffffff /* bit 31 */ 372# define MA_dit555_disable 0x0 373# define MA_dit555_enable 0x80000000 374 375# define MCWS_casltncy_MASK 0xfffffff8 /* bits 0-2 */ 376# define MCWS_casltncy_SHIFT 0 377# define MCWS_rrddelay_MASK 0xffffffcf /* bits 4-5 */ 378# define MCWS_rcddelay_MASK 0xfffffe7f /* bits 7-8 */ 379# define MCWS_rasmin_MASK 0xffffe3ff /* bits 10-12 */ 380# define MCWS_rasmin_SHIFT 10 381# define MCWS_rpdelay_MASK 0xffff3fff /* bits 14-15 */ 382# define MCWS_wrdelay_MASK 0xfff3ffff /* bits 18-19 */ 383# define MCWS_rddelay_MASK 0xffdfffff /* bit 21 */ 384# define MCWS_rddelay_disable 0x0 385# define MCWS_rddelay_enable 0x200000 386# define MCWS_smrdelay_MASK 0xfe7fffff /* bits 23-24 */ 387# define MCWS_bwcdelay_MASK 0xf3ffffff /* bits 26-27 */ 388# define MCWS_bpldelay_MASK 0x1fffffff /* bits 29-31 */ 389# define MCWS_bpldelay_SHIFT 29 390 391# define MRB_mclkbrd0_MASK 0xfffffff0 /* bits 0-3 */ 392# define MRB_mclkbrd0_SHIFT 0 393# define MRB_mclkbrd1_MASK 0xfffffe1f /* bits 5-8 */ 394# define MRB_mclkbrd1_SHIFT 5 395# define MRB_strmfctl_MASK 0xff3fffff /* bits 22-23 */ 396# define MRB_mrsopcod_MASK 0xe1ffffff /* bits 25-28 */ 397# define MRB_mrsopcod_SHIFT 25 398 399# define OM_dmamod_MASK 0xfffffff3 /* bits 2-3 */ 400# define OM_dmamod_general 0x0 /* val 0, shift 2 */ 401# define OM_dmamod_blit 0x4 /* val 1, shift 2 */ 402# define OM_dmamod_vector 0x8 /* val 2, shift 2 */ 403# define OM_dmamod_vertex 0xc /* val 3, shift 2 */ 404# define OM_dmadatasiz_MASK 0xfffffcff /* bits 8-9 */ 405# define OM_dmadatasiz_8 0x0 /* val 0, shift 8 */ 406# define OM_dmadatasiz_16 0x100 /* val 1, shift 8 */ 407# define OM_dmadatasiz_32 0x200 /* val 2, shift 8 */ 408# define OM_dirdatasiz_MASK 0xfffcffff /* bits 16-17 */ 409# define OM_dirdatasiz_8 0x0 /* val 0, shift 16 */ 410# define OM_dirdatasiz_16 0x10000 /* val 1, shift 16 */ 411# define OM_dirdatasiz_32 0x20000 /* val 2, shift 16 */ 412 413# define P_iy_MASK 0xffffe000 /* bits 0-12 */ 414# define P_iy_SHIFT 0 415# define P_ylin_MASK 0xffff7fff /* bit 15 */ 416# define P_ylin_disable 0x0 417# define P_ylin_enable 0x8000 418 419# define PDCA_primod_MASK 0xfffffffc /* bits 0-1 */ 420# define PDCA_primod_general 0x0 /* val 0, shift 0 */ 421# define PDCA_primod_blit 0x1 /* val 1, shift 0 */ 422# define PDCA_primod_vector 0x2 /* val 2, shift 0 */ 423# define PDCA_primod_vertex 0x3 /* val 3, shift 0 */ 424# define PDCA_primaddress_MASK 0x3 /* bits 2-31 */ 425# define PDCA_primaddress_SHIFT 2 426 427# define PDEA_primnostart_MASK 0xfffffffe /* bit 0 */ 428# define PDEA_primnostart_disable 0x0 429# define PDEA_primnostart_enable 0x1 430# define PDEA_pagpxfer_MASK 0xfffffffd /* bit 1 */ 431# define PDEA_pagpxfer_disable 0x0 432# define PDEA_pagpxfer_enable 0x2 433# define PDEA_primend_MASK 0x3 /* bits 2-31 */ 434# define PDEA_primend_SHIFT 2 435 436# define PLS_primptren0_MASK 0xfffffffe /* bit 0 */ 437# define PLS_primptren0_disable 0x0 438# define PLS_primptren0_enable 0x1 439# define PLS_primptren1_MASK 0xfffffffd /* bit 1 */ 440# define PLS_primptren1_disable 0x0 441# define PLS_primptren1_enable 0x2 442# define PLS_primptr_MASK 0x7 /* bits 3-31 */ 443# define PLS_primptr_SHIFT 3 444 445# define R_softreset_MASK 0xfffffffe /* bit 0 */ 446# define R_softreset_disable 0x0 447# define R_softreset_enable 0x1 448# define R_softextrst_MASK 0xfffffffd /* bit 1 */ 449# define R_softextrst_disable 0x0 450# define R_softextrst_enable 0x2 451 452# define SDCA_secmod_MASK 0xfffffffc /* bits 0-1 */ 453# define SDCA_secmod_general 0x0 /* val 0, shift 0 */ 454# define SDCA_secmod_blit 0x1 /* val 1, shift 0 */ 455# define SDCA_secmod_vector 0x2 /* val 2, shift 0 */ 456# define SDCA_secmod_vertex 0x3 /* val 3, shift 0 */ 457# define SDCA_secaddress_MASK 0x3 /* bits 2-31 */ 458# define SDCA_secaddress_SHIFT 2 459 460# define SDEA_sagpxfer_MASK 0xfffffffd /* bit 1 */ 461# define SDEA_sagpxfer_disable 0x0 462# define SDEA_sagpxfer_enable 0x2 463# define SDEA_secend_MASK 0x3 /* bits 2-31 */ 464# define SDEA_secend_SHIFT 2 465 466# define SETDCA_setupmod_MASK 0xfffffffc /* bits 0-1 */ 467# define SETDCA_setupmod_vertlist 0x0 /* val 0, shift 0 */ 468# define SETDCA_setupaddress_MASK 0x3 /* bits 2-31 */ 469# define SETDCA_setupaddress_SHIFT 2 470 471# define SETDEA_setupagpxfer_MASK 0xfffffffd /* bit 1 */ 472# define SETDEA_setupagpxfer_disable 0x0 473# define SETDEA_setupagpxfer_enable 0x2 474# define SETDEA_setupend_MASK 0x3 /* bits 2-31 */ 475# define SETDEA_setupend_SHIFT 2 476 477# define S_sdydxl_MASK 0xfffffffe /* bit 0 */ 478# define S_sdydxl_y 0x0 479# define S_sdydxl_x 0x1 480# define S_scanleft_MASK 0xfffffffe /* bit 0 */ 481# define S_scanleft_disable 0x0 482# define S_scanleft_enable 0x1 483# define S_sdxl_MASK 0xfffffffd /* bit 1 */ 484# define S_sdxl_pos 0x0 485# define S_sdxl_neg 0x2 486# define S_sdy_MASK 0xfffffffb /* bit 2 */ 487# define S_sdy_pos 0x0 488# define S_sdy_neg 0x4 489# define S_sdxr_MASK 0xffffffdf /* bit 5 */ 490# define S_sdxr_pos 0x0 491# define S_sdxr_neg 0x20 492# define S_brkleft_MASK 0xfffffeff /* bit 8 */ 493# define S_brkleft_disable 0x0 494# define S_brkleft_enable 0x100 495# define S_errorinit_MASK 0x7fffffff /* bit 31 */ 496# define S_errorinit_disable 0x0 497# define S_errorinit_enable 0x80000000 498 499# define FSC_x_off_MASK 0xfffffff0 /* bits 0-3 */ 500# define FSC_x_off_SHIFT 0 501# define FSC_funcnt_MASK 0xffffff80 /* bits 0-6 */ 502# define FSC_funcnt_SHIFT 0 503# define FSC_y_off_MASK 0xffffff8f /* bits 4-6 */ 504# define FSC_y_off_SHIFT 4 505# define FSC_funoff_MASK 0xffc0ffff /* bits 16-21 */ 506# define FSC_funoff_SHIFT 16 507# define FSC_stylelen_MASK 0xffc0ffff /* bits 16-21 */ 508# define FSC_stylelen_SHIFT 16 509 510 511# define STH_softraphand_MASK 0x3 /* bits 2-31 */ 512# define STH_softraphand_SHIFT 2 513 514# define SO_srcmap_MASK 0xfffffffe /* bit 0 */ 515# define SO_srcmap_fb 0x0 516# define SO_srcmap_sys 0x1 517# define SO_srcacc_MASK 0xfffffffd /* bit 1 */ 518# define SO_srcacc_pci 0x0 519# define SO_srcacc_agp 0x2 520# define SO_srcorg_MASK 0x7 /* bits 3-31 */ 521# define SO_srcorg_SHIFT 3 522 523# define STAT_softrapen_MASK 0xfffffffe /* bit 0 */ 524# define STAT_softrapen_disable 0x0 525# define STAT_softrapen_enable 0x1 526# define STAT_pickpen_MASK 0xfffffffb /* bit 2 */ 527# define STAT_pickpen_disable 0x0 528# define STAT_pickpen_enable 0x4 529# define STAT_vsyncsts_MASK 0xfffffff7 /* bit 3 */ 530# define STAT_vsyncsts_disable 0x0 531# define STAT_vsyncsts_enable 0x8 532# define STAT_vsyncpen_MASK 0xffffffef /* bit 4 */ 533# define STAT_vsyncpen_disable 0x0 534# define STAT_vsyncpen_enable 0x10 535# define STAT_vlinepen_MASK 0xffffffdf /* bit 5 */ 536# define STAT_vlinepen_disable 0x0 537# define STAT_vlinepen_enable 0x20 538# define STAT_extpen_MASK 0xffffffbf /* bit 6 */ 539# define STAT_extpen_disable 0x0 540# define STAT_extpen_enable 0x40 541# define STAT_wpen_MASK 0xffffff7f /* bit 7 */ 542# define STAT_wpen_disable 0x0 543# define STAT_wpen_enable 0x80 544# define STAT_wcpen_MASK 0xfffffeff /* bit 8 */ 545# define STAT_wcpen_disable 0x0 546# define STAT_wcpen_enable 0x100 547# define STAT_dwgengsts_MASK 0xfffeffff /* bit 16 */ 548# define STAT_dwgengsts_disable 0x0 549# define STAT_dwgengsts_enable 0x10000 550# define STAT_endprdmasts_MASK 0xfffdffff /* bit 17 */ 551# define STAT_endprdmasts_disable 0x0 552# define STAT_endprdmasts_enable 0x20000 553# define STAT_wbusy_MASK 0xfffbffff /* bit 18 */ 554# define STAT_wbusy_disable 0x0 555# define STAT_wbusy_enable 0x40000 556# define STAT_swflag_MASK 0xfffffff /* bits 28-31 */ 557# define STAT_swflag_SHIFT 28 558 559# define S_sref_MASK 0xffffff00 /* bits 0-7 */ 560# define S_sref_SHIFT 0 561# define S_smsk_MASK 0xffff00ff /* bits 8-15 */ 562# define S_smsk_SHIFT 8 563# define S_swtmsk_MASK 0xff00ffff /* bits 16-23 */ 564# define S_swtmsk_SHIFT 16 565 566# define SC_smode_MASK 0xfffffff8 /* bits 0-2 */ 567# define SC_smode_salways 0x0 /* val 0, shift 0 */ 568# define SC_smode_snever 0x1 /* val 1, shift 0 */ 569# define SC_smode_se 0x2 /* val 2, shift 0 */ 570# define SC_smode_sne 0x3 /* val 3, shift 0 */ 571# define SC_smode_slt 0x4 /* val 4, shift 0 */ 572# define SC_smode_slte 0x5 /* val 5, shift 0 */ 573# define SC_smode_sgt 0x6 /* val 6, shift 0 */ 574# define SC_smode_sgte 0x7 /* val 7, shift 0 */ 575# define SC_sfailop_MASK 0xffffffc7 /* bits 3-5 */ 576# define SC_sfailop_keep 0x0 /* val 0, shift 3 */ 577# define SC_sfailop_zero 0x8 /* val 1, shift 3 */ 578# define SC_sfailop_replace 0x10 /* val 2, shift 3 */ 579# define SC_sfailop_incrsat 0x18 /* val 3, shift 3 */ 580# define SC_sfailop_decrsat 0x20 /* val 4, shift 3 */ 581# define SC_sfailop_invert 0x28 /* val 5, shift 3 */ 582# define SC_sfailop_incr 0x30 /* val 6, shift 3 */ 583# define SC_sfailop_decr 0x38 /* val 7, shift 3 */ 584# define SC_szfailop_MASK 0xfffffe3f /* bits 6-8 */ 585# define SC_szfailop_keep 0x0 /* val 0, shift 6 */ 586# define SC_szfailop_zero 0x40 /* val 1, shift 6 */ 587# define SC_szfailop_replace 0x80 /* val 2, shift 6 */ 588# define SC_szfailop_incrsat 0xc0 /* val 3, shift 6 */ 589# define SC_szfailop_decrsat 0x100 /* val 4, shift 6 */ 590# define SC_szfailop_invert 0x140 /* val 5, shift 6 */ 591# define SC_szfailop_incr 0x180 /* val 6, shift 6 */ 592# define SC_szfailop_decr 0x1c0 /* val 7, shift 6 */ 593# define SC_szpassop_MASK 0xfffff1ff /* bits 9-11 */ 594# define SC_szpassop_keep 0x0 /* val 0, shift 9 */ 595# define SC_szpassop_zero 0x200 /* val 1, shift 9 */ 596# define SC_szpassop_replace 0x400 /* val 2, shift 9 */ 597# define SC_szpassop_incrsat 0x600 /* val 3, shift 9 */ 598# define SC_szpassop_decrsat 0x800 /* val 4, shift 9 */ 599# define SC_szpassop_invert 0xa00 /* val 5, shift 9 */ 600# define SC_szpassop_incr 0xc00 /* val 6, shift 9 */ 601# define SC_szpassop_decr 0xe00 /* val 7, shift 9 */ 602 603# define TD1_color1arg2selMASK 0xfffffffc /* bits 0-1 */ 604# define TD1_color1alphaselMASK 0xffffffe3 /* bits 2-4 */ 605# define TD1_color1alphaselSHIFT 2 606# define TD1_color1arg1alphaMASK 0xffffffdf /* bit 5 */ 607# define TD1_color1arg1alphadisable 0x0 608# define TD1_color1arg1alphaenable 0x20 609# define TD1_color1arg1invMASK 0xffffffbf /* bit 6 */ 610# define TD1_color1arg1invdisable 0x0 611# define TD1_color1arg1invenable 0x40 612# define TD1_color1arg2alphaMASK 0xffffff7f /* bit 7 */ 613# define TD1_color1arg2alphadisable 0x0 614# define TD1_color1arg2alphaenable 0x80 615# define TD1_color1arg2invMASK 0xfffffeff /* bit 8 */ 616# define TD1_color1arg2invdisable 0x0 617# define TD1_color1arg2invenable 0x100 618# define TD1_color1alpha1invMASK 0xfffffdff /* bit 9 */ 619# define TD1_color1alpha1invdisable 0x0 620# define TD1_color1alpha1invenable 0x200 621# define TD1_color1alpha2invMASK 0xfffffbff /* bit 10 */ 622# define TD1_color1alpha2invdisable 0x0 623# define TD1_color1alpha2invenable 0x400 624# define TD1_color1selMASK 0xff9fffff /* bits 21-22 */ 625# define TD1_color1selarg1 0x0 /* val 0, shift 21 */ 626# define TD1_color1selarg2 0x200000 /* val 1, shift 21 */ 627# define TD1_color1seladd 0x400000 /* val 2, shift 21 */ 628# define TD1_color1selmul 0x600000 /* val 3, shift 21 */ 629# define TD1_alpha1selMASK 0x3fffffff /* bits 30-31 */ 630# define TD1_alpha1selarg1 0x0 /* val 0, shift 30 */ 631# define TD1_alpha1selarg2 0x40000000 /* val 1, shift 30 */ 632# define TD1_alpha1seladd 0x80000000 /* val 2, shift 30 */ 633# define TD1_alpha1selmul 0xc0000000 /* val 3, shift 30 */ 634 635# define TST_ramtsten_MASK 0xfffffffe /* bit 0 */ 636# define TST_ramtsten_disable 0x0 637# define TST_ramtsten_enable 0x1 638# define TST_ramtstdone_MASK 0xfffffffd /* bit 1 */ 639# define TST_ramtstdone_disable 0x0 640# define TST_ramtstdone_enable 0x2 641# define TST_wramtstpass_MASK 0xfffffffb /* bit 2 */ 642# define TST_wramtstpass_disable 0x0 643# define TST_wramtstpass_enable 0x4 644# define TST_tcachetstpass_MASK 0xfffffff7 /* bit 3 */ 645# define TST_tcachetstpass_disable 0x0 646# define TST_tcachetstpass_enable 0x8 647# define TST_tluttstpass_MASK 0xffffffef /* bit 4 */ 648# define TST_tluttstpass_disable 0x0 649# define TST_tluttstpass_enable 0x10 650# define TST_luttstpass_MASK 0xffffffdf /* bit 5 */ 651# define TST_luttstpass_disable 0x0 652# define TST_luttstpass_enable 0x20 653# define TST_besramtstpass_MASK 0xffffffbf /* bit 6 */ 654# define TST_besramtstpass_disable 0x0 655# define TST_besramtstpass_enable 0x40 656# define TST_ringen_MASK 0xfffffeff /* bit 8 */ 657# define TST_ringen_disable 0x0 658# define TST_ringen_enable 0x100 659# define TST_apllbyp_MASK 0xfffffdff /* bit 9 */ 660# define TST_apllbyp_disable 0x0 661# define TST_apllbyp_enable 0x200 662# define TST_hiten_MASK 0xfffffbff /* bit 10 */ 663# define TST_hiten_disable 0x0 664# define TST_hiten_enable 0x400 665# define TST_tmode_MASK 0xffffc7ff /* bits 11-13 */ 666# define TST_tmode_SHIFT 11 667# define TST_tclksel_MASK 0xfffe3fff /* bits 14-16 */ 668# define TST_tclksel_SHIFT 14 669# define TST_ringcnten_MASK 0xfffdffff /* bit 17 */ 670# define TST_ringcnten_disable 0x0 671# define TST_ringcnten_enable 0x20000 672# define TST_ringcnt_MASK 0xc003ffff /* bits 18-29 */ 673# define TST_ringcnt_SHIFT 18 674# define TST_ringcntclksl_MASK 0xbfffffff /* bit 30 */ 675# define TST_ringcntclksl_disable 0x0 676# define TST_ringcntclksl_enable 0x40000000 677# define TST_biosboot_MASK 0x7fffffff /* bit 31 */ 678# define TST_biosboot_disable 0x0 679# define TST_biosboot_enable 0x80000000 680 681# define TMC_tformat_MASK 0xfffffff0 /* bits 0-3 */ 682# define TMC_tformat_tw4 0x0 /* val 0, shift 0 */ 683# define TMC_tformat_tw8 0x1 /* val 1, shift 0 */ 684# define TMC_tformat_tw15 0x2 /* val 2, shift 0 */ 685# define TMC_tformat_tw16 0x3 /* val 3, shift 0 */ 686# define TMC_tformat_tw12 0x4 /* val 4, shift 0 */ 687# define TMC_tformat_tw32 0x6 /* val 6, shift 0 */ 688# define TMC_tformat_tw422 0xa /* val 10, shift 0 */ 689# define TMC_tpitchlin_MASK 0xfffffeff /* bit 8 */ 690# define TMC_tpitchlin_disable 0x0 691# define TMC_tpitchlin_enable 0x100 692# define TMC_tpitchext_MASK 0xfff001ff /* bits 9-19 */ 693# define TMC_tpitchext_SHIFT 9 694# define TMC_tpitch_MASK 0xfff8ffff /* bits 16-18 */ 695# define TMC_tpitch_SHIFT 16 696# define TMC_owalpha_MASK 0xffbfffff /* bit 22 */ 697# define TMC_owalpha_disable 0x0 698# define TMC_owalpha_enable 0x400000 699# define TMC_azeroextend_MASK 0xff7fffff /* bit 23 */ 700# define TMC_azeroextend_disable 0x0 701# define TMC_azeroextend_enable 0x800000 702# define TMC_decalckey_MASK 0xfeffffff /* bit 24 */ 703# define TMC_decalckey_disable 0x0 704# define TMC_decalckey_enable 0x1000000 705# define TMC_takey_MASK 0xfdffffff /* bit 25 */ 706# define TMC_takey_0 0x0 707# define TMC_takey_1 0x2000000 708# define TMC_tamask_MASK 0xfbffffff /* bit 26 */ 709# define TMC_tamask_0 0x0 710# define TMC_tamask_1 0x4000000 711# define TMC_clampv_MASK 0xf7ffffff /* bit 27 */ 712# define TMC_clampv_disable 0x0 713# define TMC_clampv_enable 0x8000000 714# define TMC_clampu_MASK 0xefffffff /* bit 28 */ 715# define TMC_clampu_disable 0x0 716# define TMC_clampu_enable 0x10000000 717# define TMC_tmodulate_MASK 0xdfffffff /* bit 29 */ 718# define TMC_tmodulate_disable 0x0 719# define TMC_tmodulate_enable 0x20000000 720# define TMC_strans_MASK 0xbfffffff /* bit 30 */ 721# define TMC_strans_disable 0x0 722# define TMC_strans_enable 0x40000000 723# define TMC_itrans_MASK 0x7fffffff /* bit 31 */ 724# define TMC_itrans_disable 0x0 725# define TMC_itrans_enable 0x80000000 726 727# define TMC_decalblend_MASK 0xfffffffe /* bit 0 */ 728# define TMC_decalblend_disable 0x0 729# define TMC_decalblend_enable 0x1 730# define TMC_idecal_MASK 0xfffffffd /* bit 1 */ 731# define TMC_idecal_disable 0x0 732# define TMC_idecal_enable 0x2 733# define TMC_decaldis_MASK 0xfffffffb /* bit 2 */ 734# define TMC_decaldis_disable 0x0 735# define TMC_decaldis_enable 0x4 736# define TMC_ckstransdis_MASK 0xffffffef /* bit 4 */ 737# define TMC_ckstransdis_disable 0x0 738# define TMC_ckstransdis_enable 0x10 739# define TMC_borderen_MASK 0xffffffdf /* bit 5 */ 740# define TMC_borderen_disable 0x0 741# define TMC_borderen_enable 0x20 742# define TMC_specen_MASK 0xffffffbf /* bit 6 */ 743# define TMC_specen_disable 0x0 744# define TMC_specen_enable 0x40 745 746# define TF_minfilter_MASK 0xfffffff0 /* bits 0-3 */ 747# define TF_minfilter_nrst 0x0 /* val 0, shift 0 */ 748# define TF_minfilter_bilin 0x2 /* val 2, shift 0 */ 749# define TF_minfilter_cnst 0x3 /* val 3, shift 0 */ 750# define TF_minfilter_mm1s 0x8 /* val 8, shift 0 */ 751# define TF_minfilter_mm2s 0x9 /* val 9, shift 0 */ 752# define TF_minfilter_mm4s 0xa /* val 10, shift 0 */ 753# define TF_minfilter_mm8s 0xc /* val 12, shift 0 */ 754# define TF_magfilter_MASK 0xffffff0f /* bits 4-7 */ 755# define TF_magfilter_nrst 0x0 /* val 0, shift 4 */ 756# define TF_magfilter_bilin 0x20 /* val 2, shift 4 */ 757# define TF_magfilter_cnst 0x30 /* val 3, shift 4 */ 758# define TF_avgstride_MASK 0xfff7ffff /* bit 19 */ 759# define TF_avgstride_disable 0x0 760# define TF_avgstride_enable 0x80000 761# define TF_filteralpha_MASK 0xffefffff /* bit 20 */ 762# define TF_filteralpha_disable 0x0 763# define TF_filteralpha_enable 0x100000 764# define TF_fthres_MASK 0xe01fffff /* bits 21-28 */ 765# define TF_fthres_SHIFT 21 766# define TF_mapnb_MASK 0x1fffffff /* bits 29-31 */ 767# define TF_mapnb_SHIFT 29 768 769# define TH_th_MASK 0xffffffc0 /* bits 0-5 */ 770# define TH_th_SHIFT 0 771# define TH_rfh_MASK 0xffff81ff /* bits 9-14 */ 772# define TH_rfh_SHIFT 9 773# define TH_thmask_MASK 0xe003ffff /* bits 18-28 */ 774# define TH_thmask_SHIFT 18 775 776# define TO_texorgmap_MASK 0xfffffffe /* bit 0 */ 777# define TO_texorgmap_fb 0x0 778# define TO_texorgmap_sys 0x1 779# define TO_texorgacc_MASK 0xfffffffd /* bit 1 */ 780# define TO_texorgacc_pci 0x0 781# define TO_texorgacc_agp 0x2 782# define TO_texorg_MASK 0x1f /* bits 5-31 */ 783# define TO_texorg_SHIFT 5 784 785# define TT_tckey_MASK 0xffff0000 /* bits 0-15 */ 786# define TT_tckey_SHIFT 0 787# define TT_tkmask_MASK 0xffff /* bits 16-31 */ 788# define TT_tkmask_SHIFT 16 789 790# define TT_tckeyh_MASK 0xffff0000 /* bits 0-15 */ 791# define TT_tckeyh_SHIFT 0 792# define TT_tkmaskh_MASK 0xffff /* bits 16-31 */ 793# define TT_tkmaskh_SHIFT 16 794 795# define TW_tw_MASK 0xffffffc0 /* bits 0-5 */ 796# define TW_tw_SHIFT 0 797# define TW_rfw_MASK 0xffff81ff /* bits 9-14 */ 798# define TW_rfw_SHIFT 9 799# define TW_twmask_MASK 0xe003ffff /* bits 18-28 */ 800# define TW_twmask_SHIFT 18 801 802# define WAS_seqdst0_MASK 0xffffffc0 /* bits 0-5 */ 803# define WAS_seqdst0_SHIFT 0 804# define WAS_seqdst1_MASK 0xfffff03f /* bits 6-11 */ 805# define WAS_seqdst1_SHIFT 6 806# define WAS_seqdst2_MASK 0xfffc0fff /* bits 12-17 */ 807# define WAS_seqdst2_SHIFT 12 808# define WAS_seqdst3_MASK 0xff03ffff /* bits 18-23 */ 809# define WAS_seqdst3_SHIFT 18 810# define WAS_seqlen_MASK 0xfcffffff /* bits 24-25 */ 811# define WAS_wfirsttag_MASK 0xfbffffff /* bit 26 */ 812# define WAS_wfirsttag_disable 0x0 813# define WAS_wfirsttag_enable 0x4000000 814# define WAS_wsametag_MASK 0xf7ffffff /* bit 27 */ 815# define WAS_wsametag_disable 0x0 816# define WAS_wsametag_enable 0x8000000 817# define WAS_seqoff_MASK 0xefffffff /* bit 28 */ 818# define WAS_seqoff_disable 0x0 819# define WAS_seqoff_enable 0x10000000 820 821# define WMA_wcodeaddr_MASK 0xff /* bits 8-31 */ 822# define WMA_wcodeaddr_SHIFT 8 823 824# define WF_walustsflag_MASK 0xffffff00 /* bits 0-7 */ 825# define WF_walustsflag_SHIFT 0 826# define WF_walucfgflag_MASK 0xffff00ff /* bits 8-15 */ 827# define WF_walucfgflag_SHIFT 8 828# define WF_wprgflag_MASK 0xffff /* bits 16-31 */ 829# define WF_wprgflag_SHIFT 16 830 831# define WF1_walustsflag1_MASK 0xffffff00 /* bits 0-7 */ 832# define WF1_walustsflag1_SHIFT 0 833# define WF1_walucfgflag1_MASK 0xffff00ff /* bits 8-15 */ 834# define WF1_walucfgflag1_SHIFT 8 835# define WF1_wprgflag1_MASK 0xffff /* bits 16-31 */ 836# define WF1_wprgflag1_SHIFT 16 837 838# define WGV_wgetmsbmin_MASK 0xffffffe0 /* bits 0-4 */ 839# define WGV_wgetmsbmin_SHIFT 0 840# define WGV_wgetmsbmax_MASK 0xffffe0ff /* bits 8-12 */ 841# define WGV_wgetmsbmax_SHIFT 8 842# define WGV_wbrklefttop_MASK 0xfffeffff /* bit 16 */ 843# define WGV_wbrklefttop_disable 0x0 844# define WGV_wbrklefttop_enable 0x10000 845# define WGV_wfastcrop_MASK 0xfffdffff /* bit 17 */ 846# define WGV_wfastcrop_disable 0x0 847# define WGV_wfastcrop_enable 0x20000 848# define WGV_wcentersnap_MASK 0xfffbffff /* bit 18 */ 849# define WGV_wcentersnap_disable 0x0 850# define WGV_wcentersnap_enable 0x40000 851# define WGV_wbrkrighttop_MASK 0xfff7ffff /* bit 19 */ 852# define WGV_wbrkrighttop_disable 0x0 853# define WGV_wbrkrighttop_enable 0x80000 854 855# define WIA_wmode_MASK 0xfffffffc /* bits 0-1 */ 856# define WIA_wmode_suspend 0x0 /* val 0, shift 0 */ 857# define WIA_wmode_resume 0x1 /* val 1, shift 0 */ 858# define WIA_wmode_jump 0x2 /* val 2, shift 0 */ 859# define WIA_wmode_start 0x3 /* val 3, shift 0 */ 860# define WIA_wagp_MASK 0xfffffffb /* bit 2 */ 861# define WIA_wagp_pci 0x0 862# define WIA_wagp_agp 0x4 863# define WIA_wiaddr_MASK 0x7 /* bits 3-31 */ 864# define WIA_wiaddr_SHIFT 3 865 866# define WIA2_wmode_MASK 0xfffffffc /* bits 0-1 */ 867# define WIA2_wmode_suspend 0x0 /* val 0, shift 0 */ 868# define WIA2_wmode_resume 0x1 /* val 1, shift 0 */ 869# define WIA2_wmode_jump 0x2 /* val 2, shift 0 */ 870# define WIA2_wmode_start 0x3 /* val 3, shift 0 */ 871# define WIA2_wagp_MASK 0xfffffffb /* bit 2 */ 872# define WIA2_wagp_pci 0x0 873# define WIA2_wagp_agp 0x4 874# define WIA2_wiaddr_MASK 0x7 /* bits 3-31 */ 875# define WIA2_wiaddr_SHIFT 3 876 877# define WIMA_wimemaddr_MASK 0xffffff00 /* bits 0-7 */ 878# define WIMA_wimemaddr_SHIFT 0 879 880# define WM_wucodecache_MASK 0xfffffffe /* bit 0 */ 881# define WM_wucodecache_disable 0x0 882# define WM_wucodecache_enable 0x1 883# define WM_wmaster_MASK 0xfffffffd /* bit 1 */ 884# define WM_wmaster_disable 0x0 885# define WM_wmaster_enable 0x2 886# define WM_wcacheflush_MASK 0xfffffff7 /* bit 3 */ 887# define WM_wcacheflush_disable 0x0 888# define WM_wcacheflush_enable 0x8 889 890# define WVS_wvrtxsz_MASK 0xffffffc0 /* bits 0-5 */ 891# define WVS_wvrtxsz_SHIFT 0 892# define WVS_primsz_MASK 0xffffc0ff /* bits 8-13 */ 893# define WVS_primsz_SHIFT 8 894 895# define XYEA_x_end_MASK 0xffff0000 /* bits 0-15 */ 896# define XYEA_x_end_SHIFT 0 897# define XYEA_y_end_MASK 0xffff /* bits 16-31 */ 898# define XYEA_y_end_SHIFT 16 899 900# define XYSA_x_start_MASK 0xffff0000 /* bits 0-15 */ 901# define XYSA_x_start_SHIFT 0 902# define XYSA_y_start_MASK 0xffff /* bits 16-31 */ 903# define XYSA_y_start_SHIFT 16 904 905# define YA_ydst_MASK 0xff800000 /* bits 0-22 */ 906# define YA_ydst_SHIFT 0 907# define YA_sellin_MASK 0x1fffffff /* bits 29-31 */ 908# define YA_sellin_SHIFT 29 909 910# define YDL_length_MASK 0xffff0000 /* bits 0-15 */ 911# define YDL_length_SHIFT 0 912# define YDL_yval_MASK 0xffff /* bits 16-31 */ 913# define YDL_yval_SHIFT 16 914 915# define ZO_zorgmap_MASK 0xfffffffe /* bit 0 */ 916# define ZO_zorgmap_fb 0x0 917# define ZO_zorgmap_sys 0x1 918# define ZO_zorgacc_MASK 0xfffffffd /* bit 1 */ 919# define ZO_zorgacc_pci 0x0 920# define ZO_zorgacc_agp 0x2 921# define ZO_zorg_MASK 0x3 /* bits 2-31 */ 922# define ZO_zorg_SHIFT 2 923 924 925 926 927/**************** (END) AUTOMATICALLY GENERATED REGISTER FILE ****************/ 928 929#endif /* _MGAREGS_H_ */ 930 931