1/*
2 * Copyright (c) 1993-2003 NVIDIA, Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sublicense, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef __NV_LOCAL_H__
25#define __NV_LOCAL_H__
26
27/*
28 * This file includes any environment or machine specific values to access the
29 * HW.  Put all affected includes, typdefs, etc. here so the riva_hw.* files
30 * can stay generic in nature.
31 */
32#include "compiler.h"
33#include "xf86_OSproc.h"
34
35#include "shadow.h"
36/*
37 * Typedefs to force certain sized values.
38 */
39typedef unsigned char  U008;
40typedef unsigned short U016;
41typedef unsigned int   U032;
42
43/*
44 * HW access macros.  These assume memory-mapped I/O, and not normal I/O space.
45 */
46#define NV_WR08(p,i,d)  MMIO_OUT8((pointer)(p), (i), (d))
47#define NV_RD08(p,i)    MMIO_IN8((pointer)(p), (i))
48#define NV_WR16(p,i,d)  MMIO_OUT16((pointer)(p), (i), (d))
49#define NV_RD16(p,i)    MMIO_IN16((pointer)(p), (i))
50#define NV_WR32(p,i,d)  MMIO_OUT32((pointer)(p), (i), (d))
51#define NV_RD32(p,i)    MMIO_IN32((pointer)(p), (i))
52
53/* VGA I/O is now always done through MMIO */
54#define VGA_WR08(p,i,d) NV_WR08(p,i,d)
55#define VGA_RD08(p,i)   NV_RD08(p,i)
56
57#if defined(__i386__)
58#define _NV_FENCE() outb(0x3D0, 0);
59#elif defined(__powerpc__)
60#define _NV_FENCE() __asm("eieio; sync;" ::: "memory");
61#else
62#define _NV_FENCE() mem_barrier();
63#endif
64
65#define NVDmaNext(pNv, data) { \
66     (pNv)->dmaBase[(pNv)->dmaCurrent++] = (data); \
67     _NV_FENCE() }
68
69#define NVDmaStart(pNv, tag, size) {          \
70     if((pNv)->dmaFree <= (size))             \
71        NVDmaWait(pNv, size);                 \
72     NVDmaNext(pNv, ((size) << 18) | (tag));  \
73     (pNv)->dmaFree -= ((size) + 1);          \
74}
75
76#define WRITE_PUT(pNv, data) {       \
77  volatile CARD8 scratch;            \
78  _NV_FENCE()                        \
79  scratch = (pNv)->FbStart[0];       \
80  _NV_FENCE()			     \
81  (pNv)->FIFO[0x0010] = (data) << 2; \
82  _NV_FENCE()			     \
83  mem_barrier();                     \
84}
85
86#define READ_GET(pNv) ((pNv)->FIFO[0x0011] >> 2)
87
88
89#endif /* __NV_LOCAL_H__ */
90