1a6b33934Smacallan/* 2a6b33934Smacallan * SBus Weitek P9100 framebuffer - hardware registers. 3a6b33934Smacallan * 4a6b33934Smacallan * Copyright (C) 2005 Michael Lorenz 5a6b33934Smacallan * 6a6b33934Smacallan * Permission is hereby granted, free of charge, to any person obtaining a copy 7a6b33934Smacallan * of this software and associated documentation files (the "Software"), to deal 8a6b33934Smacallan * in the Software without restriction, including without limitation the rights 9a6b33934Smacallan * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10a6b33934Smacallan * copies of the Software, and to permit persons to whom the Software is 11a6b33934Smacallan * furnished to do so, subject to the following conditions: 12a6b33934Smacallan * 13a6b33934Smacallan * The above copyright notice and this permission notice shall be included in 14a6b33934Smacallan * all copies or substantial portions of the Software. 15a6b33934Smacallan * 16a6b33934Smacallan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17a6b33934Smacallan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18a6b33934Smacallan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19a6b33934Smacallan * MICHAEL LORENZ BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20a6b33934Smacallan * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21a6b33934Smacallan * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22a6b33934Smacallan */ 23ae7dafb3Sjdc/* $NetBSD: pnozz_regs.h,v 1.2 2021/06/09 07:25:57 jdc Exp $ */ 24a6b33934Smacallan 25a6b33934Smacallan#ifndef PNOZZ_REGS_H 26a6b33934Smacallan#define PNOZZ_REGS_H 27a6b33934Smacallan 28a6b33934Smacallan/* The Tadpole 3GX Technical Reference Manual lies. The ramdac registers 29a6b33934Smacallan * are map in 4 byte increments, not 8. 30a6b33934Smacallan */ 31a6b33934Smacallan#define SCRN_RPNT_CTL_1 0x0138 /* Screen Repaint Timing Control 1 */ 32a6b33934Smacallan#define VIDEO_ENABLED 0x00000020 33a6b33934Smacallan#define PWRUP_CNFG 0x0194 /* Power Up Configuration */ 34a6b33934Smacallan#define DAC_CMAP_WRIDX 0x0200 /* IBM RGB528 Palette Address (Write) */ 35a6b33934Smacallan#define DAC_CMAP_DATA 0x0204 /* IBM RGB528 Palette Data */ 36a6b33934Smacallan#define DAC_PXL_MASK 0x0208 /* IBM RGB528 Pixel Mask */ 37a6b33934Smacallan#define DAC_CMAP_RDIDX 0x020c /* IBM RGB528 Palette Address (Read) */ 38a6b33934Smacallan#define DAC_INDX_LO 0x0210 /* IBM RGB528 Index Low */ 39a6b33934Smacallan#define DAC_INDX_HI 0x0214 /* IBM RGB528 Index High */ 40a6b33934Smacallan#define DAC_INDX_DATA 0x0218 /* IBM RGB528 Index Data (Indexed Registers) */ 41a6b33934Smacallan#define DAC_INDX_CTL 0x021c /* IBM RGB528 Index Control */ 42a6b33934Smacallan #define DAC_INDX_AUTOINCR 0x01 43a6b33934Smacallan 44a6b33934Smacallan/* RAMDAC control registers, accessed through DAC_INDX_* */ 45a6b33934Smacallan#define DAC_MISC_CLK 0x02 46a6b33934Smacallan#define DAC_POWER_MGT 0x05 47a6b33934Smacallan#define DAC_OPERATION 0x06 48a6b33934Smacallan #define DAC_SYNC_ON_GREEN 0x08 49a6b33934Smacallan#define DAC_PALETTE_CTRL 0x07 50a6b33934Smacallan#define DAC_PIXEL_FMT 0x0a 51a6b33934Smacallan#define DAC_8BIT_CTRL 0x0b 52a6b33934Smacallan #define DAC8_DIRECT_COLOR 0x01 53a6b33934Smacallan#define DAC_16BIT_CTRL 0x0c 54a6b33934Smacallan #define DAC16_INDIRECT_COLOR 0x00 55a6b33934Smacallan #define DAC16_DYNAMIC_COLOR 0x40 56a6b33934Smacallan #define DAC16_DIRECT_COLOR 0xc0 57a6b33934Smacallan #define DAC16_BYPASS_POLARITY 0x20 58a6b33934Smacallan #define DAC16_BIT_FILL_LINEAR 0x04 59a6b33934Smacallan #define DAC16_555 0x00 60a6b33934Smacallan #define DAC16_565 0x02 61a6b33934Smacallan #define DAC16_CONTIGUOUS 0x01 62a6b33934Smacallan#define DAC_24BIT_CTRL 0x0d 63a6b33934Smacallan #define DAC24_DIRECT_COLOR 0x01 64a6b33934Smacallan#define DAC_32BIT_CTRL 0x0e 65a6b33934Smacallan #define DAC32_BYPASS_POLARITY 0x04 66a6b33934Smacallan #define DAC32_INDIRECT_COLOR 0x00 67a6b33934Smacallan #define DAC32_DYNAMIC_COLOR 0x01 68a6b33934Smacallan #define DAC32_DIRECT_COLOR 0x03 69a6b33934Smacallan#define DAC_VCO_DIV 0x16 70a6b33934Smacallan#define DAC_PLL0 0x20 71a6b33934Smacallan#define DAC_MISC_1 0x70 72a6b33934Smacallan#define DAC_MISC_2 0x71 73a6b33934Smacallan#define DAC_MISC_3 0x72 74a6b33934Smacallan 75a6b33934Smacallan#define DAC_CURSOR_CTL 0x30 76a6b33934Smacallan #define DAC_CURSOR_OFF 0x00 77a6b33934Smacallan #define DAC_CURSOR_WIN 0x02 78a6b33934Smacallan #define DAC_CURSOR_X11 0x03 79a6b33934Smacallan #define DAC_CURSOR_64 0x04 /* clear for 32x32 cursor */ 80a6b33934Smacallan#define DAC_CURSOR_X 0x31 /* 32-low, 32-high */ 81a6b33934Smacallan#define DAC_CURSOR_Y 0x33 /* 32-low, 32-high */ 82a6b33934Smacallan#define DAC_CURSOR_HOT_X 0x35 /* hotspot */ 83a6b33934Smacallan#define DAC_CURSOR_HOT_Y 0x36 84a6b33934Smacallan#define DAC_CURSOR_COL_1 0x40 /* red. green and blue in subseq. registers */ 85a6b33934Smacallan#define DAC_CURSOR_COL_2 0x43 /* red. green and blue in subseq. registers */ 86a6b33934Smacallan#define DAC_CURSOR_COL_3 0x46 /* red. green and blue in subseq. registers */ 87a6b33934Smacallan#define DAC_PIX_PLL 0x8e 88a6b33934Smacallan#define DAC_CURSOR_DATA 0x100 89a6b33934Smacallan 90a6b33934Smacallan/* main registers */ 91a6b33934Smacallan#define SYS_CONF 0x0004 /* System Configuration Register */ 92a6b33934Smacallan #define BUFFER_WRITE_1 0x0200 /* writes got o buffer 1 */ 93a6b33934Smacallan #define BUFFER_WRITE_0 0x0000 /* writes go to buffer 0 */ 94a6b33934Smacallan #define BUFFER_READ_1 0x0400 /* read from buffer 1 */ 95a6b33934Smacallan #define BUFFER_READ_0 0x0000 96a6b33934Smacallan #define MEM_SWAP_BITS 0x0800 /* swap bits when accessing VRAM */ 97a6b33934Smacallan #define MEM_SWAP_BYTES 0x1000 /* swap bytes when accessing VRAM */ 98a6b33934Smacallan #define MEM_SWAP_HWORDS 0x2000 /* swap halfwords when accessing VRAM */ 99a6b33934Smacallan #define SHIFT_0 14 100a6b33934Smacallan #define SHIFT_1 17 101a6b33934Smacallan #define SHIFT_2 20 102a6b33934Smacallan #define SHIFT_3 29 103a6b33934Smacallan #define PIXEL_SHIFT 26 104a6b33934Smacallan #define SWAP_SHIFT 11 105a6b33934Smacallan /* this is what the 3GX manual says */ 106a6b33934Smacallan #define SC_8BIT 2 107a6b33934Smacallan #define SC_16BIT 3 108a6b33934Smacallan #define SC_24BIT 7 109a6b33934Smacallan #define SC_32BIT 5 110a6b33934Smacallan 111a6b33934Smacallan/* video controller registers */ 112a6b33934Smacallan#define VID_HCOUNTER 0x104 113a6b33934Smacallan#define VID_HTOTAL 0x108 114a6b33934Smacallan#define VID_HSRE 0x10c /* hsync raising edge */ 115a6b33934Smacallan#define VID_HBRE 0x110 /* hblank raising edge */ 116a6b33934Smacallan#define VID_HBFE 0x114 /* hblank falling edge */ 117a6b33934Smacallan#define VID_HCNTPRLD 0x118 /* hcounter preload */ 118a6b33934Smacallan#define VID_VCOUNTER 0x11c /* vcounter */ 119a6b33934Smacallan#define VID_VLENGTH 0x120 /* lines, including blanks */ 120a6b33934Smacallan#define VID_VSRE 0x124 /* vsync raising edge */ 121a6b33934Smacallan#define VID_VBRE 0x128 /* vblank raising edge */ 122a6b33934Smacallan#define VID_VBFE 0x12c /* vblank falling edge */ 123a6b33934Smacallan#define VID_VCNTPRLD 0x130 /* vcounter preload */ 124a6b33934Smacallan#define VID_SRADDR 0x134 /* screen repaint address */ 125a6b33934Smacallan#define VID_SRTC 0x138 /* screen repaint timing control */ 126a6b33934Smacallan#define VID_QSFCNTR 0x13c /* QSF counter */ 127a6b33934Smacallan 128a6b33934Smacallan#define VID_MEM_CONFIG 0x184 /* memory config */ 129a6b33934Smacallan#define VID_RFPERIOD 0x188 /* refresh period */ 130a6b33934Smacallan#define VID_RFCOUNT 0x18c /* refresh counter */ 131a6b33934Smacallan#define VID_RLMAX 0x190 /* RAS low max */ 132a6b33934Smacallan#define VID_RLCUR 0x194 /* RAS low current */ 133a6b33934Smacallan#define VID_DACSYNC 0x198 /* read after last DAC access */ 134a6b33934Smacallan 135a6b33934Smacallan#define ENGINE_STATUS 0x2000 /* drawing engine status register */ 136a6b33934Smacallan #define BLITTER_BUSY 0x80000000 137a6b33934Smacallan #define ENGINE_BUSY 0x40000000 138a6b33934Smacallan#define COMMAND_BLIT 0x2004 139a6b33934Smacallan#define COMMAND_QUAD 0x2008 140a6b33934Smacallan#define PIXEL_8 0x200c 141a6b33934Smacallan#define PIXEL_1 0x2080 /* pixel data for monochrome colour expansion */ 142a6b33934Smacallan/* apparently bits 2-6 control how many pixels we write - n+1 */ 143a6b33934Smacallan 144a6b33934Smacallan/* drawing engine registers */ 145a6b33934Smacallan#define COORD_INDEX 0x218c 146a6b33934Smacallan#define WINDOW_OFFSET 0x2190 147a6b33934Smacallan 148a6b33934Smacallan#define FOREGROUND_COLOR 0x2200 149a6b33934Smacallan#define BACKGROUND_COLOR 0x2204 150a6b33934Smacallan#define COLOR_0 0x2200 151a6b33934Smacallan#define COLOR_1 0x2204 152a6b33934Smacallan#define PLANE_MASK 0x2208 153a6b33934Smacallan#define DRAW_MODE 0x220c 154a6b33934Smacallan#define PATTERN_ORIGIN_X 0x2210 155a6b33934Smacallan#define PATTERN_ORIGIN_Y 0x2214 156a6b33934Smacallan#define RASTER_OP 0x2218 157a6b33934Smacallan #define ROP_NO_SOLID 0x02000 /* if set use pattern instead of color for quad operations */ 158a6b33934Smacallan #define ROP_2BIT_PATTERN 0x04000 /* 4-colour pattern instead of mono */ 159a6b33934Smacallan #define ROP_PIX1_TRANS 0x08000 /* transparent background in mono */ 160a6b33934Smacallan #define ROP_OVERSIZE 0x10000 161a6b33934Smacallan// #define ROP_PATTERN 0x20000 /* the manual says pattern enable */ 162a6b33934Smacallan #define ROP_TRANS 0x20000 /* but XFree86 says trans */ 163a6b33934Smacallan #define ROP_SRC 0xCC 164a6b33934Smacallan #define ROP_PAT 0xF0 165a6b33934Smacallan #define ROP_DST 0xAA 166a6b33934Smacallan #define ROP_SET 0xff 167a6b33934Smacallan 168a6b33934Smacallan#define PIXEL_8_REG 0x221c /* PIXEL_8 overflow data */ 169a6b33934Smacallan#define WINDOW_MIN 0x2220 170a6b33934Smacallan#define WINDOW_MAX 0x2224 171ae7dafb3Sjdc #define CLIP_MAX 0x1fff1fff 172ae7dafb3Sjdc 173ae7dafb3Sjdc#define COLOR_2 0x2230 174ae7dafb3Sjdc#define COLOR_3 0x2234 175a6b33934Smacallan 176a6b33934Smacallan#define PATTERN0 0x2280 177a6b33934Smacallan#define PATTERN1 0x2284 178a6b33934Smacallan#define PATTERN2 0x2288 179a6b33934Smacallan#define PATTERN3 0x228c 180a6b33934Smacallan#define USER0 0x2290 181a6b33934Smacallan#define USER1 0x2294 182a6b33934Smacallan#define USER2 0x2298 183a6b33934Smacallan#define USER3 0x229c 184a6b33934Smacallan#define BYTE_CLIP_MIN 0x22a0 185a6b33934Smacallan#define BYTE_CLIP_MAX 0x22a4 186a6b33934Smacallan 187a6b33934Smacallan/* coordinate registers */ 188a6b33934Smacallan#define ABS_X0 0x3008 189a6b33934Smacallan#define ABS_Y0 0x3010 190a6b33934Smacallan#define ABS_XY0 0x3018 191a6b33934Smacallan#define REL_X0 0x3028 192a6b33934Smacallan#define REL_Y0 0x3030 193a6b33934Smacallan#define REL_XY0 0x3038 194a6b33934Smacallan 195a6b33934Smacallan#define ABS_X1 0x3048 196a6b33934Smacallan#define ABS_Y1 0x3050 197a6b33934Smacallan#define ABS_XY1 0x3058 198a6b33934Smacallan#define REL_X1 0x3068 199a6b33934Smacallan#define REL_Y1 0x3070 200a6b33934Smacallan#define REL_XY1 0x3078 201a6b33934Smacallan 202a6b33934Smacallan#define ABS_X2 0x3088 203a6b33934Smacallan#define ABS_Y2 0x3090 204a6b33934Smacallan#define ABS_XY2 0x3098 205a6b33934Smacallan#define REL_X2 0x30a8 206a6b33934Smacallan#define REL_Y2 0x30b0 207a6b33934Smacallan#define REL_XY2 0x30b8 208a6b33934Smacallan 209a6b33934Smacallan#define ABS_X3 0x30c8 210a6b33934Smacallan#define ABS_Y3 0x30d0 211a6b33934Smacallan#define ABS_XY3 0x30d8 212a6b33934Smacallan#define REL_X3 0x30e8 213a6b33934Smacallan#define REL_Y3 0x30f0 214a6b33934Smacallan#define REL_XY3 0x30f8 215a6b33934Smacallan 216a6b33934Smacallan/* meta-coordinates */ 217a6b33934Smacallan#define POINT_RTW_X 0x3208 218a6b33934Smacallan#define POINT_RTW_Y 0x3210 219a6b33934Smacallan#define POINT_RTW_XY 0x3218 220a6b33934Smacallan#define POINT_RTP_X 0x3228 221a6b33934Smacallan#define POINT_RTP_Y 0x3220 222a6b33934Smacallan#define POINT_RTP_XY 0x3238 223a6b33934Smacallan 224a6b33934Smacallan#define LINE_RTW_X 0x3248 225a6b33934Smacallan#define LINE_RTW_Y 0x3250 226a6b33934Smacallan#define LINE_RTW_XY 0x3258 227a6b33934Smacallan#define LINE_RTP_X 0x3268 228a6b33934Smacallan#define LINE_RTP_Y 0x3260 229a6b33934Smacallan#define LINE_RTP_XY 0x3278 230a6b33934Smacallan 231a6b33934Smacallan#define TRIANGLE_RTW_X 0x3288 232a6b33934Smacallan#define TRIANGLE_RTW_Y 0x3290 233a6b33934Smacallan#define TRIANGLE_RTW_XY 0x3298 234a6b33934Smacallan#define TRIANGLE_RTP_X 0x32a8 235a6b33934Smacallan#define TRIANGLE_RTP_Y 0x32a0 236a6b33934Smacallan#define TRIANGLE_RTP_XY 0x32b8 237a6b33934Smacallan 238a6b33934Smacallan#define QUAD_RTW_X 0x32c8 239a6b33934Smacallan#define QUAD_RTW_Y 0x32d0 240a6b33934Smacallan#define QUAD_RTW_XY 0x32d8 241a6b33934Smacallan#define QUAD_RTP_X 0x32e8 242a6b33934Smacallan#define QUAD_RTP_Y 0x32e0 243a6b33934Smacallan#define QUAD_RTP_XY 0x32f8 244a6b33934Smacallan 245a6b33934Smacallan#define RECT_RTW_X 0x3308 246a6b33934Smacallan#define RECT_RTW_Y 0x3310 247a6b33934Smacallan#define RECT_RTW_XY 0x3318 248a6b33934Smacallan#define RECT_RTP_X 0x3328 249a6b33934Smacallan#define RECT_RTP_Y 0x3320 250a6b33934Smacallan#define RECT_RTP_XY 0x3338 251a6b33934Smacallan 252a6b33934Smacallan#endif /* PNOZZ_REGS_H */ 253