1 2/* 3 * 4 * Copyright 1995-1997 The XFree86 Project, Inc. 5 * 6 */ 7 8#ifndef _NEWMMIO_H_ 9#define _NEWMMIO_H_ 10 11#include <X11/Xmd.h> 12 13 14#define int16 CARD16 15#define int32 CARD32 16 17#define S3_NEWMMIO_VGABASE (S3_NEWMMIO_REGBASE + 0x8000) 18 19typedef struct { int16 vendor_ID; int16 device_ID; } pci_id; 20typedef struct { int16 cmd; int16 devsel; } cmd_devsel; 21 22typedef struct { 23 pci_id pci_ident; 24 cmd_devsel cmd_device_sel; 25 int32 class_code; 26 int32 dummy5; 27 int32 base0; 28 char dummy1[0x20-sizeof(int32)]; 29 int32 bios_base; 30 char dummy2[0x3c - 0x32]; 31} pci_conf_regs; 32 33 34typedef struct { int16 filler; int16 adv_f_cntl; } adv_f_cntl; 35 36typedef struct { 37 int32 cur_point; 38 char dummy1[4]; 39 int32 dest_stp; 40 char dummy2[4]; 41 int32 err_term; 42 char dummy3[4]; 43 int32 command; 44 int32 short_stroke; 45 int32 bkgd_color; 46 int32 frgd_color; 47 int32 wrt_mask; 48 int32 rd_mask; 49 int32 color_cmp; 50 int32 col_mix; 51 int32 sciss_topleft; 52 int32 sciss_botright; 53 int32 pix_mult; 54 int32 mult_misc; 55 int32 axis_pcnt; 56} packed_enhanced_regs; 57 58typedef struct { 59 int32 prim_stream_cntl; 60 int32 col_chroma_key_cntl; 61 char dummy1[0x8190 - 0x8184-sizeof(int32)]; 62 int32 second_stream_cntl; 63 int32 chroma_key_upper_bound; 64 int32 second_stream_stretch; 65 char dummy2[0x81a0 - 0x8198-sizeof(int32)]; 66 int32 blend_cntl; 67 char dummy3[0x81c0 - 0x81a0-sizeof(int32)]; 68 int32 prim_fbaddr0; 69 int32 prim_fbaddr1; 70 int32 prim_stream_stride; 71 int32 double_buffer; 72 int32 second_fbaddr0; 73 int32 second_fbaddr1; 74 int32 second_stream_stride; 75 int32 opaq_overlay_cntl; 76 int32 k1; 77 int32 k2; 78 int32 dda_vert; 79 int32 streams_fifo; 80 int32 prim_start_coord; 81 int32 prim_window_size; 82 int32 second_start_coord; 83 int32 second_window_size; 84} streams_proc_regs; 85 86typedef struct { char atr_cntl_ind; char attr_cntl_dat; char misc_out; 87 char viseo_enable; } v3c0; 88typedef struct { char seq_index; char seq_data; char dac_mask; 89 char dac_rd_index; } v3c4; 90typedef struct { char dac_wr_index; char dac_data; char feature_cntl; 91 char filler; } v3c8; 92typedef struct v3cc { char misc_out; char filler; char graph_cntl_index; 93 char graph_cntl_data; } v3cc; 94typedef struct { 95 v3c0 v3c0_regs; 96 v3c4 v3c4_regs; 97 v3c8 v3c8_regs; 98 v3cc v3cc_regs; 99} vga_3c_regs; 100 101typedef struct { char crt_index; char crt_data; int16 filler; } v3d4; 102typedef struct { int16 filler1; char feature_cntl; char filler2;} v3d8; 103 104typedef struct { 105 int32 filler; 106 v3d4 v3d4_regs; 107 v3d8 v3d8_regs; 108} vga_3bd_regs ; 109 110typedef struct { 111 int32 subsystem_csr; 112 int32 dummy; 113 adv_f_cntl adv_func_cntl; 114} subsys_regs; 115 116 117typedef struct { 118 int32 cur_x; 119 char filler1[0x8ae8 - 0x86e8 - sizeof(int32)]; 120 int32 dy_axstep; 121 char filler2[0x8ee8 - 0x8ae8 - sizeof(int32)]; 122 int32 dx_diastep; 123 char filler3[0x92e8 - 0x8ee8 - sizeof(int32)]; 124 int32 line_err; 125 char filler33[0x96e8 - 0x92e8 - sizeof(int32)]; 126 int32 mj_ax_pcnt; 127 char filler4[0x9ae8 - 0x96e8 - sizeof(int32)]; 128 int32 gp_stat; 129 char filler5[0x9ee8 - 0x9ae8 - sizeof(int32)]; 130 int32 stroke_vectrans; 131 char filler6[0xa2e8 - 0x9ee8 - sizeof(int32)]; 132 int32 back_color; 133 char filler7[0xa6e8 - 0xa2e8 - sizeof(int32)]; 134 int32 fore_col; 135 char filler8[0xaae8 - 0xa6e8 - sizeof(int32)]; 136 int32 bitplane_wmask; 137 char filler88[0xaee8 - 0xaae8 - sizeof(int32)]; 138 int32 bitplane_rmask; 139 char filler9[0xb2e8 - 0xaee8 - sizeof(int32)]; 140 int32 color_compare; 141 char filler10[0xb6e8 - 0xb2e8 - sizeof(int32)]; 142 int32 back_mix; 143 char filler101[0xbae8 - 0xb6e8 - sizeof(int32)]; 144 int32 fore_mix; 145 char filler11[0xbee8 - 0xbae8 - sizeof(int32)]; 146 int32 r_reg_data; 147 char filler12[0xe2e8 - 0xbee8 - sizeof(int32)]; 148 int32 pixel_data_transfer; 149} enhanced_regs; 150 151typedef struct { 152 int32 lpb_mode; 153 int32 lpb_fifostat; 154 int32 lpb_intflags; 155 int32 lpb_fb0addr; 156 int32 lpb_fb1addr; 157 int32 lpb_direct_addr; 158 int32 lpb_direct_data; 159 int32 lpb_gpio; 160 int32 lpb_serial_port; 161 int32 lpb_input_winsize; 162 int32 lpb_data_offsets; 163 int32 lpb_hor_decimctl; 164 int32 lpb_vert_decimctl; 165 int32 lpb_line_stride; 166 int32 lpb_output_fifo; 167} lpbus_regs; 168 169typedef struct { 170 int32 img[0x8000/4]; 171 union { pci_conf_regs regs; 172 char dummy[0x100]; 173 } pci_regs; 174 union { packed_enhanced_regs regs; 175 char dummy[0x80]; 176 } pk_enh_regs; 177 union { streams_proc_regs regs; 178 char dummy[0x82e8-0x8180]; 179 } streams_regs; 180 union { int32 cur_y; 181 char dummy[0x83b0 - 0x82e8]; 182 } cur_y; 183 union { vga_3bd_regs regs; 184 char dummy[0x83c0 - 0x83b0]; 185 } v3b_regs; 186 union { vga_3c_regs regs; 187 char dummy[0x83d0 - 0x83c0]; 188 } v3c_regs; 189 union { vga_3bd_regs regs; 190 char dummy[0x8504 - 0x83d0]; 191 } v3d_regs; 192 union { subsys_regs regs; 193 char dummy[0x86e8 - 0x8504]; 194 } subs_regs; 195 union { enhanced_regs regs; 196 char dummy[0xff00 - 0x86e8]; 197 } enh_regs; 198 union { lpbus_regs regs; 199 char dummy[0xff5c - 0xff00]; 200 } lbp_regs; 201} mm_trio_regs ; 202 203#define mmtr volatile mm_trio_regs * 204 205#define s3MmioMem (pS3->MMIOBase) 206 207#define IMG_TRANS (((mmtr)s3MmioMem)->img) 208 209#define SET_WRT_MASK(msk) ((mmtr)s3MmioMem)->pk_enh_regs.regs.wrt_mask = (msk) 210#define SET_RD_MASK(msk) ((mmtr)s3MmioMem)->pk_enh_regs.regs.rd_mask = (msk) 211#define SET_FRGD_COLOR(col) ((mmtr)s3MmioMem)->pk_enh_regs.regs.frgd_color = (col) 212#define SET_BKGD_COLOR(col) ((mmtr)s3MmioMem)->pk_enh_regs.regs.bkgd_color = (col) 213#define SET_COLOR_CMP(col) ((mmtr)s3MmioMem)->pk_enh_regs.regs.color_cmp = (col) 214#define SET_FRGD_MIX(fmix) ((mmtr)s3MmioMem)->enh_regs.regs.fore_mix = (fmix) 215#define SET_BKGD_MIX(bmix) ((mmtr)s3MmioMem)->enh_regs.regs.back_mix = (bmix) 216#define SET_PIX_CNTL(val) ((mmtr)s3MmioMem)->pk_enh_regs.regs.pix_mult = (val) | (MULT_MISC2 << 16) 217#define SET_MIN_AXIS_PCNT(min) ((mmtr)s3MmioMem)->enh_regs.regs.r_reg_data = (min) & 0xffff 218#define SET_MAJ_AXIS_PCNT(maj) ((mmtr)s3MmioMem)->enh_regs.regs.mj_ax_pcnt = (maj) 219#define SET_CURPT(c_x, c_y) ((mmtr)s3MmioMem)->pk_enh_regs.regs.cur_point = ((c_y)&0xffff) | ((c_x) << 16) 220#define SET_CUR_X(c_x) ((mmtr)s3MmioMem)->enh_regs.regs.cur_x = (c_x) 221#define SET_CUR_Y(c_y) ((mmtr)s3MmioMem)->cur_y.cur_y = (c_y) 222#define SET_DESTSTP(x,y) ((mmtr)s3MmioMem)->pk_enh_regs.regs.dest_stp = ((y)&0xffff) | ((x) << 16) 223#define SET_AXIS_PCNT(maj, min) ((mmtr)s3MmioMem)->pk_enh_regs.regs.axis_pcnt = ((min)&0xffff) | ((maj) << 16) 224#define SET_CMD(c_d) { mem_barrier(); ((mmtr)s3MmioMem)->pk_enh_regs.regs.command = (c_d); } 225#define SET_ERR_TERM(e) ((mmtr)s3MmioMem)->pk_enh_regs.regs.err_term = (e) 226#define SET_SCISSORS(x1,y1,x2,y2) {\ 227 ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_topleft = ((y1)&0xffff) | ((x1) << 16);\ 228 ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_botright = ((y2)&0xffff) | ((x2) << 16);\ 229 } 230#define SET_SCISSORS_RB(x,y) ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_botright = ((y)&0xffff) | ((x) << 16) 231#define SET_SCISSORS_L(l) ((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_topleft = ((l) << 16); 232#define SET_MULT_MISC(val) ((mmtr)s3MmioMem)->pk_enh_regs.regs.mult_misc = (val) 233 234 235/* 236 * reads from GP_STAT 237 */ 238#if !defined(__alpha__) 239#define INB_GP_STAT() ((((mmtr)s3MmioMem)->enh_regs.regs.gp_stat) & 0xff) 240#define INW_GP_STAT() ((((mmtr)s3MmioMem)->enh_regs.regs.gp_stat)) 241#else 242#define INB_GP_STAT() inb(GP_STAT) 243#define INW_GP_STAT() inw(GP_STAT) 244#endif 245 246#define SET_PIX_TRANS_L(val) ((mmtr)s3MmioMem)->img[0] = (val) 247#define SET_MIX(b,f) ((mmtr)s3MmioMem)->pk_enh_regs.regs.col_mix = ((b) << 16) | (f) 248 249 250#define WaitQueue(v) \ 251 if(!(pS3->PCIRetry)) { \ 252 mem_barrier(); \ 253 while(INB_GP_STAT() & (0x0100 >> (v))); \ 254 } 255 256#define CMD_REG_WIDTH 0x200 /* select 32bit command register */ 257 258#define WaitQueue16_32(n16,n32) \ 259 if((pS3->s3Bpp) <= 2) { WaitQueue(n16); } \ 260 else { WaitQueue(n32); } 261 262#endif /* _NEWMMIO_H_ */ 263