newmmio.h revision 340e3fbd 
1/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h,v 1.6 2001/07/02 10:46:04 alanh Exp $ */
2
3/*
4 *
5 * Copyright 1995-1997 The XFree86 Project, Inc.
6 *
7 */
8
9#ifndef _NEWMMIO_H_
10#define _NEWMMIO_H_
11
12#include <X11/Xmd.h>
13
14
15#define int16	CARD16
16#define int32	CARD32
17
18#define S3_NEWMMIO_VGABASE	(S3_NEWMMIO_REGBASE + 0x8000)
19
20typedef struct { int16 vendor_ID; int16 device_ID; } pci_id;
21typedef struct { int16 cmd; int16 devsel; } cmd_devsel;
22
23typedef struct  {
24        pci_id  pci_ident;
25        cmd_devsel cmd_device_sel;
26        int32 class_code;
27        int32 dummy5;
28        int32 base0;
29        char dummy1[0x20-sizeof(int32)];
30        int32 bios_base;
31        char dummy2[0x3c - 0x32];
32} pci_conf_regs;
33
34
35typedef struct { int16 filler; int16 adv_f_cntl; } adv_f_cntl;
36
37typedef struct {
38        int32	cur_point;
39        char    dummy1[4];
40        int32	dest_stp;
41        char    dummy2[4];
42        int32	err_term;
43        char    dummy3[4];
44        int32	command;
45        int32	short_stroke;
46        int32   bkgd_color;
47        int32   frgd_color;
48        int32   wrt_mask;
49        int32   rd_mask;
50        int32   color_cmp;
51        int32	col_mix;
52        int32	sciss_topleft;
53        int32	sciss_botright;
54        int32	pix_mult;
55        int32	mult_misc;
56        int32	axis_pcnt;
57} packed_enhanced_regs;
58
59typedef struct  {
60        int32  prim_stream_cntl;
61        int32  col_chroma_key_cntl;
62        char    dummy1[0x8190 - 0x8184-sizeof(int32)];
63        int32  second_stream_cntl;
64        int32  chroma_key_upper_bound;
65        int32  second_stream_stretch;
66        char dummy2[0x81a0 - 0x8198-sizeof(int32)];
67        int32  blend_cntl;
68        char    dummy3[0x81c0 - 0x81a0-sizeof(int32)];
69        int32  prim_fbaddr0;
70        int32  prim_fbaddr1;
71        int32  prim_stream_stride;
72        int32  double_buffer;
73        int32  second_fbaddr0;
74        int32  second_fbaddr1;
75        int32  second_stream_stride;
76        int32  opaq_overlay_cntl;
77        int32  k1;
78        int32  k2;
79        int32  dda_vert;
80        int32  streams_fifo;
81        int32  prim_start_coord;
82        int32  prim_window_size;
83        int32  second_start_coord;
84        int32  second_window_size;
85} streams_proc_regs;
86
87typedef struct { char atr_cntl_ind; char attr_cntl_dat; char misc_out;
88                 char viseo_enable; } v3c0;
89typedef struct { char seq_index; char seq_data; char dac_mask;
90                      char dac_rd_index; } v3c4;
91typedef struct { char dac_wr_index; char dac_data; char feature_cntl;
92                      char filler; } v3c8;
93typedef struct v3cc { char misc_out; char filler; char graph_cntl_index;
94                      char graph_cntl_data; } v3cc;
95typedef struct {
96        v3c0    v3c0_regs;
97        v3c4    v3c4_regs;
98        v3c8    v3c8_regs;
99        v3cc    v3cc_regs;
100} vga_3c_regs;
101
102typedef struct { char crt_index; char crt_data; int16 filler; } v3d4;
103typedef struct { int16 filler1; char feature_cntl; char filler2;} v3d8;
104
105typedef struct  {
106        int32   filler;
107        v3d4    v3d4_regs;
108        v3d8    v3d8_regs;
109} vga_3bd_regs ;
110
111typedef struct {
112                int32	subsystem_csr;
113		int32	dummy;
114                adv_f_cntl adv_func_cntl;
115} subsys_regs;
116
117
118typedef struct  {
119        int32	cur_x;
120        char    filler1[0x8ae8 - 0x86e8 - sizeof(int32)];
121        int32	dy_axstep;
122        char    filler2[0x8ee8 - 0x8ae8 - sizeof(int32)];
123        int32	dx_diastep;
124        char    filler3[0x92e8 - 0x8ee8 - sizeof(int32)];
125        int32	line_err;
126        char    filler33[0x96e8 - 0x92e8 - sizeof(int32)];
127        int32	mj_ax_pcnt;
128        char    filler4[0x9ae8 - 0x96e8 - sizeof(int32)];
129        int32	gp_stat;
130        char    filler5[0x9ee8 - 0x9ae8 - sizeof(int32)];
131        int32	stroke_vectrans;
132        char    filler6[0xa2e8 - 0x9ee8 - sizeof(int32)];
133        int32  back_color;
134        char    filler7[0xa6e8 - 0xa2e8 - sizeof(int32)];
135        int32  fore_col;
136        char    filler8[0xaae8 - 0xa6e8 - sizeof(int32)];
137        int32  bitplane_wmask;
138        char    filler88[0xaee8 - 0xaae8 - sizeof(int32)];
139        int32  bitplane_rmask;
140        char    filler9[0xb2e8 - 0xaee8 - sizeof(int32)];
141        int32  color_compare;
142        char    filler10[0xb6e8 - 0xb2e8 - sizeof(int32)];
143        int32	back_mix;
144        char    filler101[0xbae8 - 0xb6e8 - sizeof(int32)];
145        int32	fore_mix;
146        char    filler11[0xbee8 - 0xbae8 - sizeof(int32)];
147        int32	r_reg_data;
148        char    filler12[0xe2e8 - 0xbee8 - sizeof(int32)];
149        int32	pixel_data_transfer;
150} enhanced_regs;
151
152typedef struct {
153	int32	lpb_mode;
154	int32	lpb_fifostat;
155	int32	lpb_intflags;
156	int32	lpb_fb0addr;
157	int32	lpb_fb1addr;
158	int32	lpb_direct_addr;
159	int32	lpb_direct_data;
160	int32	lpb_gpio;
161	int32	lpb_serial_port;
162	int32	lpb_input_winsize;
163	int32	lpb_data_offsets;
164	int32	lpb_hor_decimctl;
165	int32	lpb_vert_decimctl;
166	int32	lpb_line_stride;
167	int32	lpb_output_fifo;
168} lpbus_regs;
169
170typedef struct {
171        int32 img[0x8000/4];
172        union { pci_conf_regs regs;
173                char dummy[0x100];
174        } pci_regs;
175        union { packed_enhanced_regs regs;
176                char dummy[0x80];
177        } pk_enh_regs;
178        union { streams_proc_regs regs;
179                char dummy[0x82e8-0x8180];
180        } streams_regs;
181        union { int32	cur_y;
182                char dummy[0x83b0 - 0x82e8];
183        } cur_y;
184        union { vga_3bd_regs    regs;
185                char dummy[0x83c0 - 0x83b0];
186        } v3b_regs;
187        union { vga_3c_regs     regs;
188                char dummy[0x83d0 - 0x83c0];
189        } v3c_regs;
190        union { vga_3bd_regs    regs;
191                char dummy[0x8504 - 0x83d0];
192        } v3d_regs;
193        union { subsys_regs     regs;
194                char dummy[0x86e8 - 0x8504];
195        } subs_regs;
196        union { enhanced_regs   regs;
197                char dummy[0xff00 - 0x86e8];
198        } enh_regs;
199        union { lpbus_regs   regs;
200                char dummy[0xff5c - 0xff00];
201        } lbp_regs;
202} mm_trio_regs ;
203
204#define mmtr	volatile mm_trio_regs *
205
206#define s3MmioMem		(pS3->MMIOBase)
207
208#define IMG_TRANS		(((mmtr)s3MmioMem)->img)
209
210#define SET_WRT_MASK(msk)	((mmtr)s3MmioMem)->pk_enh_regs.regs.wrt_mask = (msk)
211#define SET_RD_MASK(msk)	((mmtr)s3MmioMem)->pk_enh_regs.regs.rd_mask  = (msk)
212#define SET_FRGD_COLOR(col)	((mmtr)s3MmioMem)->pk_enh_regs.regs.frgd_color = (col)
213#define SET_BKGD_COLOR(col)	((mmtr)s3MmioMem)->pk_enh_regs.regs.bkgd_color = (col)
214#define SET_COLOR_CMP(col)	((mmtr)s3MmioMem)->pk_enh_regs.regs.color_cmp = (col)
215#define SET_FRGD_MIX(fmix)	((mmtr)s3MmioMem)->enh_regs.regs.fore_mix = (fmix)
216#define SET_BKGD_MIX(bmix)	((mmtr)s3MmioMem)->enh_regs.regs.back_mix = (bmix)
217#define SET_PIX_CNTL(val)	((mmtr)s3MmioMem)->pk_enh_regs.regs.pix_mult = (val) | (MULT_MISC2 << 16)
218#define SET_MIN_AXIS_PCNT(min)	((mmtr)s3MmioMem)->enh_regs.regs.r_reg_data = (min) & 0xffff
219#define SET_MAJ_AXIS_PCNT(maj)	((mmtr)s3MmioMem)->enh_regs.regs.mj_ax_pcnt = (maj)
220#define SET_CURPT(c_x, c_y)	((mmtr)s3MmioMem)->pk_enh_regs.regs.cur_point = ((c_y)&0xffff) | ((c_x) << 16)
221#define SET_CUR_X(c_x)		((mmtr)s3MmioMem)->enh_regs.regs.cur_x = (c_x)
222#define SET_CUR_Y(c_y)		((mmtr)s3MmioMem)->cur_y.cur_y = (c_y)
223#define SET_DESTSTP(x,y)	((mmtr)s3MmioMem)->pk_enh_regs.regs.dest_stp = ((y)&0xffff) | ((x) << 16)
224#define SET_AXIS_PCNT(maj, min)	((mmtr)s3MmioMem)->pk_enh_regs.regs.axis_pcnt = ((min)&0xffff) | ((maj) << 16)
225#define SET_CMD(c_d) 		{ mem_barrier(); ((mmtr)s3MmioMem)->pk_enh_regs.regs.command = (c_d); }
226#define SET_ERR_TERM(e)		((mmtr)s3MmioMem)->pk_enh_regs.regs.err_term = (e)
227#define SET_SCISSORS(x1,y1,x2,y2) {\
228				((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_topleft  = ((y1)&0xffff) | ((x1) << 16);\
229				((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_botright = ((y2)&0xffff) | ((x2) << 16);\
230				}
231#define SET_SCISSORS_RB(x,y)	((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_botright = ((y)&0xffff) | ((x) << 16)
232#define SET_SCISSORS_L(l)	((mmtr)s3MmioMem)->pk_enh_regs.regs.sciss_topleft  = ((l) << 16);
233#define SET_MULT_MISC(val)	((mmtr)s3MmioMem)->pk_enh_regs.regs.mult_misc = (val)
234
235
236/*
237 * reads from GP_STAT
238 */
239#if !defined(__alpha__)
240#define INB_GP_STAT() 	((((mmtr)s3MmioMem)->enh_regs.regs.gp_stat) & 0xff)
241#define INW_GP_STAT() 	((((mmtr)s3MmioMem)->enh_regs.regs.gp_stat))
242#else
243#define INB_GP_STAT() 	inb(GP_STAT)
244#define INW_GP_STAT() 	inw(GP_STAT)
245#endif
246
247#define SET_PIX_TRANS_L(val)	((mmtr)s3MmioMem)->img[0] = (val)
248#define SET_MIX(b,f)	((mmtr)s3MmioMem)->pk_enh_regs.regs.col_mix = ((b) << 16) | (f)
249
250
251#define WaitQueue(v)					\
252	if(!(pS3->PCIRetry)) {				\
253	   mem_barrier();				\
254	   while(inb(GP_STAT) & (0x0100 >> (v)));	\
255	}
256
257#define CMD_REG_WIDTH  0x200  	/* select 32bit command register */
258
259#define WaitQueue16_32(n16,n32) 		\
260	if((pS3->s3Bpp) <= 2) { WaitQueue(n16); }	\
261	else { 	WaitQueue(n32); }
262
263#endif /* _NEWMMIO_H_ */
264