1/*
2 *      Copyright 2001  Ani Joshi <ajoshi@unixbox.com>
3 *
4 *      XFree86 4.x driver for S3 chipsets
5 *
6 *
7 * Permission to use, copy, modify, distribute, and sell this software and its
8 * documentation for any purpose is hereby granted without fee, provided that
9 * the above copyright notice appear in all copies and that both that copyright
10 * notice and this permission notice appear in supporting documentation and
11 * that the name of Ani Joshi not be used in advertising or
12 * publicity pertaining to distribution of the software without specific,
13 * written prior permission.  Ani Joshi makes no representations
14 * about the suitability of this software for any purpose.  It is provided
15 * "as-is" without express or implied warranty.
16 *
17 * ANI JOSHI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
19 * EVENT SHALL ANI JOSHI BE LIABLE FOR ANY SPECIAL, INDIRECT OR
20 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
21 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
22 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
23 * PERFORMANCE OF THIS SOFTWARE.
24 *
25 *
26 */
27
28
29#ifndef _S3_H
30#define _S3_H
31
32#include "s3_pcirename.h"
33#include <string.h>
34
35#include "xf86.h"
36#include "xf86Pci.h"
37#if ABI_VIDEODRV_VERSION < SET_ABI_VERSION(25, 2)
38#include "xf86RamDac.h"
39#else
40#include "xf86Cursor.h"
41#endif
42#ifdef HAVE_XAA_H
43#include "xaa.h"
44#endif
45#include "xf86fbman.h"
46#include "vbe.h"
47#include "vgaHW.h"
48
49
50#include "xf86xv.h"
51#include <X11/extensions/Xv.h>
52#include "fourcc.h"
53
54#include "compat-api.h"
55
56
57#define PCI_VENDOR_S3			0x5333
58
59#define PCI_CHIP_PLATO			0x0551
60#define PCI_CHIP_TRIO			0x8811
61#define PCI_CHIP_AURORA64VP		0x8812
62#define PCI_CHIP_TRIO64UVP		0x8814
63#define PCI_CHIP_868			0x8880
64#define PCI_CHIP_928			0x88B0
65#define PCI_CHIP_864_0			0x88C0
66#define PCI_CHIP_864_1			0x88C1
67#define PCI_CHIP_964_0			0x88D0
68#define PCI_CHIP_964_1			0x88D1
69#define PCI_CHIP_968			0x88F0
70#define PCI_CHIP_TRIO64V2_DXGX	0x8901
71#define PCI_CHIP_PLATO_PX		0x8902
72
73
74typedef struct _S3RegRec {
75	unsigned char	cr31, cr32, cr33, cr34, cr3a, cr3b, cr3c;
76	unsigned char	cr3b2, cr3c2;
77	unsigned char	cr40, cr42, cr43, cr44, cr45;
78	unsigned char	cr50, cr51, cr53, cr54, cr55, cr58, cr59, cr5a,
79			cr5d, cr5e;
80	unsigned char	cr60, cr61, cr62, cr65, cr66, cr67, cr6d;
81	unsigned char	s3save[10];
82	unsigned char	s3syssave[46];
83	unsigned char	dacregs[0x101];
84	unsigned char	color_stack[8];
85	unsigned char	clock;
86} S3RegRec, *S3RegPtr;
87
88
89typedef struct {
90        unsigned char brightness;
91        unsigned char contrast;
92        FBLinearPtr   area;
93        RegionRec     clip;
94        CARD32        colorKey;
95        CARD32        videoStatus;
96        Time          offTime;
97        Time          freeTime;
98        int           lastPort;
99} S3PortPrivRec, *S3PortPrivPtr;
100
101
102typedef struct {
103	int bitsPerPixel;
104	int depth;
105	int displayWidth;
106	int pixel_code;
107	int pixel_bytes;
108	DisplayModePtr mode;
109} S3FBLayout;
110
111
112typedef struct _S3Rec {
113        pciVideoPtr             PciInfo;
114#ifndef XSERVER_LIBPCIACCESS
115        PCITAG                  PciTag;
116#endif
117        EntityInfoPtr           pEnt;
118        unsigned long           IOAddress;
119        unsigned long           FBAddress;
120        unsigned char *         FBBase;
121        unsigned char *         MMIOBase;
122        unsigned long           videoRam;
123        OptionInfoPtr           Options;
124        unsigned int            Flags;
125        Bool                    NoAccel;
126	Bool			HWCursor;
127	Bool			SlowDRAMRefresh;
128	Bool			SlowDRAM;
129	Bool			SlowEDODRAM;
130	Bool			SlowVRAM;
131	Bool			S3NewMMIO;
132	Bool                    hasStreams;
133	int                     Streams_FIFO;
134	Bool                    XVideo;
135	Bool			PCIRetry;
136	Bool			ColorExpandBug;
137
138#ifdef HAVE_XAA_H
139        XAAInfoRecPtr           pXAA;
140#endif
141	xf86CursorInfoPtr	pCurs;
142	xf86Int10InfoPtr	pInt10;
143        XF86VideoAdaptorPtr     adaptor;
144        S3PortPrivPtr           portPrivate;
145
146	DGAModePtr		DGAModes;
147	int			numDGAModes;
148	Bool			DGAactive;
149	int			DGAViewportStatus;
150
151	S3FBLayout		CurrentLayout;
152
153	RamDacHelperRecPtr	RamDac;
154	RamDacRecPtr		RamDacRec;
155
156	int			vgaCRIndex, vgaCRReg;
157
158	int			s3Bpp, s3BppDisplayWidth, HDisplay;
159	int			mclk, MaxClock;
160	int			pixMuxShift;
161
162        int                     Chipset, ChipRev;
163	int			RefClock;
164
165	int			s3ScissB, s3ScissR;
166	unsigned short		BltDir;
167	int			trans_color;
168	int			FBCursorOffset;
169
170	S3RegRec		SavedRegs;
171	S3RegRec		ModeRegs;
172
173	unsigned char		SAM256;
174
175	void			(*DacPreInit)(ScrnInfoPtr pScrn);
176	void			(*DacInit)(ScrnInfoPtr pScrn,
177					   DisplayModePtr mode);
178	void			(*DacSave)(ScrnInfoPtr pScrn);
179	void			(*DacRestore)(ScrnInfoPtr pScrn);
180	Bool			(*CursorInit)(ScreenPtr pScreen);
181
182	void			(*LoadPalette)(ScrnInfoPtr pScrn, int numColors,
183					       int *indicies, LOCO *colors,
184					       VisualPtr pVisual);
185
186	Bool                    (*CloseScreen)(CLOSE_SCREEN_ARGS_DECL);
187
188	unsigned char		*imageBuffer;
189	int			imageWidth;
190	int			imageHeight;
191	Bool			hwCursor;
192
193	Bool                    shadowFB;
194	int                     rotate;
195	unsigned char           * ShadowPtr;
196	int                     ShadowPitch;
197	void	                (*PointerMoved)(SCRN_ARG_TYPE arg, int x, int y);
198
199} S3Rec, *S3Ptr;
200
201#define S3PTR(p)		((S3Ptr)((p)->driverPrivate))
202
203
204#define DRIVER_NAME     "s3"
205#define DRIVER_VERSION  PACKAGE_VERSION
206#define VERSION_MAJOR   PACKAGE_VERSION_MAJOR
207#define VERSION_MINOR   PACKAGE_VERSION_MINOR
208#define PATCHLEVEL      PACKAGE_VERSION_PATCHLEVEL
209#define S3_VERSION     ((VERSION_MAJOR << 24) | \
210                        (VERSION_MINOR << 16) | PATCHLEVEL)
211
212
213
214
215/*
216 * Prototypes
217 */
218
219Bool S3AccelInit(ScreenPtr pScreen);
220Bool S3AccelInitNewMMIO(ScreenPtr pScreen);
221Bool S3AccelInitPIO(ScreenPtr pScreen);
222Bool S3DGAInit(ScreenPtr pScreen);
223Bool S3SwitchMode(SWITCH_MODE_ARGS_DECL);
224int S3GetRefClock(ScrnInfoPtr pScrn);
225
226void S3InitVideo(ScreenPtr pScreen);
227void S3InitStreams(ScrnInfoPtr pScrn, DisplayModePtr mode);
228
229/* IBMRGB */
230extern RamDacSupportedInfoRec S3IBMRamdacs[];
231Bool S3ProbeIBMramdac(ScrnInfoPtr pScrn);
232void S3IBMRGB_PreInit(ScrnInfoPtr pScrn);
233void S3IBMRGB_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
234void S3IBMRGB_Save(ScrnInfoPtr pScrn);
235void S3IBMRGB_Restore(ScrnInfoPtr pScrn);
236Bool S3IBMRGB_CursorInit(ScreenPtr pScreen);
237
238/* TRIO64 */
239Bool S3Trio64DACProbe(ScrnInfoPtr pScrn);
240void S3Trio64DAC_PreInit(ScrnInfoPtr pScrn);
241void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
242void S3Trio64DAC_Save(ScrnInfoPtr pScrn);
243void S3Trio64DAC_Restore(ScrnInfoPtr pScrn);
244
245/* Ti */
246Bool S3TiDACProbe(ScrnInfoPtr pScrn);
247void S3TiDAC_PreInit(ScrnInfoPtr pScrn);
248void S3TiDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
249void S3TiDAC_Save(ScrnInfoPtr pScrn);
250void S3TiDAC_Restore(ScrnInfoPtr pScrn);
251void S3TiLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indicies, LOCO *colors,
252		     VisualPtr pVisual);
253Bool S3Ti_CursorInit(ScreenPtr pScreen);
254void S3OutTiIndReg(ScrnInfoPtr pScrn, CARD32 reg, unsigned char mask,
255		   unsigned char data);
256
257/* SDAC/GENDAC */
258Bool S3SDACProbe(ScrnInfoPtr pScrn);
259void S3GENDAC_PreInit(ScrnInfoPtr pScrn);
260void S3GENDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
261void S3SDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
262void S3GENDAC_Save(ScrnInfoPtr pScrn);
263void S3GENDAC_Restore(ScrnInfoPtr pScrn);
264
265/* s3 gen cursor */
266Bool S3_CursorInit(ScreenPtr pScreen);
267
268/* in s3_shadow.c */
269void S3PointerMoved(SCRN_ARG_TYPE arg, int x, int y);
270void S3RefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
271void S3RefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
272void S3RefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
273void S3RefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
274void S3RefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
275
276Bool S3GENDACProbe(ScrnInfoPtr pScrn);
277
278
279#define TRIO64_RAMDAC	0x8811
280#define	TI3025_RAMDAC	0x3025
281#define	TI3020_RAMDAC	0x3020
282#define	GENDAC_RAMDAC	0x0708
283#define	SDAC_RAMDAC	0x0716
284
285/*
286 * Chip...Sets...
287 */
288
289#define S3_864_SERIES()		((pS3->Chipset == PCI_CHIP_864_0) ||	\
290				 (pS3->Chipset == PCI_CHIP_864_1))
291#define S3_964_SERIES()		((pS3->Chipset == PCI_CHIP_964_0) ||	\
292			 	 (pS3->Chipset == PCI_CHIP_964_1))
293
294#define	S3_TRIO_SERIES()	((pS3->Chipset == PCI_CHIP_TRIO) ||	\
295			 	 (pS3->Chipset == PCI_CHIP_AURORA64VP) || \
296				 (pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
297				 (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
298#endif /* _S3_H */
299