s3.h revision 340e3fbd 
1/*
2 *      Copyright 2001  Ani Joshi <ajoshi@unixbox.com>
3 *
4 *      XFree86 4.x driver for S3 chipsets
5 *
6 *
7 * Permission to use, copy, modify, distribute, and sell this software and its
8 * documentation for any purpose is hereby granted without fee, provided that
9 * the above copyright notice appear in all copies and that both that copyright
10 * notice and this permission notice appear in supporting documentation and
11 * that the name of Ani Joshi not be used in advertising or
12 * publicity pertaining to distribution of the software without specific,
13 * written prior permission.  Ani Joshi makes no representations
14 * about the suitability of this software for any purpose.  It is provided
15 * "as-is" without express or implied warranty.
16 *
17 * ANI JOSHI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
19 * EVENT SHALL ANI JOSHI BE LIABLE FOR ANY SPECIAL, INDIRECT OR
20 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
21 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
22 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
23 * PERFORMANCE OF THIS SOFTWARE.
24 *
25 *
26 */
27/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/s3/s3.h,v 1.17 2003/07/04 16:24:28 eich Exp $ */
28
29
30#ifndef _S3_H
31#define _S3_H
32
33#include <string.h>
34
35#include "xf86.h"
36#include "xf86Pci.h"
37#include "xf86PciInfo.h"
38#include "xf86RamDac.h"
39#include "xaa.h"
40#include "vbe.h"
41#include "vgaHW.h"
42
43
44#include "xf86xv.h"
45#include <X11/extensions/Xv.h>
46#include "fourcc.h"
47
48
49typedef struct _S3RegRec {
50	unsigned char	cr31, cr32, cr33, cr34, cr3a, cr3b, cr3c;
51	unsigned char	cr3b2, cr3c2;
52	unsigned char	cr40, cr42, cr43, cr44, cr45;
53	unsigned char	cr50, cr51, cr53, cr54, cr55, cr58, cr59, cr5a,
54			cr5d, cr5e;
55	unsigned char	cr60, cr61, cr62, cr65, cr66, cr67, cr6d;
56	unsigned char	s3save[10];
57	unsigned char	s3syssave[46];
58	unsigned char	dacregs[0x101];
59	unsigned char	color_stack[8];
60	unsigned char	clock;
61} S3RegRec, *S3RegPtr;
62
63
64typedef struct {
65        unsigned char brightness;
66        unsigned char contrast;
67        FBAreaPtr     area;
68        RegionRec     clip;
69        CARD32        colorKey;
70        CARD32        videoStatus;
71        Time          offTime;
72        Time          freeTime;
73        int           lastPort;
74} S3PortPrivRec, *S3PortPrivPtr;
75
76
77typedef struct {
78	int bitsPerPixel;
79	int depth;
80	int displayWidth;
81	int pixel_code;
82	int pixel_bytes;
83	DisplayModePtr mode;
84} S3FBLayout;
85
86
87typedef struct _S3Rec {
88        pciVideoPtr             PciInfo;
89        PCITAG                  PciTag;
90        EntityInfoPtr           pEnt;
91        unsigned long           IOAddress;
92        unsigned long           FBAddress;
93        unsigned char *         FBBase;
94        unsigned char *         MMIOBase;
95        unsigned long           videoRam;
96        OptionInfoPtr           Options;
97        unsigned int            Flags;
98        Bool                    NoAccel;
99	Bool			SWCursor;
100	Bool			SlowDRAMRefresh;
101	Bool			SlowDRAM;
102	Bool			SlowEDODRAM;
103	Bool			SlowVRAM;
104	Bool			S3NewMMIO;
105	Bool			PCIRetry;
106	Bool			ColorExpandBug;
107
108        XAAInfoRecPtr           pXAA;
109	xf86CursorInfoPtr	pCurs;
110	xf86Int10InfoPtr	pInt10;
111	vbeInfoPtr		pVBE;
112        XF86VideoAdaptorPtr     adaptor;
113        S3PortPrivPtr           portPrivate;
114
115	DGAModePtr		DGAModes;
116	int			numDGAModes;
117	Bool			DGAactive;
118	int			DGAViewportStatus;
119
120	S3FBLayout		CurrentLayout;
121
122	RamDacHelperRecPtr	RamDac;
123	RamDacRecPtr		RamDacRec;
124
125	int			vgaCRIndex, vgaCRReg;
126
127	int			s3Bpp, s3BppDisplayWidth, HDisplay;
128	int			mclk, MaxClock;
129	int			pixMuxShift;
130
131        int                     Chipset, ChipRev;
132	int			RefClock;
133
134	int			s3ScissB, s3ScissR;
135	unsigned short		BltDir;
136	int			trans_color;
137	int			FBCursorOffset;
138
139	S3RegRec		SavedRegs;
140	S3RegRec		ModeRegs;
141
142	unsigned char		SAM256;
143
144	void			(*DacPreInit)(ScrnInfoPtr pScrn);
145	void			(*DacInit)(ScrnInfoPtr pScrn,
146					   DisplayModePtr mode);
147	void			(*DacSave)(ScrnInfoPtr pScrn);
148	void			(*DacRestore)(ScrnInfoPtr pScrn);
149	Bool			(*CursorInit)(ScreenPtr pScreen);
150
151	void			(*LoadPalette)(ScrnInfoPtr pScrn, int numColors,
152					       int *indicies, LOCO *colors,
153					       VisualPtr pVisual);
154
155        Bool                    (*CloseScreen)(int, ScreenPtr);
156
157	unsigned char		*imageBuffer;
158	int			imageWidth;
159	int			imageHeight;
160    Bool			hwCursor;
161} S3Rec, *S3Ptr;
162
163#define S3PTR(p)		((S3Ptr)((p)->driverPrivate))
164
165
166#define DRIVER_NAME     "s3"
167#define DRIVER_VERSION  "0.5.0"
168#define VERSION_MAJOR   0
169#define VERSION_MINOR   5
170#define PATCHLEVEL      0
171#define S3_VERSION     ((VERSION_MAJOR << 24) | \
172                        (VERSION_MINOR << 16) | PATCHLEVEL)
173
174
175
176
177/*
178 * Prototypes
179 */
180
181Bool S3AccelInit(ScreenPtr pScreen);
182Bool S3AccelInitNewMMIO(ScreenPtr pScreen);
183Bool S3AccelInitPIO(ScreenPtr pScreen);
184Bool S3DGAInit(ScreenPtr pScreen);
185Bool S3SwitchMode(int scrnIndex, DisplayModePtr mode, int flags);
186int S3GetRefClock(ScrnInfoPtr pScrn);
187
188void S3InitVideo(ScreenPtr pScreen);
189void S3InitStreams(ScrnInfoPtr pScrn, DisplayModePtr mode);
190
191/* IBMRGB */
192extern RamDacSupportedInfoRec S3IBMRamdacs[];
193Bool S3ProbeIBMramdac(ScrnInfoPtr pScrn);
194void S3IBMRGB_PreInit(ScrnInfoPtr pScrn);
195void S3IBMRGB_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
196void S3IBMRGB_Save(ScrnInfoPtr pScrn);
197void S3IBMRGB_Restore(ScrnInfoPtr pScrn);
198Bool S3IBMRGB_CursorInit(ScreenPtr pScreen);
199
200/* TRIO64 */
201Bool S3Trio64DACProbe(ScrnInfoPtr pScrn);
202void S3Trio64DAC_PreInit(ScrnInfoPtr pScrn);
203void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
204void S3Trio64DAC_Save(ScrnInfoPtr pScrn);
205void S3Trio64DAC_Restore(ScrnInfoPtr pScrn);
206
207/* Ti */
208Bool S3TiDACProbe(ScrnInfoPtr pScrn);
209void S3TiDAC_PreInit(ScrnInfoPtr pScrn);
210void S3TiDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
211void S3TiDAC_Save(ScrnInfoPtr pScrn);
212void S3TiDAC_Restore(ScrnInfoPtr pScrn);
213void S3TiLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indicies, LOCO *colors,
214		     VisualPtr pVisual);
215Bool S3Ti_CursorInit(ScreenPtr pScreen);
216void S3OutTiIndReg(ScrnInfoPtr pScrn, CARD32 reg, unsigned char mask,
217		   unsigned char data);
218
219/* s3 gen cursor */
220Bool S3_CursorInit(ScreenPtr pScreen);
221
222#define TRIO64_RAMDAC	0x8811
223#define	TI3025_RAMDAC	0x3025
224#define	TI3020_RAMDAC	0x3020
225
226#define BIOS_BSIZE	1024
227#define	BIOS_BASE	0xc0000
228
229/*
230 * Chip...Sets...
231 */
232
233#define S3_964_SERIES()		((pS3->Chipset == PCI_CHIP_964_0) ||	\
234			 	 (pS3->Chipset == PCI_CHIP_964_1))
235#define	S3_TRIO_SERIES()	((pS3->Chipset == PCI_CHIP_TRIO) ||	\
236			 	 (pS3->Chipset == PCI_CHIP_AURORA64VP) || \
237				 (pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
238				 (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
239
240#endif /* _S3_H */
241