s3.h revision a9060c92 
1/*
2 *      Copyright 2001  Ani Joshi <ajoshi@unixbox.com>
3 *
4 *      XFree86 4.x driver for S3 chipsets
5 *
6 *
7 * Permission to use, copy, modify, distribute, and sell this software and its
8 * documentation for any purpose is hereby granted without fee, provided that
9 * the above copyright notice appear in all copies and that both that copyright
10 * notice and this permission notice appear in supporting documentation and
11 * that the name of Ani Joshi not be used in advertising or
12 * publicity pertaining to distribution of the software without specific,
13 * written prior permission.  Ani Joshi makes no representations
14 * about the suitability of this software for any purpose.  It is provided
15 * "as-is" without express or implied warranty.
16 *
17 * ANI JOSHI DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
19 * EVENT SHALL ANI JOSHI BE LIABLE FOR ANY SPECIAL, INDIRECT OR
20 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
21 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
22 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
23 * PERFORMANCE OF THIS SOFTWARE.
24 *
25 *
26 */
27
28
29#ifndef _S3_H
30#define _S3_H
31
32#include "s3_pcirename.h"
33#include <string.h>
34
35#include "xf86.h"
36#include "xf86Pci.h"
37#include "xf86PciInfo.h"
38#include "xf86RamDac.h"
39#include "xaa.h"
40#include "vbe.h"
41#include "vgaHW.h"
42
43
44#include "xf86xv.h"
45#include <X11/extensions/Xv.h>
46#include "fourcc.h"
47
48
49typedef struct _S3RegRec {
50	unsigned char	cr31, cr32, cr33, cr34, cr3a, cr3b, cr3c;
51	unsigned char	cr3b2, cr3c2;
52	unsigned char	cr40, cr42, cr43, cr44, cr45;
53	unsigned char	cr50, cr51, cr53, cr54, cr55, cr58, cr59, cr5a,
54			cr5d, cr5e;
55	unsigned char	cr60, cr61, cr62, cr65, cr66, cr67, cr6d;
56	unsigned char	s3save[10];
57	unsigned char	s3syssave[46];
58	unsigned char	dacregs[0x101];
59	unsigned char	color_stack[8];
60	unsigned char	clock;
61} S3RegRec, *S3RegPtr;
62
63
64typedef struct {
65        unsigned char brightness;
66        unsigned char contrast;
67        FBLinearPtr   area;
68        RegionRec     clip;
69        CARD32        colorKey;
70        CARD32        videoStatus;
71        Time          offTime;
72        Time          freeTime;
73        int           lastPort;
74} S3PortPrivRec, *S3PortPrivPtr;
75
76
77typedef struct {
78	int bitsPerPixel;
79	int depth;
80	int displayWidth;
81	int pixel_code;
82	int pixel_bytes;
83	DisplayModePtr mode;
84} S3FBLayout;
85
86
87typedef struct _S3Rec {
88        pciVideoPtr             PciInfo;
89#ifndef XSERVER_LIBPCIACCESS
90        PCITAG                  PciTag;
91#endif
92        EntityInfoPtr           pEnt;
93        unsigned long           IOAddress;
94        unsigned long           FBAddress;
95        unsigned char *         FBBase;
96        unsigned char *         MMIOBase;
97        unsigned long           videoRam;
98        OptionInfoPtr           Options;
99        unsigned int            Flags;
100        Bool                    NoAccel;
101	Bool			HWCursor;
102	Bool			SlowDRAMRefresh;
103	Bool			SlowDRAM;
104	Bool			SlowEDODRAM;
105	Bool			SlowVRAM;
106	Bool			S3NewMMIO;
107	Bool                    hasStreams;
108	int                     Streams_FIFO;
109	Bool                    XVideo;
110	Bool			PCIRetry;
111	Bool			ColorExpandBug;
112
113        XAAInfoRecPtr           pXAA;
114	xf86CursorInfoPtr	pCurs;
115	xf86Int10InfoPtr	pInt10;
116	vbeInfoPtr		pVBE;
117        XF86VideoAdaptorPtr     adaptor;
118        S3PortPrivPtr           portPrivate;
119
120	DGAModePtr		DGAModes;
121	int			numDGAModes;
122	Bool			DGAactive;
123	int			DGAViewportStatus;
124
125	S3FBLayout		CurrentLayout;
126
127	RamDacHelperRecPtr	RamDac;
128	RamDacRecPtr		RamDacRec;
129
130	int			vgaCRIndex, vgaCRReg;
131
132	int			s3Bpp, s3BppDisplayWidth, HDisplay;
133	int			mclk, MaxClock;
134	int			pixMuxShift;
135
136        int                     Chipset, ChipRev;
137	int			RefClock;
138
139	int			s3ScissB, s3ScissR;
140	unsigned short		BltDir;
141	int			trans_color;
142	int			FBCursorOffset;
143
144	S3RegRec		SavedRegs;
145	S3RegRec		ModeRegs;
146
147	unsigned char		SAM256;
148
149	void			(*DacPreInit)(ScrnInfoPtr pScrn);
150	void			(*DacInit)(ScrnInfoPtr pScrn,
151					   DisplayModePtr mode);
152	void			(*DacSave)(ScrnInfoPtr pScrn);
153	void			(*DacRestore)(ScrnInfoPtr pScrn);
154	Bool			(*CursorInit)(ScreenPtr pScreen);
155
156	void			(*LoadPalette)(ScrnInfoPtr pScrn, int numColors,
157					       int *indicies, LOCO *colors,
158					       VisualPtr pVisual);
159
160        Bool                    (*CloseScreen)(int, ScreenPtr);
161
162	unsigned char		*imageBuffer;
163	int			imageWidth;
164	int			imageHeight;
165	Bool			hwCursor;
166
167	Bool                    shadowFB;
168	int                     rotate;
169	unsigned char           * ShadowPtr;
170	int                     ShadowPitch;
171	void	                (*PointerMoved)(int index, int x, int y);
172
173} S3Rec, *S3Ptr;
174
175#define S3PTR(p)		((S3Ptr)((p)->driverPrivate))
176
177
178#define DRIVER_NAME     "s3"
179#define DRIVER_VERSION  PACKAGE_VERSION
180#define VERSION_MAJOR   PACKAGE_VERSION_MAJOR
181#define VERSION_MINOR   PACKAGE_VERSION_MINOR
182#define PATCHLEVEL      PACKAGE_VERSION_PATCHLEVEL
183#define S3_VERSION     ((VERSION_MAJOR << 24) | \
184                        (VERSION_MINOR << 16) | PATCHLEVEL)
185
186
187
188
189/*
190 * Prototypes
191 */
192
193Bool S3AccelInit(ScreenPtr pScreen);
194Bool S3AccelInitNewMMIO(ScreenPtr pScreen);
195Bool S3AccelInitPIO(ScreenPtr pScreen);
196Bool S3DGAInit(ScreenPtr pScreen);
197Bool S3SwitchMode(int scrnIndex, DisplayModePtr mode, int flags);
198int S3GetRefClock(ScrnInfoPtr pScrn);
199
200void S3InitVideo(ScreenPtr pScreen);
201void S3InitStreams(ScrnInfoPtr pScrn, DisplayModePtr mode);
202
203/* IBMRGB */
204extern RamDacSupportedInfoRec S3IBMRamdacs[];
205Bool S3ProbeIBMramdac(ScrnInfoPtr pScrn);
206void S3IBMRGB_PreInit(ScrnInfoPtr pScrn);
207void S3IBMRGB_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
208void S3IBMRGB_Save(ScrnInfoPtr pScrn);
209void S3IBMRGB_Restore(ScrnInfoPtr pScrn);
210Bool S3IBMRGB_CursorInit(ScreenPtr pScreen);
211
212/* TRIO64 */
213Bool S3Trio64DACProbe(ScrnInfoPtr pScrn);
214void S3Trio64DAC_PreInit(ScrnInfoPtr pScrn);
215void S3Trio64DAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
216void S3Trio64DAC_Save(ScrnInfoPtr pScrn);
217void S3Trio64DAC_Restore(ScrnInfoPtr pScrn);
218
219/* Ti */
220Bool S3TiDACProbe(ScrnInfoPtr pScrn);
221void S3TiDAC_PreInit(ScrnInfoPtr pScrn);
222void S3TiDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
223void S3TiDAC_Save(ScrnInfoPtr pScrn);
224void S3TiDAC_Restore(ScrnInfoPtr pScrn);
225void S3TiLoadPalette(ScrnInfoPtr pScrn, int numColors, int *indicies, LOCO *colors,
226		     VisualPtr pVisual);
227Bool S3Ti_CursorInit(ScreenPtr pScreen);
228void S3OutTiIndReg(ScrnInfoPtr pScrn, CARD32 reg, unsigned char mask,
229		   unsigned char data);
230
231/* SDAC/GENDAC */
232Bool S3SDACProbe(ScrnInfoPtr pScrn);
233void S3GENDAC_PreInit(ScrnInfoPtr pScrn);
234void S3GENDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
235void S3SDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode);
236void S3GENDAC_Save(ScrnInfoPtr pScrn);
237void S3GENDAC_Restore(ScrnInfoPtr pScrn);
238
239/* s3 gen cursor */
240Bool S3_CursorInit(ScreenPtr pScreen);
241
242/* in s3_shadow.c */
243void S3PointerMoved(int index, int x, int y);
244void S3RefreshArea(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
245void S3RefreshArea8(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
246void S3RefreshArea16(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
247void S3RefreshArea24(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
248void S3RefreshArea32(ScrnInfoPtr pScrn, int num, BoxPtr pbox);
249
250Bool S3GENDACProbe(ScrnInfoPtr pScrn);
251
252
253#define TRIO64_RAMDAC	0x8811
254#define	TI3025_RAMDAC	0x3025
255#define	TI3020_RAMDAC	0x3020
256#define	GENDAC_RAMDAC	0x0708
257#define	SDAC_RAMDAC	0x0716
258
259#define BIOS_BSIZE	1024
260#define	BIOS_BASE	0xc0000
261
262/*
263 * Chip...Sets...
264 */
265
266#define S3_864_SERIES()		((pS3->Chipset == PCI_CHIP_864_0) ||	\
267				 (pS3->Chipset == PCI_CHIP_864_1))
268#define S3_964_SERIES()		((pS3->Chipset == PCI_CHIP_964_0) ||	\
269			 	 (pS3->Chipset == PCI_CHIP_964_1))
270
271#define	S3_TRIO_SERIES()	((pS3->Chipset == PCI_CHIP_TRIO) ||	\
272			 	 (pS3->Chipset == PCI_CHIP_AURORA64VP) || \
273				 (pS3->Chipset == PCI_CHIP_TRIO64UVP) || \
274				 (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX))
275#endif /* _S3_H */
276