1/*
2 * Copyright (c) 2009 KIYOHARA Takashi
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include "xf86.h"
32#include "xf86_OSproc.h"
33#include <X11/Xos.h>
34
35#include "compiler.h"
36
37#include "s3.h"
38
39#define GENDAC_INDEX		0x3C8
40#define GENDAC_DATA		0x3C9
41
42
43static void S3GENDACSetClock(ScrnInfoPtr, long, int, int, int, int, int, int,
44			     int, long, long);
45static void S3GENDACCalcClock(long, int, int, int, int, int, long, long,
46			      unsigned char *, unsigned char *);
47static void S3GENDACSetPLL(ScrnInfoPtr, int, unsigned char, unsigned char);
48
49
50static void xf86dactopel(void);
51
52static void
53xf86dactopel()
54{
55	outb(0x3C8,0);
56	return;
57}
58
59
60Bool S3GENDACProbe(ScrnInfoPtr pScrn)
61{
62	/* probe for S3 GENDAC/SDAC */
63	/*
64	 * S3 GENDAC and SDAC have two fixed read only PLL clocks
65	 *     CLK0 f0: 25.255MHz   M-byte 0x28  N-byte 0x61
66	 *     CLK0 f1: 28.311MHz   M-byte 0x3d  N-byte 0x62
67	 * which can be used to detect GENDAC and SDAC since there is no chip-id
68	 * for the GENDAC.
69	 *
70	 * NOTE: for the GENDAC on a MIRO 10SD (805+GENDAC) reading PLL values
71	 * for CLK0 f0 and f1 always returns 0x7f
72	 * (but is documented "read only")
73	 */
74
75	S3Ptr pS3 = S3PTR(pScrn);
76	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
77	unsigned char saveCR55, saveCR45, saveCR43, savelut[6];
78	unsigned int i;		/* don't use signed int, UW2.0 compiler bug */
79	long clock01, clock23;
80	int found = 0;
81
82	if (!S3_864_SERIES())	/* need? */
83		return FALSE;
84
85	outb(vgaCRIndex, 0x43);
86	saveCR43 = inb(vgaCRReg);
87	outb(vgaCRReg, saveCR43 & ~0x02);
88
89	outb(vgaCRIndex, 0x45);
90	saveCR45 = inb(vgaCRReg);
91	outb(vgaCRReg, saveCR45 & ~0x20);
92
93	outb(vgaCRIndex, 0x55);
94	saveCR55 = inb(vgaCRReg);
95	outb(vgaCRReg, saveCR55 & ~1);
96
97	outb(0x3c7,0);
98	for(i = 0; i < 2 * 3; i++)	/* save first two LUT entries */
99		savelut[i] = inb(0x3c9);
100	outb(0x3c8,0);
101	for(i = 0; i < 2 * 3; i++)	/* set first two LUT entries to zero */
102		outb(0x3c9, 0);
103
104	outb(vgaCRIndex, 0x55);
105	outb(vgaCRReg, saveCR55 | 1);
106
107	outb(0x3c7,0);
108	for(i = clock01 = 0; i < 4; i++)
109		clock01 = (clock01 << 8) | (inb(0x3c9) & 0xff);
110	for(i = clock23 = 0; i < 4; i++)
111		clock23 = (clock23 << 8) | (inb(0x3c9) & 0xff);
112
113	outb(vgaCRIndex, 0x55);
114	outb(vgaCRReg, saveCR55 & ~1);
115
116	outb(0x3c8,0);
117	for(i = 0; i < 2 * 3; i++)	/* restore first two LUT entries */
118		outb(0x3c9, savelut[i]);
119
120	outb(vgaCRIndex, 0x55);
121	outb(vgaCRReg, saveCR55);
122
123	if (clock01 == 0x28613d62 ||
124	    (clock01 == 0x7f7f7f7f && clock23 != 0x7f7f7f7f)) {
125		xf86dactopel();
126		inb(0x3c6);
127		inb(0x3c6);
128		inb(0x3c6);
129
130		/* the fourth read will show the SDAC chip ID and revision */
131		if (((i = inb(0x3c6)) & 0xf0) == 0x70)
132			found = SDAC_RAMDAC;
133		else
134			found = GENDAC_RAMDAC;
135		saveCR43 &= ~0x02;
136		saveCR45 &= ~0x20;
137		xf86dactopel();
138	}
139
140	outb(vgaCRIndex, 0x45);
141	outb(vgaCRReg, saveCR45);
142
143	outb(vgaCRIndex, 0x43);
144	outb(vgaCRReg, saveCR43);
145
146	if (found) {
147		RamDacInit(pScrn, pS3->RamDacRec);
148		pS3->RamDac = RamDacHelperCreateInfoRec();
149		pS3->RamDac->RamDacType = found;
150		return TRUE;
151	}
152	return FALSE;
153}
154
155void S3GENDAC_PreInit(ScrnInfoPtr pScrn)
156{
157	S3Ptr pS3 = S3PTR(pScrn);
158	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
159	unsigned char saveCR55;
160	int m, n, n1, n2, mclk;
161
162	outb(vgaCRIndex, 0x55);
163	saveCR55 = inb(vgaCRReg);
164	outb(vgaCRReg, saveCR55 | 1);
165
166	outb(0x3C7, 10); /* read MCLK */
167	m = inb(0x3C9);
168	n = inb(0x3C9);
169
170	outb(vgaCRIndex, 0x55);
171	outb(vgaCRReg, saveCR55);
172
173	m &= 0x7f;
174	n1 = n & 0x1f;
175	n2 = (n >> 5) & 0x03;
176	mclk = ((1431818 * (m + 2)) / (n1 + 2) / (1 << n2) + 50) / 100;
177
178	pS3->mclk = mclk;
179	xf86DrvMsg(pScrn->scrnIndex, X_PROBED, "MCLK %1.3f MHz\n",
180	    mclk / 1000.0);
181}
182
183void S3GENDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode)
184{
185	S3Ptr pS3 = S3PTR(pScrn);
186	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
187	int daccomm = 0;	/* GENDAC command */
188	unsigned char blank, tmp;
189
190	S3GENDACSetClock(pScrn, mode->Clock * (pScrn->depth >> 3), 2, 1, 1, 31,
191	    0, 3, 1, 100000, 250000);
192
193	outb(0x3C4, 1);
194	blank = inb(0x3C5);
195	outb(0x3C5, blank | 0x20); /* blank the screen */
196
197	switch (pScrn->depth)
198	{
199	case 8:		/* 8-bit color, 1VCLK/pixel */
200		break;
201
202	case 15:	/* 15-bit color, 2VCLK/pixel */
203		daccomm = 0x20;
204		break;
205
206	case 16:	/* 16-bit color, 2VCLK/pixel */
207		daccomm = 0x60;
208		break;
209
210	case 32:	/* 32-bit color, 3VCLK/pixel */
211		daccomm = 0x40;
212	}
213
214	outb(vgaCRIndex, 0x55);
215	tmp = inb(vgaCRReg) | 1;
216	outb(vgaCRReg, tmp);
217
218	outb(0x3c6, daccomm);		/* set GENDAC mux mode */
219
220	outb(vgaCRIndex, 0x55);
221	tmp = inb(vgaCRReg) & ~1;
222	outb(vgaCRReg, tmp);
223
224	outb(0x3C4, 1);
225	outb(0x3C5, blank);		/* unblank the screen */
226}
227
228void S3SDAC_Init(ScrnInfoPtr pScrn, DisplayModePtr mode)
229{
230	S3Ptr pS3 = S3PTR(pScrn);
231	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
232	int pixmux = 0;		/* SDAC command and CR67 */
233	int blank_delay = 0;	/* CR6D */
234	int invert_vclk = 0;	/* CR66 bit 0 */
235	unsigned char blank, tmp;
236
237#if 0
238	S3GENDACSetClock(pScrn,
239	    (pScrn->depth == 32) ? mode->Clock * 2 : mode->Clock,
240	    2, 1, 1, 31, 0, 3, 1, 100000, 250000);
241#else
242	/* XXXX: for prep */
243	long freq;
244
245	switch (pScrn->depth) {
246	case 32:
247		freq = mode->Clock * 2;	/* XXXX: frem xfree86 3.x */
248		break;
249	case 16:
250		freq = mode->Clock / 2;
251		break;
252	default:
253		freq = mode->Clock;
254		break;
255	}
256	S3GENDACSetClock(pScrn, freq,
257	    2, 1, 1, 31, 0, 3, 1, 100000, 250000);
258#endif
259
260	outb(vgaCRIndex, 0x42);/* select the clock */
261	tmp = inb(vgaCRReg) & 0xf0;
262	outb(vgaCRReg, tmp | 0x02);
263	usleep(150000);
264
265	outb(0x3C4, 1);
266	blank = inb(0x3C5);
267	outb(0x3C5, blank | 0x20); /* blank the screen */
268
269	switch (pScrn->depth)
270	{
271	case 8:		/* 8-bit color, 1 VCLK/pixel */
272		pixmux = 0x10;
273		blank_delay = 2;
274		invert_vclk = 1;
275		break;
276
277	case 15:	/* 15-bit color, 1VCLK/pixel */
278		pixmux = 0x30;
279		blank_delay = 2;
280		break;
281
282	case 16:	/* 16-bit color, 1VCLK/pixel */
283		pixmux = 0x50;
284		blank_delay = 2;
285		break;
286
287	case 32:	/* 32-bit color, 2VCLK/pixel */
288		pixmux = 0x70;
289		blank_delay = 2;
290	}
291
292	outb(vgaCRIndex, 0x55);
293	tmp = inb(vgaCRReg) | 1;
294	outb(vgaCRReg, tmp);
295
296	outb(vgaCRIndex, 0x67);
297	outb(vgaCRReg, pixmux | invert_vclk);	/* set S3 mux mode */
298	outb(0x3c6, pixmux);			/* set SDAC mux mode */
299
300	outb(vgaCRIndex, 0x6D);
301	outb(vgaCRReg, blank_delay);		/* set blank delay */
302
303	outb(vgaCRIndex, 0x55);
304	tmp = inb(vgaCRReg) & ~1;
305	outb(vgaCRReg, tmp);
306
307	outb(0x3C4, 1);
308	outb(0x3C5, blank);			/* unblank the screen */
309}
310
311void S3GENDAC_Save(ScrnInfoPtr pScrn)
312{
313	S3Ptr pS3 = S3PTR(pScrn);
314	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
315	S3RegPtr save = &pS3->SavedRegs;
316	unsigned char tmp;
317
318	outb(vgaCRIndex, 0x55);
319	tmp = inb(vgaCRReg);
320	outb(vgaCRReg, tmp | 1);
321
322	save->dacregs[0] = inb(0x3c6);	/* Enhanced command register */
323	save->dacregs[2] = inb(0x3c8);	/* PLL write index */
324	save->dacregs[1] = inb(0x3c7);	/* PLL read index */
325	outb(0x3c7, 2);		/* index to f2 reg */
326	save->dacregs[3] = inb(0x3c9);	/* f2 PLL M divider */
327	save->dacregs[4] = inb(0x3c9);	/* f2 PLL N1/N2 divider */
328	outb(0x3c7, 0x0e);	/* index to PLL control */
329	save->dacregs[5] = inb(0x3c9);	/* PLL control */
330
331	outb(vgaCRReg, tmp & ~1);
332}
333
334void S3GENDAC_Restore(ScrnInfoPtr pScrn)
335{
336	S3Ptr pS3 = S3PTR(pScrn);
337	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
338	S3RegPtr restore = &pS3->SavedRegs;
339	unsigned char tmp;
340
341	outb(vgaCRIndex, 0x55);
342	tmp = inb(vgaCRReg);
343	outb(vgaCRReg, tmp | 1);
344
345	outb(0x3c6, restore->dacregs[0]);	/* Enhanced command register */
346	outb(0x3c8, 2);			/* index to f2 reg */
347	outb(0x3c9, restore->dacregs[3]);	/* f2 PLL M divider */
348	outb(0x3c9, restore->dacregs[4]);	/* f2 PLL N1/N2 divider */
349	outb(0x3c8, 0x0e);		/* index to PLL control */
350	outb(0x3c9, restore->dacregs[5]);	/* PLL control */
351	outb(0x3c8, restore->dacregs[2]);	/* PLL write index */
352	outb(0x3c7, restore->dacregs[1]);	/* PLL read index */
353
354	outb(vgaCRReg, tmp & ~1);
355}
356
357static void
358S3GENDACSetClock(ScrnInfoPtr pScrn, long freq, int clk, int min_m, int min_n1,
359	       int max_n1, int min_n2, int max_n2, int pll_type, long freq_min,
360	       long freq_max)
361{
362	unsigned char m, n;
363
364	S3GENDACCalcClock(freq, min_m, min_n1, max_n1, min_n2, max_n2,
365	    freq_min, freq_max, &m, &n);
366
367	/* XXX for pll_type == GENDAC */
368	S3GENDACSetPLL(pScrn, clk, m, n);
369}
370
371/* This function is copy from S3GENDACCalcClock() */
372static void
373S3GENDACCalcClock(long freq, int min_m, int min_n1, int max_n1, int min_n2,
374		  int max_n2, long freq_min, long freq_max,
375		  unsigned char *mdiv, unsigned char *ndiv)
376{
377	double ffreq, ffreq_min, ffreq_max;
378	double div, diff, best_diff;
379	unsigned int m;
380	unsigned char n1, n2, best_n1=18, best_n2=2, best_m=127;
381
382#define BASE_FREQ	14.31818
383	ffreq = freq / 1000.0 / BASE_FREQ;
384	ffreq_min = freq_min / 1000.0 / BASE_FREQ;
385	ffreq_max = freq_max / 1000.0 / BASE_FREQ;
386
387	if (ffreq < ffreq_min / (1 << max_n2)) {
388		ErrorF("invalid frequency %1.3f Mhz [freq >= %1.3f Mhz]\n",
389		    ffreq*BASE_FREQ, ffreq_min*BASE_FREQ / (1 << max_n2));
390		ffreq = ffreq_min / (1 << max_n2);
391	}
392	if (ffreq > ffreq_max / (1 << min_n2)) {
393		ErrorF("invalid frequency %1.3f Mhz [freq <= %1.3f Mhz]\n",
394		    ffreq*BASE_FREQ, ffreq_max*BASE_FREQ / (1 << min_n2));
395		ffreq = ffreq_max / (1<<min_n2);
396	}
397
398	/* work out suitable timings */
399
400	best_diff = ffreq;
401
402	for (n2 = min_n2; n2 <= max_n2; n2++) {
403		for (n1 = min_n1 + 2; n1 <= max_n1 + 2; n1++) {
404			m = (int)(ffreq * n1 * (1 << n2) + 0.5);
405			if (m < min_m + 2 || m > 127 + 2)
406				continue;
407			div = (double)(m) / (double)(n1);
408			if ((div >= ffreq_min) && (div <= ffreq_max)) {
409				diff = ffreq - div / (1 << n2);
410				if (diff < 0.0)
411					diff = -diff;
412				if (diff < best_diff) {
413					best_diff = diff;
414					best_m = m;
415					best_n1 = n1;
416					best_n2 = n2;
417				}
418			}
419		}
420	}
421
422	if (max_n1 == 63)
423		*ndiv = (best_n1 - 2) | (best_n2 << 6);
424	else
425		*ndiv = (best_n1 - 2) | (best_n2 << 5);
426	*mdiv = best_m - 2;
427}
428
429static void
430S3GENDACSetPLL(ScrnInfoPtr pScrn, int clk, unsigned char m, unsigned char n)
431{
432	S3Ptr pS3 = S3PTR(pScrn);
433	unsigned char tmp, tmp1;
434	int vgaCRIndex = pS3->vgaCRIndex, vgaCRReg = pS3->vgaCRReg;
435
436	/* set RS2 via CR55, yuck */
437	outb(vgaCRIndex, 0x55);
438	tmp = inb(vgaCRReg) & 0xFC;
439	outb(vgaCRReg, tmp | 0x01);
440	tmp1 = inb(GENDAC_INDEX);
441
442	outb(GENDAC_INDEX, clk);
443	outb(GENDAC_DATA, m);
444	outb(GENDAC_DATA, n);
445
446	/* Now clean up our mess */
447	outb(GENDAC_INDEX, tmp1);
448	outb(vgaCRReg, tmp);
449}
450