1 2#ifndef _S3_REG_H 3#define _S3_REG_H 4 5#include "compiler.h" 6 7extern short s3alu[16]; 8 9#define S3_NEWMMIO_REGBASE 0x1000000 /* 16MB */ 10#define S3_NEWMMIO_REGSIZE 0x10000 /* 64KB */ 11 12#define ADVFUNC_CNTL 0x4ae8 13#define SUBSYS_STAT 0x42e8 14#define SUBSYS_CNTL 0x42e8 15#define CUR_Y 0x82e8 16#define CUR_X 0x86e8 17#define CUR_Y2 0x82ea 18#define CUR_X2 0x86ea 19#define DESTY_AXSTP 0x8ae8 20#define DESTX_DIASTP 0x8ee8 21#define DESTY_AXSTP2 0x8aea 22#define DESTX_DIASTP2 0x8eea 23#define ERR_TERM 0x92e8 24#define ERR_TERM2 0x92ea 25#define MAJ_AXIS_PCNT 0x96e8 26#define MAJ_AXIS_PCNT2 0x96ea 27#define GP_STAT 0x9ae8 28#define CMD 0x9ae8 29#define CMD2 0x9aea 30#define BKGD_COLOR 0xa2e8 31#define FRGD_COLOR 0xa6e8 32#define WRT_MASK 0xaae8 33#define RD_MASK 0xaee8 34#define COLOR_CMP 0xb2e8 35#define BKGD_MIX 0xb6e8 36#define FRGD_MIX 0xbae8 37#define MULTIFUNC_CNTL 0xbee8 38#define PIX_TRANS 0xe2e8 39#define PIX_TRANS_EXT 0xe2ea 40 41/* Graphics Processor Status Register */ 42#define GPBUSY 0x0200 43 44/* Command Register */ 45#define CMD_NOP 0x0000 46#define CMD_LINE 0x2000 47#define CMD_RECT 0x4000 48#define CMD_RECTV1 0x6000 49#define CMD_RECTV2 0x8000 50#define CMD_LINEAF 0xa000 51#define CMD_BITBLT 0xc000 52#define CMD_PFILL 0xe000 53#define CMD_OP_MSK 0xf000 54#define BYTSEQ 0x1000 55#define _16BIT 0x0200 56#define _32BIT 0x0400 57#define PCDATA 0x0100 58#define INC_Y 0x0080 59#define YMAJAXIS 0x0040 60#define INC_X 0x0020 61#define DRAW 0x0010 62#define LINETYPE 0x0008 63#define LASTPIX 0x0004 64#define PLANAR 0x0002 65#define WRTDATA 0x0001 66 67 68/* Background Mix Register */ 69#define BSS_BKGDCOL 0x0000 70#define BSS_FRGDCOL 0x0020 71#define BSS_PCDATA 0x0040 72#define BSS_BITBLT 0x0060 73 74/* Foreground Mix Register */ 75#define FSS_BKGDCOL 0x0000 76#define FSS_FRGDCOL 0x0020 77#define FSS_PCDATA 0x0040 78#define FSS_BITBLT 0x0060 79 80#define PIX_CNTL 0xa000 81#define MIN_AXIS_PCNT 0x0000 82 83/* Pixel Control Register */ 84#define MIXSEL_EXPPC 0x0080 85 86#define SCISSORS_T 0x1000 87#define SCISSORS_L 0x2000 88#define SCISSORS_B 0x3000 89#define SCISSORS_R 0x4000 90#define MULT_MISC2 0xd000 91#define MULT_MISC 0xe000 92 93 94#define MIX_MASK 0x001f 95 96#define MIX_NOT_DST 0x0000 97#define MIX_0 0x0001 98#define MIX_1 0x0002 99#define MIX_DST 0x0003 100#define MIX_NOT_SRC 0x0004 101#define MIX_XOR 0x0005 102#define MIX_XNOR 0x0006 103#define MIX_SRC 0x0007 104#define MIX_NAND 0x0008 105#define MIX_NOT_SRC_OR_DST 0x0009 106#define MIX_SRC_OR_NOT_DST 0x000a 107#define MIX_OR 0x000b 108#define MIX_AND 0x000c 109#define MIX_SRC_AND_NOT_DST 0x000d 110#define MIX_NOT_SRC_AND_DST 0x000e 111#define MIX_NOR 0x000f 112 113#define MIX_MIN 0x0010 114#define MIX_DST_MINUS_SRC 0x0011 115#define MIX_SRC_MINUS_DST 0x0012 116#define MIX_PLUS 0x0013 117#define MIX_MAX 0x0014 118#define MIX_HALF__DST_MINUS_SRC 0x0015 119#define MIX_HALF__SRC_MINUS_DST 0x0016 120#define MIX_AVERAGE 0x0017 121#define MIX_DST_MINUS_SRC_SAT 0x0018 122#define MIX_SRC_MINUS_DST_SAT 0x001a 123#define MIX_HALF__DST_MINUS_SRC_SAT 0x001c 124#define MIX_HALF__SRC_MINUS_DST_SAT 0x001e 125#define MIX_AVERAGE_SAT 0x001f 126 127/* 128 * Short Stroke Vector Transfer Register (The angular Defs also apply to 129the 130 * Command Register 131 */ 132#define VECDIR_000 0x0000 133#define VECDIR_045 0x0020 134#define VECDIR_090 0x0040 135#define VECDIR_135 0x0060 136#define VECDIR_180 0x0080 137#define VECDIR_225 0x00a0 138#define VECDIR_270 0x00c0 139#define VECDIR_315 0x00e0 140#define SSVDRAW 0x0010 141 142/* 143 * Some values for Streams FIFO. 144 * primary stream threshold | secondary stream threshold | 145 * secondary stream slots (can be 0, 8, 12, 16, 24) from 24 total 146 */ 147#define FIFO_PS0_SS24 (0 << 10) | (12 << 5) | 24 148#define FIFO_PS8_SS16 (8 << 10) | (12 << 5) | 16 149#define FIFO_PS12_SS12 (6 << 10) | (8 << 5) | 12 150#define FIFO_PS16_SS8 (8 << 10) | (4 << 5) | 8 151#define FIFO_PS24_SS0 (12 << 10) | (0 << 5) | 0 152 153#define S3_OUTW(p,n) outw(p, n) 154#define S3_OUTL(p,n) outl(p, n) 155#define S3_OUTW32(p,n) if (pS3->s3Bpp > 2) { \ 156 outw(p, n); \ 157 outw(p, (n) >> 16); \ 158 } else outw(p, n) 159 160 161#define WaitIdle() do { \ 162 mem_barrier(); \ 163 while(inw(GP_STAT) & GPBUSY); \ 164 } while(0) 165 166#define WaitVSync() { \ 167 while (inb(0x3da) & 8); \ 168 while (!(inb(0x3da) & 8)); \ 169} 170 171#ifdef S3_NEWMMIO 172#include "newmmio.h" 173 174/* 175 * streams regs 176 */ 177#define SET_BLEND_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.blend_cntl = (val) 178#define SET_PSTREAM_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_stream_cntl = (val) 179#define SET_PSTREAM_FBADDR0(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_fbaddr0 = (val) 180#define SET_PSTREAM_FBADDR1(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_fbaddr1 = (val) 181#define SET_PSTREAM_STRIDE(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_stream_stride = (val) 182#define SET_PSTREAM_START(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_start_coord = (val) 183#define SET_PSTREAM_WIND(val) ((mmtr)s3MmioMem)->streams_regs.regs.prim_window_size = (val) 184#define SET_SSTREAM_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_stream_cntl = (val) 185#define SET_SSTRETCH(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_stream_stretch = (val) 186#define SET_SSTREAM_FBADDR0(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_fbaddr0 = (val) 187#define SET_SSTREAM_FBADDR1(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_fbaddr1 = (val) 188#define SET_SSTREAM_STRIDE(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_stream_stride = (val) 189#define SET_SSTREAM_START(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_start_coord = (val) 190#define SET_SSTREAM_WIND(val) ((mmtr)s3MmioMem)->streams_regs.regs.second_window_size = (val) 191#define SET_K1_VSCALE(val) ((mmtr)s3MmioMem)->streams_regs.regs.k1 = (val) 192#define SET_K2_VSCALE(val) ((mmtr)s3MmioMem)->streams_regs.regs.k2 = (val) 193#define SET_DDA_VERT(val) ((mmtr)s3MmioMem)->streams_regs.regs.dda_vert = (val) 194#define SET_CHROMA_KEY(val) ((mmtr)s3MmioMem)->streams_regs.regs.col_chroma_key_cntl = (val) 195#define SET_DOUBLE_BUFFER(val) ((mmtr)s3MmioMem)->streams_regs.regs.double_buffer = (val) 196#define SET_OPAQUE_OVERLAY(val) ((mmtr)s3MmioMem)->streams_regs.regs.opaq_overlay_cntl = (val) 197#define SET_FIFO_CNTL(val) ((mmtr)s3MmioMem)->streams_regs.regs.streams_fifo = (val) 198 199#else 200 201#define CMD_REG_WIDTH 0x0000 202 203#define WaitQueue(n) do { \ 204 mem_barrier(); \ 205 while(inb(GP_STAT) & (0x0100 >> (n))); \ 206 } while (0) 207 208#define WaitQueue16_32(n16,n32) \ 209 if (pS3->s3Bpp <= 2) { \ 210 WaitQueue(n16); \ 211 } else { \ 212 WaitQueue(n32); \ 213 } 214 215#define VerticalRetraceWait() \ 216 { \ 217 outb(vgaCRIndex, 0x17); \ 218 if (inb(vgaCRReg) & 0x80) { \ 219 while ((inb(vgaCRIndex-4+0x0a) & 0x08) == 0x00); \ 220 while ((inb(vgaCRIndex-4+0x0a) & 0x08) == 0x08); \ 221 } \ 222 } 223 224/* accel commands */ 225 226#define SET_PIX_CNTL(val) S3_OUTW(MULTIFUNC_CNTL, PIX_CNTL | (val)) 227 228#define SET_FRGD_COLOR(col) S3_OUTW32(FRGD_COLOR, col) 229#define SET_BKGD_COLOR(col) S3_OUTW32(BKGD_COLOR, col) 230 231#define SET_FRGD_MIX(fmix) S3_OUTW(FRGD_MIX, (fmix)) 232#define SET_WRT_MASK(mask) S3_OUTW32(WRT_MASK, mask) 233 234#define SET_CUR_X(cur_x) S3_OUTW(CUR_X, cur_x) 235#define SET_CUR_Y(cur_y) S3_OUTW(CUR_Y, cur_y) 236#define SET_CUR_X2(cur_x) S3_OUTW(CUR_X2, cur_x) 237#define SET_CUR_Y2(cur_y) S3_OUTW(CUR_Y2, cur_y) 238 239#define SET_CURPT(cur_x, cur_y) { \ 240 SET_CUR_X(cur_x); \ 241 SET_CUR_Y(cur_y); \ 242 } 243 244#define SET_DESTSTP(x,y) { \ 245 S3_OUTW(DESTX_DIASTP, x); \ 246 S3_OUTW(DESTY_AXSTP, y); \ 247 } 248 249#define SET_AXIS_PCNT(maj, min) { \ 250 S3_OUTW(MAJ_AXIS_PCNT, maj); \ 251 S3_OUTW(MULTIFUNC_CNTL, MIN_AXIS_PCNT | (min)); \ 252 } 253 254#define SET_CMD(cmd) S3_OUTW(CMD, cmd) 255 256#define SET_SCISSORS(x1,y1,x2,y2) { \ 257 S3_OUTW(MULTIFUNC_CNTL, SCISSORS_T | (y1)); \ 258 S3_OUTW(MULTIFUNC_CNTL, SCISSORS_L | (x1)); \ 259 S3_OUTW(MULTIFUNC_CNTL, SCISSORS_R | (x2)); \ 260 S3_OUTW(MULTIFUNC_CNTL, SCISSORS_B | (y2)); \ 261 } 262 263#define SET_MULT_MISC(val) S3_OUTW(MULTIFUNC_CNTL, MULT_MISC | (val)) 264 265#define SET_COLOR_CMP(color) S3_OUTW32(COLOR_CMP, color) 266 267#define SET_PIX_TRANS_W(val) S3_OUTW(PIX_TRANS, val) 268 269#define SET_PIX_TRANS_L(val) outl(PIX_TRANS, val) 270 271#define SET_ERR_TERM(err) S3_OUTW(ERR_TERM, err) 272#define SET_ERR_TERM2(err) S3_OUTW(ERR_TERM2, err) 273 274#define SET_MAJ_AXIS_PCNT(maj) S3_OUTW(MAJ_AXIS_PCNT, maj) 275#endif 276 277 278#endif /* _S3_REG_H */ 279